Datasheet UT62L2568LS-70LLL, UT62L2568LS-70LLE, UT62L2568LS-70LE, UT62L2568LS-70L, UT62L2568LS-55LLL Datasheet (UTRON)

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

1



FEATURES



Access time:55ns(max) for Vcc=3.0V~3.6V

70/100ns(max) for Vcc=2.7V~3.6V



CMOS Low operating power

Operating : 45/35/25mA (Icc max)
Standby : 20µA (TYP.) L-version

3µA (TYP.) LL-version



Single 2.7V~3.6V power supply



Operating Temperature:
Commercial : 0℃~70℃
Extended : -20℃~80℃



All inputs and outputs TTL compatible



Fully static operation



Three state outputs



Data retention voltage : 1.5V (min)



Package : 32 pin 8mm×20 mm TSOP-I

32 pin 8mm×13.4mm STSOP

36 pin 6mm×8mmTFBGA

FUNCTIONAL BLOCK DIAGRAM

COLUMN I/O

COLUMN DECODER

ROW

DECODER

I/O

CONTROL

LOGI C

CONTROL

A1

I/O1

VSS

VCC

WE

OE

1CE

I/O8

.

.

.

.

.
.

. .

.

A2

A3 A4 A

8

A13

A14

A15

A16

A

11

A5 A6 A

10

.

.

.

.

.

.

MEMORY ARRAY

2048 ROWS × 128 COLUMNS × 8bit s

A

12

A7 A

9

A

17

A

0

CE2

GENERAL DESCRIPTION

The UT62L2568 is a 2,097,152-bit high speed
CMOS static random access memory organized as
262,144 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.

The UT62L2568 is designed for high speed system
applications. It is particularly well suited for battery
back-up nonvolatile memory applications.

The UT62L2568 operates from a single 2.7V~3.6V
power supply and all inputs and outputs are fully
TTL compatible.

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A17 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs

1CE

,CE2

Chip Enable 1,2 Input

WE

Write Enable Input

OE

Output Enable Input

Vcc Power Supply
Vss Ground
NC No Connection

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

2



PIN CONFIGURATION

I/O4

A11

A9
A8

A13

I/O3

A10

A14
A12

A7
A6
A5

Vcc

I/O8
I/O7

I/O6
I/O5

Vss

I/O2
I/O1

A0
A1

A2

A4 A3

UT62L2568

TSOP-1/STSOP

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20
19
18

22

23

24

25

26

27

21

WE

OE

1CE

CE2

A17

A15

32
31
30
29

A16

OE

1CE

WE

A12A11 A13

CE2

NC

A10 A14

A15

I/O6

I/O7

I/O8

A9

Vss

A8

A16

I/O5

Vcc

Vcc

I/O4

A17

Vss

A7

A0

I/O3

I/O2

I/O1

A6A1 A3

A5NC

A4A2

123456

H

G

C

D

E

F

A

B

TFBGA

TRUTH TABLE

MODE

1CE

CE2

OE

WE

I/O OPERATION SUPPLY CURRENT

Standby H X X X High - Z

I

SB

,

I

SB1

Standby X L X X High -Z

I

SB

,

I

SB1

Output Disable L H H H High - Z

I

CC

Read L H L H

D

OUT

I

CC

Write L H X L

D

IN

I

CC

Note: H = VIH, L=VIL, X = Don't care.

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

3



ABSOLUTE MAXIMUM RATINGS

*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS V

TERM

-0.5 to 4.6 V

Commercial TA 0 to 70

℃

Operating Temperature

Extended T

A

-20 to 80

℃

Storage Temperature T

STG

-65 to 150

℃

Power Dissipation PD 1 W
DC Output Current I

OUT

50 mA

Soldering Temperature (under 10 secs) Tsolder 260

℃

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this

specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V~3.6V, TA =0℃ to 70℃ / -20℃ to 80℃(E))

PARAMETER

SYMBOL

TEST CONDITION MIN. TYP. MAX. UNIT

Power Voltage Vcc 2.7 3.0 3.6 V
Input High Voltage VIH 2.0 - Vcc+0.3 V
Input Low Voltage VIL - 0.2 - 0.6 V
Input Leakage Current ILI

V

SS

≦VIN ≦VCC

- 1 - 1

µ

A

Output Leakage Current ILO

V

SS

≦V

I/O

≦V

CC,

Output Disabled

- 1 - 1

µ

A
Output High Voltage VOH IOH= - 1mA 2.2 - - V
Output Low Voltage VOL IOL= 2mA - - 0.4 V

55 - 30 45 mA
70 - 25 35 mA

ICC Cycle time=Min.100% duty,

1CE

=V

IL

, CE2 = VIH, I

I/O

=0mA ,

100 - 20 25 mA

Icc1

Cycle time = 1µs,100% duty,

1CE

≦

0.2V,CE2≧V

CC

-0.2V,

I

I/O=

0mA,

other pins at 0.2V or Vcc-0.2V,

- 4 5 mA

Operating Power

Supply Current

Icc2 Cycle time =500ns,100% duty,

1CE

≦

0.2V,CE2≧V

CC

-0.2V,

I

I/O=

0mA,

other pins at 0.2V or Vcc-0.2V,

- 8 10 mA

Standby Current(TTL) I

SB1

1CE

=V

IH

or CE2 = VIL

- 0.3 0.5 mA

-L - 20 80 µA Standby Current(CMOS) I

SB1

1CE

≧

V

CC

-0.2V or .CE2≦0.2V,

other pins at 0.2V or Vcc-0.2V,

-LL - 3 25 µA

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

4



CAPACITANCE

(TA=25℃, f=1.0MHz)

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C

IN

-

6 pF

Input/Output Capacitance C

I/O

-

8 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(VCC = 2.7V~3.6V , TA =0℃ to 70℃ / -20℃ to 80℃(E))

(1) READ CYCLE

PARAMETER SYMBOL UT62L2568-55* UT62L2568-70 UT62L2568-100

UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

tRC 55 - 70 - 100 - ns

Address Access Time

tAA - 55 - 70 - 100 ns

Chip Enable Access Time

t

ACE1, tACE2

- 55 - 70 - 100 ns

Output Enable Access Time

tOE - 30 - 35 - 50 ns

Chip Enable to Output in Low Z

t

CLZ1*, tCLZ2*

10 - 10 - 10 - ns

Output Enable to Output in Low Z

t

OLZ*

5 - 5 - 5 - ns

Chip Disable to Output in High Z

t

CHZ1*, tCHZ2*

- 20 - 25 - 30 ns

Output Disable to Output in High Z

t

OHZ*

- 20 - 25 - 35 ns

Output Hold from Address Change

tOH 5 - 5 - 5 - ns

(2) WRITE CYCLE

PARAMETER SYMBOL UT62L2568-55* UT62L2568-70 UT62L2568-100

UNIT

MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time

tWC 55 - 70 - 100 - ns

Address Valid to End of Write

tAW 50 - 60 - 80 - ns

Chip Enable to End of Write

t

CW1, tCW2

50 - 60 - 80 - ns

Address Set-up Time

tAS 0 - 0 - 0 - ns

Write Pulse Width

tWP 45 - 55 - 70 - ns

Write Recovery Time

tWR 0 - 0 - 0 - ns

Data to Write Time Overlap

tDW 25 - 30 - 40 - ns

Data Hold from End of Write Time

tDH 0 - 0 - 0 - ns

Output Active from End of Write

t

OW*

5 - 5 - 5 - ns

Write to Output in High Z

t

WHZ*

- 30 - 30 - 40 ns

*These parameters are guaranteed by device characterization, but not production tested.
*55ns for Vcc=3.0V~3.6V

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

5



TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2,4)

t

RC

Address

DOUT Data Valid

t

AA

t

OH

t

OH

READ CYCLE 2

(CE and

OE

Controlled)

(1,3,5,6)

t

RC

t

AA

t

ACE1

t

ACE2

t

OE

t

CHZ1

t

CHZ2

t

OHZ

t

CLZ1

t

CLZ2

t

OH

t

OLZ

HIGH-Z

Data Valid

HIGH-Z

Address

CE1

CE2

OE

Dout

Notes :

1.

WE

is HIGH for read cycle.

2. Device is continuously selected

1CE

=V

IL

and CE2=V

IH.

3. Address must be valid prior to or coincident with

1CE

and CE2 transition; otherwise t

AA

is the limiting parameter.

4.

OE

is low.

5. t

CLZ1

, t

CLZ2

, t

OLZ

, t

CHZ1

, t

CHZ2

and t

OHZ

are specified with CL=5pF. Transition is measured ±500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ1

is less than t

CLZ1

, t

CHZ2

is less than t

CLZ2

, t

OHZ

is less than t

OLZ.

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

6



WRITE CYCLE 1

(WEControlled)

(1,2,3,5)

t WC

t AW

t CW1

t AS

t WP

t WH t OW

t DW t DH

t CW2

t WR

Address

CE1

CE2

WE

Dout

Din

Data Valid

High-Z

(4) (4)

WRITE CYCLE 2

(

CE

Controlled)

(1,2,5)

t WC

t AW

t CW1t AS t WR

t CW2

t WP

t WHZ

t DW

t DH

Data Valid

Address

CE1

CE2

WE

Dout

Din

High-Z

Notes :

1.

WE

or

1CE

must be HIGH or CE2 must be LOW during all address transitions.

2. A write occurs during the overlap of a low

1CE

, a high CE2 and a low

WE

.

3. During a

WE

controlled with write cycle with

OE

LOW, t

WP

must be greater than t

WHZ+tDW

to allow the I/O drivers

to turn off and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

5. If the

1CE

LOW transition occurs simultaneously with or after

WE

LOW transition, the outputs remain in a high

impedance state.

6. t

OW

and t

WHZ

are specified with CL=5pF. Transition is measured ±500mV from steady state.

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

7



DATA RETENTION CHARACTERISTICS

(TA =

0℃ to 70℃ / -20℃ to 80℃(E)

)

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Vcc for Data Retention

V

DR

1CE

≧ V

CC

-0.2V or

CE2 ≤ 0.2V

1.5 - 3.6 V

Data Retention Current

I

DR

Vcc=1.5V

- L - 1 50

µ

A

1CE

≧ V

CC

-0.2V or

CE2 ≤ 0.2V

- LL - 0.5 20

µ

A

Chip Disable to Data

t

CDR

See Data Retention 0 - - ms

Retention Time

Waveforms (below)

Recovery Time

t

R

5 - - ms

DATA RETENTION WAVEFORM

t

CDR

t

R

2.7V

VCC

1CE

V

SS

Date Retention Mode

V

DR

≧ 2.0V

1CE

≧ V

CC

-0.2V

V

IL

V

IL

V

IH

V

IH

CE2 ≤ 0.2V

CE2

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

8



PACKAGE OUTLINE DIMENSION

32 pin 8mm × 20mm TSOP-I Package Outline Dimension

UNIT

SYMBOL

INCH(BASE) MM(REF)

A 0.047 (MAX) 1.20 (MAX)

A1

0.004 ±0.002 0.10 ±0.05

A2

0.039 ±0.002 1.00 ±0.05

b

0.008 + 0.002

- 0.001

0.20 + 0.05

-0.03

c 0.005 (TYP) 0.127 (TYP)

D

0.724 ±0.004 18.40 ±0.10

E

0.315 ±0.004 8.00 ±0.10

e 0.020 (TYP) 0.50 (TYP)

HD

0.787 ±0.008 20.00 ±0.20

L

0.0197 ±0.004 0.50 ±0.10

L1

0.0315 ±0.004 0.08 ±0.10

y 0.003 (MAX) 0.076 (MAX)

Θ

0

o

〜

5

o

0

o

〜

5

o

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

9



32 pin 8mm x 13.4mm STSOP Package Outline Dimension

1

16

17

32

c

L

HD

D

"A"

E

e

12

°

(2x)

12°(2x)

Seating Plane

y

32

17

16

1

c

A2A1

L

A

0.254

0

GAUGE PLANE

12°(2X)

12°(2X)

SEATING PLANE

"A" DATAIL VIEW

L1

b

UNIT

SYMBOL

INCH(BASE) MM(REF)

A 0.049 (MAX) 1.25 (MAX)

A1

0.005 ±0.002 0.130 ±0.05

A2

0.039 ±0.002 1.00 ±0.05

b

0.008 ±0.01 0.20±0.025

c 0.005 (TYP) 0.127 (TYP)

D

0.465 ±0.004 11.80 ±0.10

E

0.315 ±0.004 8.00 ±0.10

e 0.020 (TYP) 0.50 (TYP)

HD

0.528±0.008 13.40 ±0.20.

L

0.0197 ±0.004 0.50 ±0.10

L1

0.0315 ±0.004 0.8 ±0.10

y 0.003 (MAX) 0.076 (MAX)

Θ

0

o

〜

5

o

0

o

〜

5

o

c

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

10



36 pin 6mm×8mm TFBGA Package Outline Dimension

A1 Ball Pad C

orner

A
B
C
D
E
F
G
H

123456

A1 Ball Pad Corner

X

Y

DETAIL A

BOTTOM VIEW ( BALL SIDE )TOP VIEW (DIE VIEW )

8.0

±

0.05

6.0±0.05

1.3755.25

1.125 3.75

0.75

0.75

SIDE VIEW

0.55

±

0.32

±

0.02

0

0.23

±

0.03

1.2 MAX.

Z

DETAIL B

0.05

0.02

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

11



ORDERING INFORMATION

COMMERCIAL TEMPERATURE

PART NO. ACCESS TIME

(ns)

STANDBY CURRENT

(µA) TYP.

PACKAGE

UT62L2568LC-55L 55 20

32 PIN TSOP-Ⅰ

UT62L2568LC-55LL 55 3

32 PIN TSOP-Ⅰ

UT62L2568LC-70L 70 20

32 PIN TSOP-Ⅰ

UT62L2568LC-70LL 70 3

32 PIN TSOP-Ⅰ
UT62L2568LS-55L 55 20 32 PIN STSOP
UT62L2568LS-55LL 55 3 32 PIN STSOP
UT62L2568LS-70L 70 20 32 PIN STSOP
UT62L2568LS-70LL 70 3 32 PIN STSOP
UT62L2568BS-55L 55 20 36 PIN TFBGA
UT62L2568BS-55LL 55 3 36 PIN TFBGA
UT62L2568BS-70L 70 20 36 PIN TFBGA
UT62L2568BS-70LL 70 3 36 PIN TFBGA

EXTENDED TEMPERATURE

PART NO. ACCESS TIME

(ns)

STANDBY CURRENT

(µA) TYP.

PACKAGE

UT62L2568LC-55LE 55 20

32 PIN TSOP-Ⅰ
UT62L2568LC-55LLE 55 3

32 PIN TSOP-Ⅰ
UT62L2568LC-70LE 70 20

32 PIN TSOP-Ⅰ
UT62L2568LC-70LLE 70 3

32 PIN TSOP-Ⅰ
UT62L2568LS-55LE 55 20 32 PIN STSOP
UT62L2568LS-55LLE 55 3 32 PIN STSOP
UT62L2568LS-70LE 70 20 32 PIN STSOP
UT62L2568LS-70LLE 70 3 32 PIN STSOP
UT62L2568BS-55LE 55 20 36 PIN TFBGA
UT62L2568BS-55LLE 55 3 36 PIN TFBGA
UT62L2568BS-70LE 70 20 36 PIN TFBGA
UT62L2568BS-70LLE 70 3 36 PIN TFBGA

UTRON

UT62L2568

Preliminary Rev. 0.1

256K X 8 BIT LOW POWER CMOS SRAM

UTRON TECHNOLOGY INC. P80059
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

12



REVISION HISTORY

REVISION DESCRIPTION DATE

Preliminary Rev. 0.1 Original. Jun 18, 2001