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UT62L25616MC-70LI
Datasheet (UTRON)
12 pgs198.39 Kb0

Datasheet UT62L25616MC-70LLI, UT62L25616MC-70LI, UT62L25616MC-55LLI, UT62L25616MC-55LI, UT62L25616BS-70LLI Datasheet (UTRON)

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Page 1
A
A
A0 A1 A2 A3 A4 A8 A
A
A
A
A
A
A
Rev. 1.1
UTRON
FEATURES
Fast access time : 55/70/100 ns
CMOS Low operating power
Operating current: 45/35/25mA (Icc max)
Standby current: 20 uA(TYP.) L-version
3 uA(TYP.) LL-version
Single 2.7V~3.6V power supply
Operating temperature:
Industrial : -40℃~85℃ All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Data byte control :
Package : 44-pin 400mil TSOPⅡ
48-pin 6mm × 8mm TFBGA
LB
UB
(I/O1~I/O8)
(I/O9~I/O16)
FUNCTIONAL BLOCK DIAGRAM
.
MEMORY ARRAY
2048 Rows x 128 Columns x 16 bits
.
. .
COLUMN I/O
COLUMN DECODER
13
14
15
16
17
I/O1
.
.
I/O16
CE
WE
OE
DECODER
. . .
CONTROL
CONTROL
ROW
I/O
LOGIC
.
.
. . .
VCC
VSS
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L25616(I) is a 4,194,304-bit low power CMOS static random access memory organized as 262,144 words by 16 bits.
The UT62L25616(I) operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are fully TTL compatible.
The UT62L25616(I) is designed for low power system applications. It is particularly suited for use in high-density high-speed system applications.
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A17 Address Inputs I/O1 - I/O16 Data Inputs/Outputs
CE
WE
OE
LB
UB VCC Power Supply VSS Ground NC No Connection
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-Byte Control
High-Byte Control
LB
UB
A9
10 A11
12
5
A7
6
1
Page 2
UTRON
Rev. 1.1
PIN CONFIGURATION
A4 A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
Vcc
Vss I/O5
I/O6
I/O7
I/O8
WE
A17
A16 A15
A14
A13
1
2 3
4
5 6
7
8
9
10 11
12
13
14
15
16 17
18
19 20
21
22 23
UT62L25616(I)
TSOP II
TRUTH TABLE
MODE
Output Disable Read L
Write L
Note: H = VIH, L=VIL, X = Don't care.
CE
OE
H X X X X High – Z High – Z ISB, I X X X H H High – Z High – Z I L L
H X
L L L
L
L
X L L
X
X
256K X 16 BIT LOW POWER CMOS SRAM
A5
44
A6
43 42
A7
41
OE
40
UB
39
LB
I/O16
38
I/O15
37
I/O14
36
35
I/O13
Vss
34
Vcc
33
I/O12
32
I/O11
31
30
I/O10
29
I/O9
28
NC
A8
27
A9
26
A10
25
A11
24
A12
WE
LB
UB
H X H H H
L L L
X H L H L L H L
X H H L L H L L
A
B
C
D
E
F
G
H
LB
I/O9
Vss
Vcc
I/O15 I/O14
I/O16
NC
123456
I/O OPERATION
I/O1-I/O8 I/O9-I/O16
High – Z High – Z
D
OUT
High – Z High – Z High – Z
High – Z
D
OUT
DIN
High – Z
High – Z
D
IN
UT62L25616(I)
OE
UB
I/O11I/O10
I/O12
I/O13
NC
A8
D D
D DIN
OUT
OUT
IN
A1
A0
A3
A4
A5
A6
A7
NC
A16 I/O5
A14
A15 I/O6
A12
A13
A9
A10
TFBGA
SUPPLY CURRENT
NC
A2
I/O1
CE
I/O3I/O2
Vcc
I/O4A17
Vss
I/O7
I/O8
WE
NC
A11
Standby
SB1
, I
SB
SB1
ICC,I
CC1,ICC2
I
CC,ICC1,ICC2
I
CC,ICC1,ICC2
2
Page 3
Rev. 1.1
UTRON
ABSOLUTE MAXIMUM RATINGS
256K X 16 BIT LOW POWER CMOS SRAM
*
UT62L25616(I)
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V Operating Temperature Industrial T
Storage Temperature T
-0.5 to 4.6 V
TERM
A
-65 to +150
STG
-40 to 85
℃ ℃
Power Dissipation PD 1 W DC Output Current I Soldering Temperature (under 10 secs) Tsolder 260
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
50 mA
OUT
℃
DC ELECTRICAL CHARACTERISTICS
(V
= 2.7V~3.6V, TA = -40℃ to 85℃(I))
CC
PARAMETER
SYMBOL
Power Voltage VCC 2.7 3.0 3.6 V Input High Voltage VIH 2.0 - VCC+0.3 V Input Low Voltage VIL -0.2 - 0.6 V Input Leakage Current ILI
Output Leakage Current ILO
Output High Voltage VOH IOH= -1mA 2.2 - - V Output Low Voltage VOL IOL= 2.1mA - - 0.4 V Operating Power
ICC Cycle time=min, 100%duty,
Supply Current
Average Operation
Icc1
Current
Icc2 Cycle time=500ns,100%duty,I/O=0mA,
Standby Current (TTL) ISB
Standby Current (CMOS) -L - 20 80
I
SB1
TEST CONDITION MIN. TYP. MAX. UNIT
V
≦VIN ≦VCC
SS
V
≦V
SS
I/O
≦V
Output Disabled
CC;
- 1 - 1
- 1 - 1
55 - 30 45 mA
I/O=0mA,
CE
=V
;
IL
70 - 25 35 mA
100 - 20 25 mA
Cycle time=1µs,100%duty,I/O=0mA,
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
CE
- 4 5 mA
- 8 10 mA
≦
0.2V,other pins at 0.2V or Vcc-0.2V,
CE
=V
CE
CE
other pins =VIL or VIH,
IH,
=V
-0.2V,
CC
other pins at 0.2V or Vcc-0.2V,
- 0.3 0.5 mA
-LL - 3 25
A
µ
A
µ
A
µ
A
µ
3
Page 4
UTRON
Rev. 1.1
CAPACITANCE
(TA=25
256K X 16 BIT LOW POWER CMOS SRAM
℃
, f=1.0MHz)
UT62L25616(I)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C Input/Output Capacitance C
Note : These parameters are guaranteed by device characterization, but not production tested.
IN
I/O
-
-
6 pF 8 pF
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V Output Load CL = 30pF, IOH/IOL = -1mA / 2.1mA
AC ELECTRICAL CHARACTERISTICS
(VCC =2.7V~3.6V, TA = -40℃ to 85℃(I))
(1) READ CYCLE
PARAMETER
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change
,UB
LB
LB
LB
Access Time
,UB
to High-Z Output
,UB
to Low-Z Output
SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
tRC 55 - 70 - 100 - ns tAA - 55 - 70 - 100 ns t
- 55 - 70 - 100 ns
ACE
tOE - 30 - 35 - 50 ns t
10 - 10 - 10 - ns
CLZ*
t
5 - 5 - 5 - ns
OLZ*
t
- 20 - 25 - 30 ns
CHZ*
t
- 20 - 25 - 30 ns
OHZ*
tOH 5 - 5 - 5 - ns tBA - 55 - 70 - 100 ns
t
- 25 - 30 - 40 ns
HZB
t
0 - 0 - 0 - ns
LZB
(2) WRITE CYCLE
PARAMETER
Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z
,UB
LB
*These parameters are guaranteed by device characterization, but not production tested.
Valid to End of Write
SYMBOL UT62L25616(I)-55 UT62L25616(I)-70 UT62L25616(I)-100 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
tWC 55 - 70 - 100 - ns tAW 50 - 60 - 80 - ns tCW 50 - 60 - 80 - ns tAS 0 - 0 - 0 - ns tWP 45 - 55 - 70 - ns tWR 0 - 0 - 0 - ns tDW 25 - 30 - 40 - ns tDH 0 - 0 - 0 - ns t
5 - 5 - 5 - ns
OW*
t
- 30 - 30 - 40 ns
WHZ*
tBW 45 - 60 - 80 - ns
4
Page 5
UTRON
Rev. 1.1
TIMING WAVEFORMS
256K X 16 BIT LOW POWER CMOS SRAM
READ CYCLE 1
(Address Controlled)
Address
t
OH
DOUT Data Valid
READ CYCLE 2
(CE and
OE
(1,2,4)
t
AA
Controlled)
t
RC
(1,3,5,6)
t
RC
UT62L25616(I)
t
OH
Address
t
AA
t
CE
ACE
LB , UB
OE
t
CLZ
t
Dout
HIGH-Z
OLZ
Notes :
1.
2. Device is continuously selected
3. Address must be valid prior to or coincident with
4.
5. t
6. At any given temperature and voltage condition, t
is HIGH for read cycle.
WE
is LOW.
OE
, t
, t
CLZ
OLZ
CHZ
and t
=V
IL.
CE
are specified with CL = 5pF. Transition is measured ±500mV from steady state.
OHZ
t
BA
t
BLZ
t
OE
transition; otherwise t
CE
is less than t
CHZ
CLZ
, t
OHZ
t
t
OH
Data Valid
t
BHZ
is the limiting parameter.
AA
is less than t
OLZ.
OHZ
t
CHZ
HIGH-Z
5
Page 6
UTRON
Rev. 1.1
WRITE CYCLE 1
Address
CE
WE
LB , UB
Dout
Din
WRITE CYCLE 2
(
(
WE
CE
Controlled)
t
Controlled)
256K X 16 BIT LOW POWER CMOS SRAM
(1,2,3,5)
t
WC
AW
t
CW
t
AS
t
WP
BW
t
WHZ
t
High-Z
t
DW
Data Valid
(1,2,5)
(4) (4)
WC
t
UT62L25616(I)
WR
t
OW
t
DH
t
Address
AW
t
CE
AS
t
WE
LB , UB
WHZ
t
Dout
Din
Notes :
1.
2. A write occurs during the overlap of a low
3. During a
4. During this period, I/O pins are in the output state, and input signals must not be applied.
or
WE
to be placed on the bus.
5. If the CE
must be HIGH during all address transitions.
CE
CE
controlled with write cycle with
WE
transition occurs simultaneously with or after WE
LOW
CW
t
WP
t
BW
t
and a low
LOW, t
OE
High-Z
DW
t
Data Valid
.
WE
must be greater than t
WP
WR
t
t
WHZ+tDW
LOW
high impedance state.
6. t
OW
and t
are specified with CL = 5pF. Transition is measured ±500mV from steady state.
WHZ
DH
to allow the drivers to turn off and data
transition, the outputs remain in a
6
Page 7
Rev. 1.1
UTRON
DATA RETENTION CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time Recovery Time
V
I
DR
t
CDR
t
R
DR
≧ V
CE
Vcc=1.5V
≧ V
CE See Data Retention 0 - - ms Waveforms (below)
DATA RETENTION WAVEFORM
VCC
CE
VSS
2.7V
t
CDR
Data Retention Mode
V
DR
CE ≧ V
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
(TA =
-0.2V
CC
-0.2V
CC
≧ 1.5V
-0.2V
CC
-40℃ to 85℃(I)
)
1.5 - 3.6 V
- L - 1 50
- LL - 0.5 20
5 - - ms
2.7V
t
R
A
µ
A
µ
7
Page 8
Rev. 1.1
UTRON
PACKAGE OUTLINE DIMENSION
44 pin 400mil TSOP-Ⅱ Package Outline Dimension
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
θ
SYMBOLS
A 1.00 - 1.20 0.039 - 0.047 A1 0.05 - 0.15 0.002 - 0.006 A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.30 0.35 0.45 0.012 0.014 0.018
c 0.12 - 0.21 0.0047 - 0.083 D 18.313 18.415 18.517 0.721 0.725 0.728 E 11.854 11.836 11.838 0.460 0.466 0.470
E1 10.058 10.180 10.282 0.398 0.400 0.404
e - 0.800 - - 0.0315 ­L 0.40 0.50 0.60 0.0157 0.020 0.0236
2D - 0.805 - - 0.0317 -
y 0.00 - 0.076 0.000 - 0.003
Θ
DIMENSIONS IN MILLMETERS DIMENSIONS IN INCHS
MIN NOM MAX. MIN. NOM. MAX.
o
0
- 5o 0
o
- 5o
8
Page 9
UTRON
Rev. 1.1
48 pin 6mm×8mm TFBGA Outline Dimension
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
9
Page 10
Rev. 1.1
UTRON
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25616(I)
ORDERING INFORMATION
INDUSTRIAL TEMPERATURE
PART NO. ACCESS TIME
(ns)
UT62L25616MC-55LI 55 20 UT62L25616MC-55LLI 55 3 UT62L25616MC-70LI 70 20 UT62L25616MC-70LLI 70 3 UT62L25616BS-55LI 55 20 48 PIN TFBGA UT62L25616BS-55LLI 55 3 48 PIN TFBGA
UT62L25616BS-70LI 70 20 48 PIN TFBGA UT62L25616BS-70LLI 70 3 48 PIN TFBGA
STANDBY CURRENT
(µA) TYP.
PACKAGE
44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ 44 PIN TSOP-Ⅱ
10
Page 11
Rev. 1.1
UTRON
256K X 16 BIT LOW POWER CMOS SRAM
UT62L25616(I)
REVISION HISTORY
REVISION DESCRIPTION DATE
Preliminary Rev. 0.5 Original. Mar, 2001
Rev. 1.0
Rev. 1.1
1. The symbols CE# and OE# and WE# are revised as.
and
OE and
2. Separate Industrial and Consumer SPEC.
3. Add access time 55ns range.
4. The power supply is revised: 3.3V3.6V
1. Revised PIN CONFIGURATION : Rev 1.0 : No A17 pintyping error Rev 1.1 : add A17 pin.
WE
.
CE
Jul 4,2001
Oct 18,2001
11
Page 12
Rev. 1.1
UTRON
THIS PAGE IS LEFT BLANK INTENTIONALLY.
UT62L25616(I)
256K X 16 BIT LOW POWER CMOS SRAM
12
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