Datasheet UT62L1024SC-70LL, UT62L1024SC-70L, UT62L1024SC-55LL, UT62L1024SC-55L, UT62L1024SC-35LL Datasheet (UTRON)



Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

FEATURES

Access time : 35/55/70ns (max.)



Low power consumption :



Operating : 40/35/30 mA (typical) Standby : 2.5µA (typical) L-version

0.5µA (typical) LL-version

Power supply range : 2.7V to 3.6V



All inputs and outputs TTL compatible



Fully static operation



Three state outputs



Data retention voltage : 2V (min.)



Package : 32-pin 600 mil PDIP



32-pin 450 mil SOP 32-pin 8x20 mm TSOP-1 32-pin 8x13.4 mm STSOP

FUNCTIONAL BLOCK DIAGRAM

UT62L1024

GENERAL DESCRIPTION

The UT62L1024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

Easy memory expansion is provided by using two chip enable input.( particularly well suited for battery back-up

nonvolatile memory application.

The UT62L1024 operates from a single 2.7V~

3.6V power supply and all inputs and outputs are fully TTL compatible.

,CE2) It is

1CE

2048 ×512

A0-A16

DECODER

MEMORY

ARRAY

Vcc Vss

I/O1-I/O8

I/O DATA

CIRCUIT

COLUMN I/O

CE1 CE2

OE

CONTROL

CIRCUIT

WE

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

PIN CONFIGURATION

NC

A16

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

32

31

30

29

UT62L1024

28

27

26

25

24

23

22

21

20

19

18

1716

PDIP / SOP

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A16 Address Inputs

I/O1 - I/O8 Data Inputs/Outputs

,CE2

1CE

WE

OE

Chip enable 1,2 Inputs

Write Enable Input

Output Enable Input

VCC Power Supply

VSS Ground NC No Connection

Vcc

A15

CE2

WE

A13

A9

A11

OE

A10

I/O8

I/O7

I/O6

I/O5

I/O4

UT62L1024

A11

A9

A8

A13

WE

A8

1CE

CE2

A15

Vcc

NC

A16

A14

A12

A7

A6

A5

A4 A3

1

2

3

4

5

6

7

8

UT62L1024

9

10

11

12

13

14

15

16

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

A10

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

1CE

A0

A1

A2

TSOP-I/STSOP

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

UT62L1024

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to Vss V Operating Temperature TA 0 to +70

Storage Temperature T Power Dissipation PD 1 W

DC Output Current I Soldering Temperature (under 10 sec) T

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

CE2

1CE

Standby H X X X High - Z Standby X L X X High -Z Output Disable L H H H High - Z

Read L H L H Write L H X L

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current I

Output High Voltage Output Low Voltage Average Operating

I

V

V V

V

I

CC

IL

OL

OH

OL

IH

IL

Power Supply Courrent

I

CC1

Standby Power

Supply Current

*Those parameters are for reference only under 50℃

I

SB

I

SB1

*

-0.5 to +4.6 V

TERM

℃

-65 to +150

STG

50 mA

OUT

260

solder

I/O OPERATION SUPPLY CURRENT

OE

VSS ≦VIN ≦VCC VSS ≦V

=V

1CE

= V

OE

WE

(VCC = 2.7V~3.6V, Ta = 0℃ to +70℃)

≦

V

I/O

IH

CC

or CE2 = VIL or

WE

= V

or

D

OUT

D

IN

IL

2.0 - V

- 0.5 - 0.6 V

- 1 - 1

,

I

SB

SB1

,

I

SB

SB1

I

CC , ICC1

I

CC , ICC1

I

CC , ICC1

CC

IOH = - 1mA 2.2 - - V IOL= 4mA - - 0.4 V Cycle time =Min. 100% Duty,

=V

I

= 0mA

I/O

, CE2 = VIH,

1CE

IL

35 - 40 60 mA 55 - 35 50 mA 70 - 30 40 mA

Cycle time = 1µs, 100% Duty,

≦

1CE

= 0mA

I/O

=V

1CE

≧

1CE

0.2V,CE2≧V

or CE2 = VIL

IH

V

CC

.

I

.CE2≦0.2V

-0.2V or

-0.2V,

CC

- - 5 mA

- - 1.0 mA

- L - 2.5

-

- 0.5

LL

100

20*

10*

℃

+0.5 V

µ

40

µ

A

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

UT62L1024

CAPACITANCE

PARAMETER SYMBOL MIN. MAX. UNIT

Input Capacitance Input/Output Capacitance

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels 0.4V to 2.4V Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V Output Load CL=50pF, IOH/IOL=-1mA/2mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE PARAMETER

Read Cycle Time tRC 35 - 55 - 70 - ns Address Access Time tAA - 35 - 55 - 70 ns Chip Enable Access Time t Output Enable Access Time tOE - 25 - 30 - 35 ns Chip Enable to Output in Low-Z t Output Enable to Output in Low-Z t Chip Disable to Output in High-Z t Output Disable to Output in High-Z t Output Hold from Address Change tOH 5 - 5 - 5 - ns

(2) WRITE CYCLE PARAMETER SYMBOL

Write Cycle Time tWC 35 - 55 - 70 - ns Address Valid to End of Write tAW 30 - 50 - 60 - ns Chip Enable to End of Write t Address Set-up Time tAS 0 - 0 - 0 - ns Write Pulse Width tWP 25 - 40 - 45 - ns Write Recovery Time tWR 0 - 0 - 0 - ns Data to Write Time Overlap tDW 20 - 25 - 30 - ns Data Hold from End of Write-Time tDH 0 - 0 - 0 - ns Output Active from End of Write tOW* 5 - 5 - 5 - ns Write to Output in High-Z t

*These parameters are guaranteed by device characterization, but not production tested.

(Ta=25℃, f=1.0MHz)

SYMBOL

, t

ACE1

*, t

CLZ1

* 5 - 5 - 5 - ns

OLZ

*, t

CHZ1

* - 25 - 30 - 35 ns

OHZ

, t

CW1

CW2

* - 15 - 20 - 25 ns

WHZ

C

IN

C

I/O

UT62L1024-35 UT62L1024-55 UT62L1024-70

-

(VCC = 2.7V~3.6V , Ta = 0℃ to +70℃)

MIN. MAX. MIN. MAX. MIN. MAX.

- 35 - 55 - 70 ns

ACE2

* 10 - 10 - 10 - ns

CLZ2

* - 25 - 30 - 35 ns

CHZ2

UT62L1024-35

MIN.

30 - 50 - 60 - ns

UT62L1024-55

MAX. MIN.

6 pF 8 pF

UT62L1024-70

MAX. MIN. MAX.

UNIT

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1 (Address Controlled)

Address

DOUT Data Valid

READ CYCLE 2 (

1CE

t

AA

t

OH

, CE2 and

(1,2,4)

Controlled)

OE

t

RC

(1,3,5,6)

RC

t

UT62L1024

t

OH

Address

AA

t

CE1

CE2

OE

t

CLZ1

t

CLZ2

t

CHZ2

OLZ

OE

and t

Dout

Notes :

1.

2. Device is continuously selected

3. Address must be valid prior to or coincident with

4.

5. t

6. At any given temperature and voltage condition, t

is HIGH for a read cycle.

WE

is low.

OE

, t

CLZ1

CLZ2

, t

HIGH-Z

, t

OLZ

CHZ1

, t

ACE1

t

ACE2

,

=V

and CE2=V

IL

1CE

are specified with CL=5pF. Transition is measured ±500mV from steady state.

OHZ

t

OE

low

1CE

is less than t

CHZ1

t

CHZ1

t

CHZ2

t

OHZ

t

OH

HIGH-Z

Data Valid

IH.

and CE2 high transition; otherwise tAA is the limiting parameter.

, t

CLZ1

CHZ2

is less than t

CLZ2

, t

is less than t

OHZ

OLZ.

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

UTRON

Rev. 1.7

128K X 8 BIT LOW POWER CMOS SRAM

WRITE CYCLE 1 (

Address

CE1

CE2

WE

Dout

Din

WRITE CYCLE 2 (

Controlled)

WE

t

AS

and CE2 Controlled)

1CE

(1,2,3,5)

t

UT62L1024

WC

t

AW

t

CW1

t

CW2

WR

WP

t

WHZ

t

(4) (4)

(1,2,5)

WC

t

High-Z

t

DW

Data Valid

t

OW

t

DH

t

Address

AW

t

CE1

CE2

WE

Dout

Din

Notes :

1.

WE

2. A write occurs during the overlap of a low

3. During a

off and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

4. If the

state.

and t

6. t

OW

must be HIGH or CE2 must be LOW during all address transitions.

or

1CE

controlled with write cycle with

WE

LOW transition occurs simultaneously with or after

1CE

are specified with CL=5pF. Transition is measured ±500mV from steady state.

WHZ

AS

t

WHZ

t

CW1

t

CW2

t

WP

t

High-Z

, a high CE2 and a low

1CE

OE

LOW, t

must be greater than t

WP

WE

WR

t

DH

DW

t

Data Valid

WE

LOW transition, the outputs remain in a high Impedance

t

.

WHZ+tDW

to allow the I/O drivers to turn

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

UT62L1024

DATA RETENTION CHARACTERISTICS

(Ta = 0℃ to +70℃)

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Vcc for Data Retention

Chip Disable to Data

Retention Time

Recovery Time

tRC* = Read Cycle Time *Those parameters are for reference only under 50℃

t

V

DR

t

CDR

R

DR

≧ V

1CE

CE2 ≤ 0.2V Vcc=2V

≧ V

1CE

CE2 ≤ 0.2V See Data Retention Waveforms (below)

-0.2V or

CC

-0.2V or

CC

2.0 - 3.3 V

- L -

- LL -

0 - - ns

tRC* - - ns

DATA RETENTION WAVEFORM

VCC

V

SS

1CE

2.7V

t

CDR

V

IH

Date Retention Mode

V

≧ 2.0V

DR

≧ V

CC

-0.2V

1CE

CE2

V

IL

CE2 ≤ 0.2V

2.7V

t

R

V

40 Data Retention Current I

20*

20

5*

µA

1

0.5

IH

IL

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

PACKAGE OUTLINE DIMENSION

32 pin 600 mil PDIP Package Outline Dimension

UT62L1024

UNIT

INCH(BASE) MM(REF)

0.150 ±0.005 3.810 ±0.127

0.018 ±0.005 0.457±0.127

0.050 ±0.005 1.270±0.127

0.010 ±0.004 0.254±0.102

1.650 ±0.005 41.910 ±0.127

0.600 ±0.010 15.240 ±0.254

0.544 ±0.004 13.818 ±0.102

0.640±0.020 16.256 ±0.508

0.130 ±0.010 3.302 ±0.254

0.075 ±0.010 1.905 ±0.254

0.070 ±0.005 1.778 ±0.127

A

SYMBOL

A1 0.010 (MIN) 0.254 (MIN) A2

B

B1

c D E

E1

e 0.100 (TYP) 2.540 (TYP)

eB

L S

Q1

Note:

1. D/E1/S DIMENSION DO NOT INCLUDE MOLD FLASH.

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Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

32 pin 450mil SOP Package Outline Dimension

UT62L1024

UNIT

SYMBOL

A 0.118 (MAX) 2.997 (MAX) A1 0.004(MIN) 0.102(MIN) A2 0.111(MAX) 2.82(MAX)

b 0.016(TYP) 0.406(TYP)

c 0.008(TYP) 0.203(TYP)

D 0.817(MAX) 20.75(MAX)

E E1

e 0.050(TYP) 1.270(TYP)

L

L1

S 0.026(MAX) 0.066 (MAX)

y

Θ

INCH(BASE) MM(REF)

0.445 ±0.005 11.303 ±0.127

0.555 ±0.012 14.097 ±0.305

0.0347 ±0.008 0.881 ±0.203

0.055 ±0.008 1.397 ±0.203

0.004(MAX) 0.101(MAX)

o

0

-10o 0

o

-10o

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

32 pin TSOP-I Package Outline Dimension

UT62L1024

UNIT

SYMBOL

A 0.047 (MAX) 1.20 (MAX) A1 A2

b

c 0.005 (TYP) 0.127 (TYP)

D

E

e 0.020 (TYP) 0.50 (TYP)

HD

L

L1

y 0.003 (MAX) 0.076 (MAX)

Θ

0

INCH(BASE) MM(REF)

0.004 ±0.002 0.10 ±0.05

0.039 ±0.002 1.00 ±0.05

0.008 + 0.002

- 0.001

0.724 ±0.004 18.40 ±0.10

0.315 ±0.004 8.00 ±0.10

0.787 ±0.008 20.00 ±0.20

0.0197 ±0.004 0.50 ±0.10

0.0315 ±0.004 0.08 ±0.10

o

〜

5

0

0.20 + 0.05

-0.03

o

〜

5

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

32 pin 8mm x 13.4mm STSOP Package Outline Dimension

1

16

HD

c

L

32

17

"A"

D

UT62L1024

12°(2x)12°(2x)

e

E

b

Seating Plane

y

°

12

(2X)

16

1

17

c

A2A1

A

SEATING PLANE

12°(2X)

"A" DATAIL VIEW

32

GAUGE PLANE

0.254

0

L

L1

UNIT

SYMBOL

INCH(BASE) MM(REF)

A 0.049 (MAX) 1.25 (MAX) A1 A2

b

0.005 ±0.002 0.130 ±0.05

0.039 ±0.002 1.00 ±0.05

0.008 ±0.01 0.20±0.025 c 0.005 (TYP) 0.127 (TYP) D E

0.465 ±0.004 11.80 ±0.10

0.315 ±0.004 8.00 ±0.10

e 0.020 (TYP) 0.50 (TYP)

HD

L

L1

c

y 0.003 (MAX) 0.076 (MAX)

Θ

0

0.528±0.008 13.40 ±0.20.

0.0197 ±0.004 0.50 ±0.10

0.0315 ±0.004 0.8 ±0.10

o

〜

5

0

o

〜

5

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

UT62L1024

ORDERING INFORMATION

PART NO. ACCESS TIME

(ns)

UT62L1024PC-35L 35 20 32 PIN PDIP UT62L1024PC-35LL 35 10 32 PIN PDIP UT62L1024PC-55L 55 20 32 PIN PDIP UT62L1024PC-55LL 55 10 32 PIN PDIP UT62L1024PC-70L 70 20 32 PIN PDIP UT62L1024PC-70LL 70 10 32 PIN PDIP UT62L1024SC-35L 35 20 32 PIN SOP UT62L1024SC-35LL 35 10 32 PIN SOP UT62L1024SC-55L 55 20 32 PIN SOP UT62L1024SC-55LL 55 10 32 PIN SOP UT62L1024SC-70L 70 20 32 PIN SOP UT62L1024SC-70LL 70 10 32 PIN SOP UT62L1024LC-35L 35 20 32 PIN TSOP-I UT62L1024LC-35LL 35 10 32 PIN TSOP-I UT62L1024LC-55L 55 20 32 PIN TSOP-I UT62L1024LC-55LL 55 10 32 PIN TSOP-I UT62L1024LC-70L 70 20 32 PIN TSOP-I UT62L1024LC-70LL 70 10 32 PIN TSOP-I UT62L1024LS-35L 35 20 32 PIN STSOP UT62L1024LS-35LL 35 10 32 PIN STSOP UT62L1024LS-55L 55 20 32 PIN STSOP UT62L1024LS-55LL 55 10 32 PIN STSOP UT62L1024LS-70L 70 20 32 PIN STSOP UT62L1024LS-70LL 70 10 32 PIN STSOP

STANDBY CURRENT

(µA) (max) Ta = 50℃

PACKAGE

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

UT62L1024

REVISION HISTORY

REVISION DESCRIPTION DATE

Rev. 1.0 Original. Jun. 01. 1997 Rev. 1.1

Rev. 1.2 Add STSOP-I Package Aug. 29. 2000 Rev. 1.3 Modify the format of power consumption Sep. 01. 2000 Rev. 1.4 Add speed : -55ns Dec. 01. 2000 Rev. 1.5 Vcc min 3.1→2.7V Mar. 15. 2001 Rev. 1.6

Rev. 1.7 Revised 32 pin 8mmx13.4mm STSOP Package Outline

128Kx 8 Low Voltage CMOS SRAM 之TN8106 body

降為

tunings,將I

1. The symbols CE1# ,OE# & WE# are revised as

2. Add Icc value of 55ns range(access time) .

3. V

OH

4. I

is revised as 100µs.

SB1

Dimension.

SB1

is revised as 2.2V.

0.5uA(LL)、2uA(L)、Vcc range：3.0V~3.6V

已作

fine

1CE,OE&WE

Apr. 05. 2000

Jun. 26. 2001

.

Nov. 26. 2001

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

Rev. 1.7

UTRON

128K X 8 BIT LOW POWER CMOS SRAM

UT62L1024

THIS PAGE IS LEFT BLANK INTENTIONALLY.

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