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UT62L1024SC-55LI
Datasheet (UTRON)
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Datasheet UT62L1024SC-70LLI, UT62L1024SC-70LI, UT62L1024SC-55LLI, UT62L1024SC-55LI, UT62L1024LS-70LLI Datasheet (UTRON)

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Page 1
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Access time : 55/70ns (max.)
Low power consumption :
Operating : 30/20 mA (typical) Standby : 10µA (max) L-version T
A
＝50℃
3µA (max) LL-version T
A
＝50℃
Power supply range : 2.5V ~ 3.6V
All inputs and outputs TTL compatible
Fully static operation
Data retention voltage : 2V (min.)
Operation Temperature
Industrial : -40℃~+85℃
Package : 32-pin 450mil SOP
32-pin 8x20mm TSOP-1
32-pin 8x13.4mm STSOP
36-pin 6×8mm TFBGA
GENERAL DESCRIPTION
The UT62L1024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.
Easy memory expansion is provided by using two chip enable input (
1CE
,CE2) and supports
industrial operating temperature range.
The UT62L1024 operates from a wide range
2.5V~3.6V power supply and all inputs and outputs are fully TTL compatible.
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
2048 ×512
MEMORY
ARRAY
COLUMN I/O
OE
WE
A0-A16
Vcc Vss
I/O1-I/O8
CE1 CE2
Page 2
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
2
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
CE2
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT62L1024
SOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
1716
15
20
19
18
22
23
24
25
26
27
21
1CE
WE
OE
A13
A14
NC
A16
Vcc
A15
29
30
31
32
TSOP-1/STSOP
I/O4
A11
A9 A8
A13
I/O3
A10
A14 A12
A7 A6 A5
Vcc
I/O7 I/O6 I/O5
Vss
I/O2 I/O1
A0 A1
A2
A4 A3
UT62L1024
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20 19 18
22
23
24
25
26
27
21
WE
OE
CE2
NC
A15
32 31 30 29
A16
1CE
I/O8
OE
WE
A12A11 A13
CE2
NC
A10 A14
A15
I/O6
I/O7
I/O8
A9
Vss
A8
A16
I/O5
Vcc
Vcc
I/O4
NC
Vss
A7
A0
I/O3
I/O2
I/O1
A6A1 A3
A5NC
A4A2
123456
H
G
C
D
E
F
A
B
TFBGA
CE1
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
1CE
,CE2
Chip enable 1,2 Inputs
WE
Write Enable Input
OE
Output Enable Input
VCC Power Supply
VSS Ground NC No Connection
Page 3
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
3
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to Vss V
TERM
-0.5 to Vcc+0.5 V
Operating Temperature Industrial TA -40 to +85
℃
Storage Temperature T
STG
-65 to +150
℃
Power Dissipation PD 1 W DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 sec) T
solder
260
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
1CE
CE2
OE
WE
I/O OPERATION SUPPLY CURRENT
Standby H X X X High - Z
I
SB
,
I
SB1
Standby X L X X High -Z
I
SB
,
I
SB1
Output Disable L H H H High - Z ICC, ICC1
Read L H L H D
OUT
ICC, ICC1
Write L H X L D
IN
ICC, ICC1,
Note: H = VIH, L=VIL, X = Don't care.
Page 4
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
4
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.5V~3.6V, TA = -40℃~+85℃ )
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Input High Voltage
V
IH
2.0 - V
CC
+0.5 V
Input Low Voltage
V
IL
- 0.5 - 0.6 V
Input Leakage Current
I
IL
VSS ≦VIN ≦VCC
- 1 - 1
µ
A
Output Leakage Current I
OL
VSS ≦V
I/O
≦
V
CC
1CE
=V
IH
or CE2 = VIL or
OE
= V
IH
or
WE
= V
IL
- 1 - 1
µ
A
Output High Voltage
V
OH
IOH = - 1mA 2.0 - - V
Output Low Voltage
V
OL
IOL= 2.1mA - - 0.4 V
55 - 30 40 mA
ICC
Cycle time = Min.,100% Duty,
1CE
=V
IL
, CE2 = VIH,I
I/O
=0mA
70 - 20 30 mA
Average Operating Power Supply Courrent
I
CC1
Cycle time = 1µs, 100% Duty,
.
1CE
≦
0.2V,CE2≧V
CC
-0.2V, I
I/O
= 0mA
- - 5 mA
I
SB
1CE
=V
IH
or CE2 = VIL
- - 1.0 mA
TA = -40℃~+85℃
- - 50
- L
TA=+50℃
- - 10
µ
A
TA = -40℃~+85℃
- - 10
Standby Power
Supply Current
I
SB1
1CE
≧
V
CC
-0.2V
or .CE2≦0.2V
-
LL
TA=+50℃
- - 3
µ
A
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX. UNIT
Input Capacitance
C
IN
-
6 pF
Input/Output Capacitance
C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0.4V to 2.2V Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V Output Load CL=30pF, IOH/IOL=-1mA/2.1mA
Page 5
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
5
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.5V~3.6V , TA = -40℃~+85℃ )
(1) READ CYCLE
UT62L1024-55 UT62L1024-70
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time tRC 55 - 70 - ns Address Access Time tAA - 55 - 70 ns Chip Enable Access Time t
ACE1
, t
ACE2
- 55 - 70 ns Output Enable Access Time tOE - 30 - 35 ns Chip Enable to Output in Low-Z t
CLZ1
*, t
CLZ2
* 10 - 10 - ns
Output Enable to Output in Low-Z t
OLZ
* 5 - 5 - ns
Chip Disable to Output in High-Z t
CHZ1
*, t
CHZ2
* - 30 - 35 ns
Output Disable to Output in High-Z t
OHZ
* - 30 - 35 ns
Output Hold from Address Change tOH 5 - 5 - ns
(2) WRITE CYCLE
UT62L1024-55 UT62L1024-70
PARAMETER SYMBOL
MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time tWC 55 - 70 - ns Address Valid to End of Write tAW 50 - 60 - ns Chip Enable to End of Write t
CW1
, t
CW2
50 - 60 - ns Address Set-up Time tAS 0 - 0 - ns Write Pulse Width tWP 40 - 45 - ns Write Recovery Time tWR 0 - 0 - ns Data to Write Time Overlap tDW 25 - 30 - ns Data Hold from End of Write-Time tDH 0 - 0 - ns Output Active from End of Write tOW* 5 - 5 - ns Write to Output in High-Z t
WHZ
* - 20 - 25 ns
*These parameters are guaranteed by device characterization, but not production tested.
Page 6
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
6
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled)
(1,2,4)
t
RC
Address
DOUT Data Valid
t
AA
t
OH
t
OH
READ CYCLE 2 (
1CE
, CE2 and
OE
Controlled)
(1,3,5,6)
t
RC
t
AA
t
ACE1
t
ACE2
t
OE
t
CHZ1
t
CHZ2
t
OHZ
t
CLZ1
t
CLZ2
t
OH
t
OLZ
HIGH-Z
Data Valid
HIGH-Z
Address
CE1
CE2
OE
Dout
Notes :
1.
WE
is HIGH for a read cycle.
2. Device is continuously selected
OE
,
1CE
=V
IL
and CE2=V
IH.
3. Address must be valid prior to or coincident with
1CE
low
and CE2 high transition; otherwise tAA is the limiting parameter.
4.
OE
is low.
5. t
CLZ1
, t
CLZ2
, t
OLZ
, t
CHZ1
, t
CHZ2
and t
OHZ
are specified with CL=5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ1
is less than t
CLZ1
, t
CHZ2
is less than t
CLZ2
, t
OHZ
is less than t
OLZ.
Page 7
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
7
WRITE CYCLE 1 (
WE
Controlled)
(1,2,3,5)
t
WC
t
AW
t
CW1
t
AS
t
WP
t
WHZ
t
OW
t
DW
t
DH
t
CW2
t
WR
Address
CE1
CE2
WE
Dout
Din
Data Valid
High-Z
(4) (4)
WRITE CYCLE 2 (
1CE
and CE2 Controlled)
(1,2,5)
t
WC
t
AW
t
CW1
t
AS
t
WR
t
CW2
t
WP
t
WHZ
t
DW
t
DH
Data Valid
Address
CE1
CE2
WE
Dout
Din
High-Z
Notes :
1.
WE
or
1CE
must be HIGH or CE2 must be LOW during all address transitions.
2. A write occurs during the overlap of a low
1CE
, a high CE2 and a low
WE
.
3. During a
WE
controlled with write cycle with
OE
LOW, t
WP
must be greater than t
WHZ+tDW
to allow the I/O drivers to turn
off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
4. If the
1CE
LOW transition occurs simultaneously with or after
WE
LOW transition, the outputs remain in a high
Impedance state.
6. t
OW
and t
WHZ
are specified with CL=5pF. Transition is measured ±500mV from steady state.
Page 8
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
8
DATA RETENTION CHARACTERISTICS
(TA = -40℃~+85℃ )
PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT
Vcc for Data Retention
V
DR
1CE
≧ V
CC
-0.2V or CE2 ≤ 0.2V
2.0 - 3.3 V
50 Data Retention Current I
DR
- L ­5
10*
µA
15
Vcc=2V
1CE
≧ V
CC
-0.2V or
CE2 ≤ 0.2V
- LL -
1.5 2*
µA
Chip Disable to Data
t
CDR
See Data Retention
0 - - ns
Retention Time
Waveforms (below)
Recovery Time
t
R
tRC* - - ns
tRC* = Read Cycle Time *Those parameters are for reference only under 50℃
DATA RETENTION WAVEFORM
Low Vcc Data Retention Waveform (1) (
1CE
controlled)
Data Retention Mode
V
DR
≧
2V
CE1
≧
VCC-0.2V
Vcc
Vcc
V
IH
V
IH
V
CC
CE1
t
R
t
CDR
Low Vcc Data Retention Waveform (2) (CE2 controlled)
Data Retention Mode
V
DR
≧
2V
Vcc
Vcc
V
CC
t
R
t
CDR
CE2 ≦ 0.2V
V
IL
V
IL
CE2
Page 9
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
9
PACKAGE OUTLINE DIMENSION
32 pin 450mil SOP Package Outline Dimension
UNIT
SYMBOL
INCH(REF) MM(BASE)
A 0.118 (MAX) 2.997 (MAX) A1 0.004(MIN) 0.102(MIN) A2 0.111(MAX) 2.82(MAX)
b 0.016(TYP) 0.406(TYP)
c 0.008(TYP) 0.203(TYP)
D 0.817(MAX) 20.75(MAX)
E
0.445 ±0.005 11.303 ±0.127
E1
0.555 ±0.012 14.097 ±0.305 e 0.050(TYP) 1.270(TYP) L
0.0347 ±0.008 0.881 ±0.203
L1
0.055 ±0.008 1.397 ±0.203 S 0.026(MAX) 0.660 (MAX)
y
0.004(MAX) 0.101(MAX)
Θ
0
o
-10o 0
o
-10o
Page 10
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
10
32 pin TSOP-I Package Outline Dimension
UNIT
SYMBOL
INCH(BASE) MM(REF)
A 0.047 (MAX) 1.20 (MAX)
A1
0.004 ±0.002 0.10 ±0.05
A2
0.039 ±0.002 1.00 ±0.05
b
0.008 + 0.002
- 0.001
0.20 + 0.05
-0.03 c 0.005 (TYP) 0.127 (TYP) D
0.724 ±0.004 18.40 ±0.10
E
0.315 ±0.004 8.00 ±0.10
e 0.020 (TYP) 0.50 (TYP)
HD
0.787 ±0.008 20.00 ±0.20
L
0.0197 ±0.004 0.50 ±0.10
L1
0.0315 ±0.004 0.8 ±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ
0
o
〜
5
o
0
o
〜
5
o
Page 11
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
11
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
1
16
17
32
c
L
HD
D
"A"
E
e
12°(2x)12°(2x)
Seating Plane
y
32
17
16
1
c
A2A1
L
A
0.254
0
GAUGE PLANE
12°(2X)
12°(2X)
SEATING PLANE
"A" DATAIL VIEW
L1
b
UNIT
SYMBOL
INCH(BASE) MM(REF)
A 0.049 (MAX) 1.25 (MAX)
A1
0.005 ±0.002 0.130 ±0.05
A2
0.039 ±0.002 1.00 ±0.05
b
0.008 ±0.001 0.200 ±0.025 c 0.005 (TYP) 0.127 (TYP) D
0.465 ±0.004 11.80 ±0.10
E
0.315 ±0.004 8.00 ±0.10
e 0.020 (TYP) 0.50 (TYP)
HD
0.528±0.008 13.40 ±0.20.
L
0.0197 ±0.004 0.50 ±0.10
L1
0.0315 ±0.004 0.8 ±0.10
y 0.003 (MAX) 0.076 (MAX)
Θ
0
o
〜
5
o
0
o
〜
5
o
Page 12
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
12
36 pin 6mm×8mm TFBGA Package Outline Dimension
A1 Ball Pad Corner
A B C D E F G H
123456
A1 Ball Pad Corner
X
Y
DETAIL A
BOTTOM VIEW ( BALL SIDE )TOP VIEW (DIE VIEW )
8.0
±
0.05
6.0±0.05
1.3755.25
1.125 3.75
0.75
0.75
SIDE VIEW
0.55
±
0.32
±
0.02
0
0.23
±
0.03
1.2 MAX.
Z
DETAIL B
0.05
0.02
Page 13
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
13
ORDERING INFORMATION
PART NO. ACCESS TIME
(ns)
PACKAGE
UT62L1024SC-55LI 55 32 PIN SOP UT62L1024SC-55LLI 55 32 PIN SOP UT62L1024SC-70LI 70 32 PIN SOP UT62L1024SC-70LLI 70 32 PIN SOP UT62L1024LC-55LI 55 32 PIN TSOP-I UT62L1024LC-55LLI 55 32 PIN TSOP-I UT62L1024LC-70LI 70 32 PIN TSOP-I UT62L1024LC-70LLI 70 32 PIN TSOP-I UT62L1024LS-55LI 55 32 PIN STSOP UT62L1024LS-55LLI 55 32 PIN STSOP UT62L1024LS-70LI 70 32 PIN STSOP UT62L1024LS-70LLI 70 32 PIN STSOP UT62L1024BS-55LI 55 36 PIN TFBGA UT62L1024BS-55LLI 55 36 PIN TFBGA UT62L1024BS-70LI 70 36 PIN TFBGA UT62L1024BS-70LLI 70 36 PIN TFBGA
Page 14
UTRON
UT62L1024(I)
Preliminary Rev. 0.1
UTRON TECHNOLOGY INC. P80078 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919
14
REVISION HISTORY
REVISION DESCRIPTION DATE
Preliminary Rev. 0.1 Original. Nov 15,. 2001
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