Datasheet UT6264CSC-70LL, UT6264CSC-70L, UT6264CSC-70, UT6264CSC-35LL, UT6264CSC-35L Datasheet (UTRON)



Rev. 1.1

UTRON

FEATURES

Access time : 35/70ns (max.)



Low power consumption :



Operating : 45/30 mA (typ.)
CMOS Standby : 2mA (typ.) normal

2 µA (typ.) L-version
1 µA (typ.) LL-version

Single 4.5V~5.5V power supply



Operating temperature :



Commercial : 0℃~70℃

All inputs and outputs TTL compatible



Fully static operation



Three state outputs



Data retention voltage : 2V (min.)



Package : 28-pin 600 mil PDIP



28-pin 330 mil SOP

FUNCTIONAL BLOCK DIAGRAM

A0-A12

I/O1-I/O8

Vcc
Vss

DECODER

I/O DATA

CIRCUIT

8K ×8

MEMORY

ARRAY

COLUMN I/O

UT6264C

8K X 8 BIT LOW POWER CMOS SRAM

The UT6264C is a 65,536-bit low power CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.

Easy memory expansion is provided by using two
chip enable input.(

,CE2) ,and supports low

1CE

data retention voltage for battery back-up
operation with low data retention current.

The UT6264C operates from a single 4.5V~5.5V
power supply and all inputs and outputs are fully
TTL compatible.

PIN CONFIGURATION

NC

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

1

2

3

4

UT6264C

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Vcc

WE

CE2

A8

A9

A11

OE

A10

1CE

I/O8

I/O7

I/O6

I/O5

I/O4

CE1
CE2

WE

OE

CONTROL

CIRCUIT

PDIP/SOP

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A12 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs

Chip Enable Inputs

Write Enable Input
Output Enable Input

WE

OE

,CE2

1CE

VCC Power Supply
VSS Ground
NC No connection

GENERAL DESCRIPTION

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

1



Rev. 1.1

UTRON

8K X 8 BIT LOW POWER CMOS SRAM

UT6264C

ABSOLUTE MAXIMUM RATINGS*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS V
Operating Temperature Commercial TA 0 to +70

Storage Temperature T
Power Dissipation PD 1 W

DC Output Current I
Soldering Temperature (under 10 sec) Tsolder 260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.

TRUTH TABLE

MODE

CE

CE2

1

OE

Standby H X X X High - Z ISB, ISB1
Standby X L X X High - Z ISB, ISB1
Output Disable L H H H High - Z Icc,Icc1,Icc2
Read L H L H
Write L H X L

note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

(VCC = 4.5V~5.5V, TA = 0℃ to 70℃)

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Power Voltage Vcc 4.5 5.0 5.5 V
Input High Voltage V
Input Low Voltage V
Input Leakage Current

Output Leakage Current I

Output High Voltage V
Output Low Voltage V

2.2 - VCC+0.5 V

IH

- 0.5 - 0.8 V

IL

≦

I

LI

V

SS

V

SS

LO

or

OE

IOH = - 1mA 2.4 - - V

OH

OL

I

CC

I

= 4mA

OL

Cycle time=Min,I

1CE

≦

V

IN

≦

≦

V

I/O

;

= V

IH

= V

CE2= VIH - 70 - 30 45 mA

IL ,

Cycle time=1us; I

Operating Power
Supply Current

Icc1

=0.2V; CE2=Vcc-0.2V;

1CE
other pins at 0.2V or Vcc-0.2V
Cycle time=500ns;I

Icc2

=0.2V; CE2=Vcc-0.2V;

1CE
other pins at 0.2V or Vcc-0.2V

= VIH or CE2= VIL

Standby Current (TTL)

Standby Current (CMOS) I

I

SB

SB1

1CE

1CE

or CE2

≧

VCC-0.2V ;

≦

0.2V;

other pins at 0.2V or Vcc-0.2V

-0.5 to +7.0 V

TERM

℃

-65 to +150

STG

50 mA

OUT

I/O OPERATION SUPPLY CURRENT

WE

VCC

V

CC;

or

WE

=V

1CE

= VIL

IH;

D

OUT

D

IN

or CE2=V

Icc,Icc1,Icc2
Icc,Icc1,Icc2

- 1 - 1

IL;

- 1 - 1

℃

℃

µ

µ

- - 0.4 V

0mA;

;

=

I/O

= 0mA

I/O

- 35 - 45 60 mA

- 20 30 mA

= 0mA;

I/O

- 10 15 mA

Normal - 1 10 mA

- L/- LL - 0.3 3 mA
Normal - 2 5 mA

- L - 2 100

- LL - 1 50

µ
µ

A

A

A
A

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

2



UTRON

Rev. 1.1

CAPACITANCE

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C
Input/Output Capacitance C

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 100pF, IOH/IOL = -1mA/4mA

(TA=25℃, f=1.0MHz)

8K X 8 BIT LOW POWER CMOS SRAM

IN

I/O

-

-

10 pF

UT6264C

8 pF

AC ELECTRICAL CHARACTERISTICS

(V

= 4.5V~5.5V, TA = 0℃ to 70℃)

CC

(1) READ CYCLE

PARAMETER

Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change

(2) WRITE CYCLE

PARAMETER SYMBOL

Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write-Time
Output Active from End of Write
Write to Output in High-Z

*These parameters are guaranteed by device characterization, but not production tested.

SYMBOL

tRC 35 - 70 - ns
tAA - 35 - 70 ns
t

ACE1, tACE2

tOE - 25 - 35 ns
t

CLZ1*, tCLZ2*

t

OLZ*

t

CHZ1*, tCHZ2*

t

OHZ*

tOH 5 - 5 - ns

tWC 35 - 70 - ns
tAW 30 - 60 - ns
t

CW1, tCW2

tAS 0 - 0 - ns
tWP 25 - 50 - ns
tWR 0 - 0 - ns
tDW 20 - 30 - ns
tDH 0 - 0 - ns
t

OW*

t

WHZ*

- 35 - 70 ns

5 - 5 - ns

- 25 - 35 ns

30 - 60 - ns

5 - 5 - ns

- 15 - 25 ns

UT6264C-35 UT6264C-70

MIN. MAX. MIN. MAX.

UNIT

10 - 10 - ns

- 25 - 35 ns

UT6264C-35 UT6264C-70

MIN. MAX. MIN. MAX.

UNIT

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

3



Rev. 1.1

UTRON

8K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE

1 (Address Controlled)

Address

t

AA

t

OH

DOUT Data Valid

(

READ CYCLE 2

Address

, CE2 and

1CE

(1,2,4)

Controlled)

OE

t

RC

t

(1,3,5,6)

RC

UT6264C

t

OH

AA

t

ACE1

CE1

CE2

OE

CLZ1

t

CLZ2

t

CLZ2

, t

HIGH-Z

, t

OLZ

CHZ1

Dout

Notes :

1.

is HIGH for a read cycle.

WE

2. Device is continuously selected

3. Address must be valid prior to or coincident with

is low.

4.

OE

5. t

, t

CLZ1

6. At any given temperature and voltage condition, t

, t

CHZ2

t

and t

t

ACE2

t

OLZ

OE

,

OHZ

and CE2=V

=V

IL

1CE

are specified with CL=5pF. Transition is measured ±500mV from steady state.

OE

t

low

1CE

is less than t

CHZ1

CHZ1

t

CHZ2

t

OHZ

t

OH

t

HIGH-Z

Data Valid

IH.

and CE2 high transition; otherwise tAA is the limiting parameter.

, t

CLZ1

CHZ2

is less than t

CLZ2

, t

is less than t

OHZ

OLZ.

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

4



UTRON

Rev. 1.1

WRITE CYCLE 1

Address

CE1

CE2

WE

Dout

Din

WRITE CYCLE 2

(

Controlled)

WE

AS

t

(

and CE2 Controlled)

1CE

(1,2,3,5,6)

t

t

CW2

t

8K X 8 BIT LOW POWER CMOS SRAM

t

WC

t

AW

CW1

t

t

WP

WHZ

(4) (4)

(1,2,5)

t

WC

High-Z

t

DW

Data Valid

WR

t

OW

t

DH

UT6264C

Address

t

AW

CE1

CE2

WE

t

AS

t

Dout

Din

Notes :

or

1.

WE

2. A write occurs during the overlap of a low

3. During a

and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

5. If the

6. t

and t

OW

must be HIGH or CE2 must be LOW during all address transitions.

1

CE

controlled with write cycle with OE LOW, tWP must be greater than t

WE

LOW transition occurs simultaneously with or after WE LOW transition, the outputs remain in a high Impedance state.

1CE

are specified with CL=5pF. Transition is measured ±500mV from steady state.

WHZ

t

CW1

t

CW2

t

WP

WHZ

, a high CE2 and a low

1CE

High-Z

t

DW

WE

Data Valid

.

t

WR

t

DH

WHZ+tDW

to allow the I/O drivers to turn off

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

5



Rev. 1.1

UTRON

8K X 8 BIT LOW POWER CMOS SRAM

UT6264C

DATA RETENTION CHARACTERISTICS

(TA = 0℃ to 70

℃

)

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Vcc for Data Retention

Data Retention Current

Chip Disable to Data
Retention Time
Recovery Time t

t

= Read Cycle Time

RC*

V

DR

I

DR

t

CDR

t

R

≧ V

1CE

-0.2V or CE2 ≤ 0.2V

CC

Vcc=2V

≧

V

-0.2V or CE2 ≤ 0.2V

CC

1CE

See Data RetentionWaveforms
(below)

2.0 - 5.5 V

-L - 1 50

-LL - 0.5 20

0 - - ns

- - ns

RC*

DATA RETENTION WAVEFORM

controlled)

Low Vcc Data Retention Waveform (1)

CC

V

Vcc

CDR

t

(

CE

1

Data Retention Mode

≧

DR

V

2V

Vcc

R

t

µA
µA

IH

CE1

V

Low Vcc Data Retention Waveform (2)

CC

V

Vcc

CDR

t

IL

CE2

V

≧

CE1

VCC-0.2V

(CE2 controlled)

Data Retention Mode

≧

V

2V

DR

CE2 ≦ 0.2V

Vcc

t

IH

V

R

IL

V

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

6



Rev. 1.1

UTRON

PACKAGE OUTLINE DIMENSION

28 pin 600 mil PDIP Package Outline Dimension

UT6264C

8K X 8 BIT LOW POWER CMOS SRAM

SYMBOL

`

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

UNIT

INCH(BASE) MM(REF)

A1 0.010 (MIN) 0.254 (MIN)
A2

B 0.020 (MAX) 0.508(MAX)

B1 0.055 (MAX) 1.397(MAX)

c 0.012 (MAX) 0.304 (MAX)

D 1.430 (MAX) 36.322 (MAX)

E 0.625 (MAX) 15.87 (MAX)

E1 0.52 (MAX) 13.208 (MAX)

e 0.100 (TYP) 2.540(TYP)

eB 0.6 (TYP) 15.24 (TYP)

L 0.180(MAX) 4.572(MAX)
S 0.06 (MAX) 1.524 (MAX)

Q1 0.08(MAX) 2.032(MAX)

Θ

0.150±0.005 3.810±0.127

o

15

(MAX) 15o(MAX)

7



UTRON

Rev. 1.1

28 pin 330 mil SOP Package Outline Dimension

UT6264C

8K X 8 BIT LOW POWER CMOS SRAM

SYMBOL

UNIT

A 0.112(max) 2.845(max)
A1 0.004(MIN) 0.102(MIN)
A2 0.098±0.005 2.489±0.127

b 0.016(TYP) 0.406(TYP)

c 0.010(TYP) 0.254(TYP)
D 0.713±0.005 18.110±0.127
E 0.331±0.005 8.407±0.127

E1 0.465±0.012 11.811±0.305

e 0.050(TYP) 1.270(TYP)
L 0.0404±0.008 1.0255±0.203

L1 0.067±0.008 1.702±0.203

S 0.047(MAX) 1.194(MAX)

y 0.003(MAX) 0.076(MAX)
θ 0°~10° 0°~10°

INCH(REF) MM(BASE)

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

8



Rev. 1.1

UTRON

8K X 8 BIT LOW POWER CMOS SRAM

UT6264C

ORDERING INFORMATION

PART NO.

UT6264CPC-35 35 2mA 28 PIN PDIP
UT6264CPC-35L 35 2µA 28 PIN PDIP

UT6264CPC-35LL 35 1µA 28 PIN PDIP
UT6264CPC-70 70 2mA 28 PIN PDIP
UT6264CPC-70L 70 2µA 28 PIN PDIP
UT6264CPC-70LL 70 1µA 28 PIN PDIP
UT6264CSC-35 35 2mA 28 PIN SOP
UT6264CSC-35L 35 2µA 28 PIN SOP
UT6264CSC-35LL 35 1µA 28 PIN SOP
UT6264CSC-70 70 2mA 28 PIN SOP

UT6264CSC-70L 70 2µA 28 PIN SOP
UT6264CSC-70LL 70 1µA 28 PIN SOP

ACCESS TIME

(ns)

STANDBY CURRENT

(µA) (TYP.)

PACKAGE

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

9



Rev. 1.1

UTRON

8K X 8 BIT LOW POWER CMOS SRAM

UT6264C

REVISION HISTORY

REVISION DESCRIPTION DATE

Preliminary Rev. 0.1 Original. May 3 ,2001

Rev. 1.0 The timeing waveforms add CE2 control pin. Jun.4,2001
Rev. 1.1 1. Revised package outline dimension.

2. Revised waveform.

Jan 15,2002

UTRON TECHNOLOGY INC. P80028
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

10