Datasheet UT62256SC-70LL, UT62256SC-70L, UT62256SC-70, UT62256SC-35LL, UT62256SC-35L Datasheet (UTRON)

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A

A9 A2 A1 A0 A

A

Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

FEATURES

Access time : 35/70ns (max.)



Low power consumption:



Operating : 60/40 mA (typical.)

Standby : 3mA (typical) normal

Single 5V power supply

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All inputs and outputs are TTL compatible

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Fully static operation



Three state outputs

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Data retention voltage : 2V (min.)

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Package : 28-pin 600 mil PDIP



28-pin 330 mil SOP

FUNCTIONAL BLOCK DIAGRAM

A4

A3

14

13

12

DECODER

A7

A6

A5

A8

I/O1

.

CONTROL

.

I/O8

2uA (typical) L-version 1uA (typical) LL-version

28-pin 8x13.4mm STSOP

.

ROW

.

MEMORY ARRAY

512 ROWS × 512 COLUMNS

.

. .

I/O

. .

.

COLUMN I/O

COLUMN DECODER

UT62256

GENERAL DESCRIPTION

The UT62256 is a 262,144-bit low power CMOS static random access memory organized as 32,768 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology.

The UT62256 is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application.

The UT62256 operates from a single 5V power supply and all inputs and outputs are fully TTL compatible

PIN CONFIGURATION

VCC

VSS

A14

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

I/O3

Vss

1

2

3

4

UT62256

5 6

7

8

9

10

11

12

13

14

28

27

26

25

24 23

22

21

20

19

18

17

16

15

Vcc

WE

A13

A8

A9

A11

OE

A10

CE

I/O8

I/O7

I/O6

I/O5

I/O4

CE

LOGI C

WE

CONTROL

OE

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A14 Address Inputs I/O1 - I/O8 Data Inputs/Outputs

CE

WE

OE

10

11

Chip Enable Input

Write Enable Input

Output Enable Input

OE

A11

A9

A8

A13

WE

Vcc

A14

A12

A7

A6

A5

A4

A3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

PDIP/SOP

UT62256

28 27

26

25

24

23

22

21

20

19

18

17

16

15

VCC Power Supply VSS Ground

STSOP

____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

1

A10

CE

I/O8

I/O7

I/O6

I/O5

I/O4

Vss

I/O3

I/O2

I/O1

A0

A1

A2



t

Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

UT62256

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS V Operating Temperature TA 0 to +70 Storage Temperature T Power Dissipation PD 1 W DC Output Current I Soldering Temperature (under 10 sec0 Tsolder 260

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for

extended period may affect device reliability.

TRUTH TABLE

MODE

Standby H X X High - Z ISB, ISB1 Output Disable L H H High - Z ICC Read L L H D Write L X L DIN I

Note: H = VIH, L=VIL, X = Don't care.

CE

DC ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

Input High Voltage VIH 2.2 - VCC+0.5 V Input Low Voltage VIL - 0.5 - 0.8 V Input Leakage Curren

Output Leakage

Current

Output High Voltage VOH IOH= - 1mA 2.4 - - V Output Low Voltage VOL IOL= 4mA - - 0.4 V

Supply Current

Standby Power Supply Current

I

TEST CONDITION MIN. TYP. MAX. UNIT

ILI

V

ILO

V

CE

or

ICC Cycle time=Min,

I

I/O

ISB

I

CE

SB1

CE

SB

CE

SB1

CE

-LL - 1 50

*

OE

≦VIN ≦VCC

SS

≦V

SS

= 0mA ,

=V

WE

=V

≧

=V

≧

IH

V

CC

IH

V

CC

I/O

or

= VIL

≦V

CE

-0.2V

-0.5 to +7.0 V

TERM

℃

-65 to +150

STG

50 mA

OUT

℃

I/O OPERATION SUPPLY CURRENT

WE

I

OUT

CC

(VCC = 5V±10%, TA = 0℃ to 70℃)

OE

CC

= V

- 1 - 1

IH

- 35 - 60 100 mA Operating Power

- 70 - 40 70 mA

,.

IL

normal

- 1 10 mA

- 0.3 5 mA

-L/-LL - - 3 mA

-L - 2 100

µ µ

µ

A A

A

____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

2



Rev. 1.5

CAPACITANCE

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C Input/Output Capacitance C

Note : These parameters are guaranteed by device characterization, but not production tested.

UTRON

(TA=25℃, f=1.0MHz)

32K X 8 BIT LOW POWER CMOS SRAM

IN

I/O

-

UT62256

8 pF

10 pF

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V Input Rise and Fall Times 5ns Input and Output Timing Reference Levels 1.5V Output Load CL = 100pF, IOH/IOL = -1mA/4mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER

Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change

(2) WRITE CYCLE PARAMETER SYMBOL UT62256-35 UT62256-70 UNIT

Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High Z

*These parameters are guaranteed by device characterization, but not production tested.

SYMBOL

tRC 35 - 70 - ns tAA - 35 - 70 ns t

ACE

tOE - 25 - 35 ns t

CLZ*

t

OLZ*

t

CHZ*

t

OHZ*

tOH 5 - 5 - ns

tWC 35 - 70 - ns tAW 30 - 60 - ns tCW 30 - 60 - ns tAS 0 - 0 - ns tWP 25 - 50 - ns tWR 0 - 0 - ns tDW 20 - 30 - ns tDH 0 - 0 - ns t

OW*

t

WHZ*

(VCC = 5V±10% , TA = 0℃ to 70℃)

UT62256-35 UT62256-70 UNIT

MIN. MAX. MIN. MAX.

- 35 - 70 ns

10 - 10 - ns 5 - 5 - ns

- 25 - 35 ns

MIN. MAX. MIN. MAX.

5 - 5 - ns

- 15 - 25 ns

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

3



Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

Address

t

OH

DOUT Data Valid

READ CYCLE 2

(CE and

OE

t

AA

Controlled)

t

RC

(1,2,4)

t

RC

(1,3,5,6)

UT62256

t

OH

Address

t

AA

CE

t

ACE

OE

t

CLZ

D

OUT

Notes :

1.

2. Device is continuously selected

3. Address must be valid prior to or coincident with

4.

5. t

6. At any given temperature and voltage condition, t

is HIGH for read cycle.

WE

is LOW.

OE

, t

CLZ

OLZ

High-z

, t

and t

CHZ

OHZ

OE

t

OLZ

=V

IL.

CE

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

Data valid

transition; otherwise t

CE

is less than t

CHZ

CLZ

t

CHZ

, t

OHZ

t

OHZ

t

OH

is the limiting parameter.

AA

is less than t

OLZ.

High-Z

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

4



(4)

Rev. 1.5

WRITE CYCLE 1

Address

WRITE CYCLE 2

CE

WE

D

OUT

IN

UTRON

(WEControlled)

t

AS

(

Controlled)

CE

UT62256

32K X 8 BIT LOW POWER CMOS SRAM

(1,2,3,5)

t

WC

t

AW

t

CW

t

WHZ

(1,2,5)

t

WP

High-Z

t

DW

Data Valid

t

WR

t

OW

t

DH

(4)

Address

CE

WE

D

OUT

D

IN

t

AS

t

WHZ

(4)

t

WC

t

AW

t

CW

t

WP

High-Z

t

DW

Data Valid

t

WR

t

DH

Notes :

must be HIGH during all address transitions.

1.

2. A write occurs during the overlap of a low

3. During a

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the CE

6. t

or

WE

to turn off and data to be placed on the bus.

CE

controlled with write cycle with

WE

transition occurs simultaneously with or after WE

LOW

and a low

CE

OE

outputs remain in a high impedance state.

OW

and t

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

WHZ

LOW, t

.

WE

must be greater than t

WP

WHZ+tDW

to allow the drivers

transition, the

LOW

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

5



Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

UT62256

DATA RETENTION CHARACTERISTICS

(TA = 0℃ to 70℃)

PARAMETER SYMBOL TEST CONDITION MIN. TYP. MAX. UNIT

Vcc for Data Retention

Data Retention Current I

V

DR

≧ V

CE

Vcc=3V

-0.2V

CC

2.0 - 5.5 V

- L - 1

50

20*

CE

≧ V

CC

-0.2V

- LL - 0.5

20

5*

Chip Disable to Data

Retention Time Recovery Time

t

= Read Cycle Time

RC*

* Those parameters are limited for temperature below 40℃

t

CDR

t

R

See Data Retention 0 - - ns Waveforms (below)

t

- - ns

RC*

DATA RETENTION WAVEFORM

VCC

CE

V

SS

4.5V

t

CDR

Data Retention Mode

V

CE ≧ V

≧ 2V

DR

CC

-0.2V

4.5V

t

R

A

µ

A

µ

A

µ

A

µ

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

6



C

Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

PACKAGE OUTLINE DIMENSION

28 pin 600 mil PDIP Package Outline Dimension

SYMBOL

UNIT

INCH(BASE) MM(REF)

A1 0.010 (MIN) 0.254 (MIN) A2

B 0.020 (MAX) 0.508(MAX)

B1 0.055 (MAX) 1.397(MAX)

c 0.012 (MAX) 0.304 (MAX) D 1.430 (MAX) 36.322 (MAX) E 0.6 (TYP) 15.24 (TYP)

E1 0.52 (MAX) 13.208 (MAX)

e 0.100 (TYP) 2.540(TYP)

eB 0.625 (MAX) 15.87 (MAX)

L 0.180(MAX) 4.572(MAX) S 0.06 (MAX) 1.524 (MAX)

Q1 0.08(MAX) 2.032(MAX)

Θ

0.150±0.005 3.810±0.127

o

(MAX) 15o(MAX)

15

UT62256

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

7



Rev. 1.5

28 pin 330 mil SOP Package Outline Dimension

UTRON

SYMBOL

32K X 8 BIT LOW POWER CMOS SRAM

UNIT

INCH(BASE) MM(REF)

A 0.120 (MAX) 3.048 (MAX)

A1 0.002(MIN) 0.05(MIN) A2

b 0.0016 (TYP) 0.406(TYP)

c 0.010 (TYP) 0.254(TYP) D 0.728 (MAX) 18.491 (MAX) E 0.340 (MAX) 8.636 (MAX)

E1

e 0.050 (TYP) 1.270(TYP) L 0.05 (MAX) 1.270 (MAX)

L1

S 0.047 (MAX) 1.194 (MAX)

y 0.003(MAX) 0.076(MAX)

Θ

0

0.098±0.005 2.489±0.127

0.465±0.012 11.811±0.305

0.067±0.008 1.702 ±0.203

o

〜

10

o

〜

0

10

UT62256

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

8



Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

28 pin 8mmx13.4mm STSOP Package Outline Dimension

UT62256

Note： E dimension is not including end flash the total of both sides’ end flash is not above 0.3mm.

2

5

UNIT

SYMBOL

INCH(BASE) MM(REF)

A 0.047 (MAX) 1.20 (MAX) A1 A2

0.004±0.002 0.10±0.05

0.039±0.002 1.00±0.05 b 0.006 (TYP) 0.15(TYP) c 0.010 (TYP) 0.254(TYP)

Db

E

0.465±0.004 11.80±0.10

0.315±0.004 8.00±0.10 e 0.022 (TYP) 0.55(TYP)

D

L

L1

0.528±0.008 13.40±0.20

0.020±0.004 0.50±0.10

0.0315±0.004 0.80±0.10

y 0.08(MAX) 0.003(MAX)

o

Θ

0

〜

o

5

0

o

〜

5

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

9



Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

UT62256

ORDERING INFORMATION

PART NO. ACCESS TIME

(ns)

UT62256PC-70 70 5 mA 28PIN PDIP UT62256PC-70L 70

UT62256PC-70LL 70 UT62256SC-35 35 5 mA 28PIN SOP

UT62256SC-35L 35 UT62256SC-35LL 35 UT62256SC-70 70 5 mA 28PIN SOP

UT62256SC-70L 70 UT62256SC-70LL 70 UT62256LS-35L 35 UT62256LS-35LL 35 UT62256LS-70L 70 UT62256LS-70LL 70

STANDBY CURRENT

(µA)

100 µA 50 µA

100 µA 50 µA 100 µA 50 µA 100 µA 50 µA

PACKAGE

28PIN PDIP 28PIN PDIP

28PIN SOP 28PIN SOP

28PIN SOP 28PIN SOP 28PIN STSOP 28PIN STSOP 28PIN STSOP 28PIN STSOP

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

10



Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

UT62256

REVISION HISTORY

REVISION DESCRIPTION DATE

REV. 1.0 Original.

REV 1.1 The value of symbol “E” is revised as 0.35 inch. AUG. 24,1999

REV. 1.2 Combine version_UT62256(normal) and

version_UT62256SC-35 into version_UT62256

REV. 1.4 1. The pin configurations’ name of TSOP-1 is revised as

STSOP.

≧

CE

V

CC

-0.2V.

REV. 1.5

2. The data retention waveform, Add data retention current for temperature below 40℃.

（

page 6

DEC. 8,1999

MAY. 10,2001

）

JUL.11 ,2001

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

11



Rev. 1.5

UTRON

32K X 8 BIT LOW POWER CMOS SRAM

THIS PAGE IS LEFT BLANK INTENTIONALLY.

UT62256

_____________________________________________________________________________________________

UTRON TECHNOLOGY INC. P80025 1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. TEL: 886-3-5777882 FAX: 886-3-5777919

12