Page 1
UTRON
UT61L6416
Preliminary Rev. 0.5
64K X 16 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Fast access time :
8ns(max) for Vcc=3.15V~3.6V
10/12/15ns(max) for Vcc=3.0V~3.6V
Low power consumption
Operating : 195mA (MAX.)
Standby : 30 mA(MAX.)
Single 3.0V~3.6V power supply
Operating temperature:
Commercial : 0℃~70℃
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data byte control :
LB
(I/O1~I/O8)
UB
(I/O9~I/O16)
Package : 44-pin 400mil TSOPⅡ
FUNCTIONAL BLOCK DIAGRAM
MEMORY ARRAY
512 Rows x 128 Columns × 16bits
COLUMN I/O
COLUMN DECODER
I/O
CONTROL
LOGIC
CONTROL
I/O1
VSS
VCC
I/O16
.
.
.
.
.
.
. .
.
A
13
A
14
A
10
. . .
.
.
A12
ROW
DECODER
A
8
A7 A0 A
1
A
2
A3 A4 A5 A6 A
15
A11
A
9
LB
UB
WE
OE
CE
GENERAL DESCRIPTION
The UT61L6416 is a 1,048,576-bit high speed
CMOS static random access memory organized
as 65,536 words by 16 bits.
The UT61L6416 operates from a single 3.0V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
The UT61L6416 is designed for lower and upper
byte access by data byte control.(
LB
UB
)
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A15 Address Inputs
I/O1 - I/O16 Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
LB
Lower-Byte Control
UB
High-Byte Control
VCC Power Supply
VSS Ground
NC No Connection
PIN CONFIGURATION
TSOP II
A1
A2
A3
A4
I/O16
I/O1
I/O2
I/O3
Vcc
Vss
NC
NC
I/O15
I/O13
I/O14
I/O12
Vss
Vcc
I/O11
I/O10
I/O4
I/O5
UT61L6416
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22 23
24
25
26
27
21
CE
OE
A15
A0
I/O7
I/O8
A5
A6
A7
A8
A9
I/O6
I/O9
A14
A13
A12
A10
WE
NC
34
29
30
31
32
33
44
39
40
41
42
43
35
36
37
38
UB
LB
A11
Page 2
UTRON
UT61L6416
Preliminary Rev. 0.5
64K X 16 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM
-0.5 to 4.6 V
Operating Temperature Commercial T
A
0 to 70
℃
Storage Temperature T
STG
-65 to +150
℃
Power Dissipation PD 1 W
DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 secs) Tsolder 260
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
TRUTH TABLE
WE
I/O OPERATION
MODE
CE
OE
LB
UB
I/O1-I/O8 I/O9-I/O16
SUPPLY CURREN
T
Standby H X X X X High – Z High – Z ISB, I
SB1
Output
Disable
L
L
H
H
H
H
L
X
X L High – Z
High – Z
High – Z
High – Z
ICC
Read L
L
L
L
L
L
H
H
H
L
H
L
H
L
L
D
OUT
High – Z
D
OUT
High – Z
D
OUT
D
OUT
I
CC
Write L
L
L
X
X
X
L
L
L
L
H
L
H
L
L
DIN
High – Z
D
IN
High – Z
D
IN
DIN
I
CC
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V~3.6V, TA = 0℃ to 70℃)
PARAMETER
SYMBOL
TEST CONDITION MIN. TYP. MAX. UNIT
Power Voltage VCC 3.0 3.3 3.6 V
Input High Voltage VIH 2.0 - VCC+0.3 V
Input Low Voltage VIL -0.3 - 0.8 V
Input Leakage Current
I
LI
V
SS
≦VIN ≦VCC
- 2 - 2
µ
A
Output Leakage Current
I
LO
V
SS
≦V
I/O
≦V
CC;
Output Disabled
- 2 - 2
µ
A
Output High Voltage VOH IOH= -4mA 2.4 - - V
Output Low Voltage VOL IOL= 8 mA - - 0.4 V
8 - - 200 mA
10 - - 195 mA
12 - - 190 mA
Operating Power
Supply Current
I
CC
Cycle time=min, 100%duty,
I/O=0mA,
CE
=V
IL
;
15 - - 150 mA
Standby Current (TTL)
I
SB
CE
=V
IH,
other pins =VIL or VIH,
- - 30 mA
Standby Current (CMOS)
I
SB1
CE
=V
CC
-0.2V, other pins at 0.2V or
Vcc-0.2V,
- - 10 mA
Page 3
UTRON
UT61L6416
Preliminary Rev. 0.5
64K X 16 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C
IN
-
6 pF
Input/Output Capacitance C
I/O
-
8 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -4mA / 8mA
AC ELECTRICAL CHARACTERISTICS
(VCC =3.0V~3.6V, TA =0℃ to 70℃)
(1) READ CYCLE
PARAMETER SYMBOL
UT61L6416
-8
UT61L6416
-10
UT61L6416
-12
UT61L6416
-15
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
tRC 8 - 10 - 12 - 15 - ns
Address Access Time
tAA - 8 - 10 - 12 - 15 ns
Chip Enable Access Time
t
ACE
- 8 - 10 - 12 - 15 ns
Output Enable Access Time
tOE - 4 - 5 - 6 - 7 ns
Chip Enable to Output in Low Z
t
CLZ*
3 - 3 - 3 - 3 - ns
Output Enable to Output in Low Z
t
OLZ*
0 - 0 - 0 - 0 - ns
Chip Disable to Output in High Z
t
CHZ*
- 4 - 5 - 6 - 7 ns
Output Disable to Output in High Z
t
OHZ*
- 4 - 5 - 6 - 7 ns
Output Hold from Address Change
tOH 3 - 3 - 3 - 3 - ns
LB
,UB
Access Time
tBA - 4 - 5 - 6 - 7 ns
LB
,UB
to High-Z Output
t
BHZ
- 4 - 5 - 6 - 7 ns
LB
,UB
to Low-Z Output
t
BLZ
0 - 0 - 0 - 0 - ns
(2) WRITE CYCLE
PARAMETER SYMBOL
UT61L6416
-8
UT61L6416
-10
UT61L6416
-12
UT61L6416
-15
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 8 - 10 - 12 - 15 - ns
Address Valid to End of Write
tAW 7 - 8 - 9 - 10 - ns
Chip Enable to End of Write
tCW 7 - 8 - 9 - 10 - ns
Address Set-up Time
tAS 0 - 0 - 0 - 0 - ns
Write Pulse Width
tWP 7 - 8 - 9 - 10 - ns
Write Recovery Time
tWR 0 - 0 - 0 - 0 - ns
Data to Write Time Overlap
tDW 5.5 - 6 - 7 - 8 - ns
Data Hold from End of Write Time
tDH 0 - 0 - 0 - 0 - ns
Output Active from End of Write
t
OW*
3 - 3 - 3 - 3 - ns
Write to Output in High Z
t
WHZ*
- 4 - 5 - 6 - 7 ns
LB
,UB
Valid to End of Write
tBW 7 - 8 - 9 - 10 - ns
*These parameters are guaranteed by device characterization, but not production tested.
*8ns for Vcc=3.15V~3.6V
Page 4
UTRON
UT61L6416
Preliminary Rev. 0.5
64K X 16 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
DOUT Data Valid
t
AA
t
OH
t
OH
READ CYCLE 2
(CE and
OE
Controlled)
(1,3,5,6)
t
RC
t
AA
t
ACE
t
BLZ
t
OE
t
CHZ
t
OHZ
t
CLZ
t
BHZ
t
OH
t
OLZ
HIGH-Z
Data Valid
HIGH-Z
Address
CE
LB , UB
OE
Dout
t
BA
Notes :
1.
WE
is HIGH for read cycle.
2. Device is continuously selected
CE
=V
IL.
3. Address must be valid prior to or coincident with
CE
transition; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ, tBHZ
and t
BLZ
are specified with CL = 5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
, t
BHZ
is less than t
BLZ
Page 5
UTRON
UT61L6416
Preliminary Rev. 0.5
64K X 16 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
WRITE CYCLE 1
(WEControlled)
(1,2,3,5)
t
WC
t
AW
t
CW
t
AS
t
WP
t
BW
t
WHZ
t
OW
t
DW
t
DH
t
WR
Address
CE
WE
LB , UB
Dout
Din
Data Valid
High-Z
(4) (4)
WRITE CYCLE 2
(
CE
Controlled)
(1,2,5)
t
WC
t
AW
t
CW
t
AS
t
WR
t
WP
t
BW
t
WHZ
t
DW
t
DH
Data Valid
Address
CE
WE
LB , UB
Dout
Din
High-Z
Notes :
1.
WE
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap of
CE
＝
low ,
WE
＝
low ,
LB
and/or
UB
＝
low.
3. During a
WE
controlled with write cycle with
OE
LOW, tWP must be greater than tWHZ+tDW to allow the drivers to turn
off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CE
low transition occurs simultaneously with or after
WE
low transition, the outputs remain in a high impedance
state.
6. t
OW
and t
WHZ
are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Page 6
UTRON
UT61L6416
Preliminary Rev. 0.5
64K X 16 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
PACKAGE OUTLINE DIMENSION
44 pin 400mil TSOP-Ⅱ PACKAGE OUTLINE DIMENSION
θ
DIMENSIONS IN MILLMETERS DIMENSIONS IN INCHS
SYMBOLS
MIN NOM MAX. MIN. NOM. MAX.
A 1.00 - 1.20 0.039 - 0.047
A1 0.05 - 0.15 0.002 - 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.30 0.35 0.45 0.012 0.014 0.018
c 0.12 - 0.21 0.0047 - 0.083
D 18.313 18.415 18.517 0.721 0.725 0.728
E 11.854 11.836 11.838 0.460 0.466 0.470
E1 10.058 10.180 10.282 0.398 0.400 0.404
e - 0.800 - - 0.0315 L 0.40 0.50 0.60 0.0157 0.020 0.0236
2D - 0.805 - - 0.0317 -
y 0.00 - 0.076 0.000 - 0.003
Θ
0
o
- 5o 0
o
- 5o
Page 7
UTRON
UT61L6416
Preliminary Rev. 0.5
64K X 16 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
ORDERING INFORMATION
COMMERCIAL TEMPERATURE
PART NO.
ACCESS TIME
(ns)
PACKAGE
UT61L6416MC-8 8
44 PIN TSOP-Ⅱ
UT61L6416MC-10 10
44 PIN TSOP-Ⅱ
UT61L6416MC-12 12
44 PIN TSOP-Ⅱ
UT61L6416MC-15 15
44 PIN TSOP-Ⅱ
Page 8
UTRON
UT61L6416
Preliminary Rev. 0.5
64K X 16 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80072
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
REVISION HISTORY
REVISION DESCRIPTION DATE
Preliminary Rev. 0.4 Original. Mar, 2001
Preliminary Rev. 0.5
1. The symbols CE# and OE# and WE# are revised as.
CE
and
OE and
WE
.
2. Separate Industrial and Commercial SPEC.
3. Add access time 15ns range.
4. Delete SOJ package.
Aug 31,2001
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