Page 1
UTRON
UT61L5128
Rev. 1.0
512K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Single 3.3V power supply
Fast access time : 10/12/15 ns
CMOS Low operating power
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Easy memory expansion with
CE
andOE
options.
Package : 44-pin 400mil TSOP-Ⅱ
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
512K×8
MEMORY
ARRAY
COLUMN I/O
CE
OE
WE
A0-A18
Vcc
GND
I/O0-I/O7
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A18 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
NC No Connection
Vcc Power supply
Vss Ground
GENERAL DESCRIPTION
The UT61L5128 is a 4,194,304-bit high speed
CMOS static random access memory organized as
524,288 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.
The UT61L5128 is designed for high speed system
applications. It is particularly suited for use in
high-density high-speed system applications.
The UT61L5128 operates from a single 3.3V
power supply and all inputs and outputs are fully
TTL compatible.
PIN CONFIGURATION
A1
A2
A3
A4
I/O0
I/O1
I/O2
I/O3
Vcc
Vss
A17
A16
Vss
Vcc
UT61L5128
TSOP-II
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22 23
24
25
26
27
21
CE
OE
A15
A0
A5
A6
A7
A8
A9
A14
A13
A12
A10
WE
NC
34
29
30
31
32
33
44
39
40
41
42
43
35
36
37
38
A11
I/O4
I/O5
I/O7
I/O6
NC
NC
NC
NC
NC
A18
NC
NC
NC
NC
Page 2
UTRON
UT61L5128
Rev. 1.0
512K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to VSS V
TERM
-0.5 to VCC+0.5 V
Operating Temperature TA 0 to +70
℃
Storage Temperature T
STG
-65 to +150
℃
Power Dissipation PD 1 W
DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 sec0 Tsolder 260
℃
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
WE
CE
OE
I/O OPERATION SUPPLY CURRENT
Standby X H X High – Z ISB, I
SB1
Output Disable H L H High – Z ICC
Read H L L D
OUT
I
CC
Write L L X DIN I
CC
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V±10%, TA = 0℃ to 70℃)
PARAMETER
SYMBOL
TEST CONDITION MIN. MAX. UNIT
Input High Voltage VIH 2.2 VCC+0.5 V
Input Low Voltage VIL - 0.5 0.8 V
Input Leakage Current ILI
V
SS
≦VIN ≦VCC
- 1 1
µ
A
Output Leakage Current ILO
V
SS
≦V
I/O
≦V
CC
Output Disabled
- 1 1
µ
A
Output High Voltage VOH IOH= - 4mA 2.4 - V
Output Low Voltage VOL IOL= 8mA - 0.4 V
-10 - 170 mA
-12 - 150 mA
Operating Power
Supply Current
ICC Cycle time=Min.
CE
= V
IL
,
I
I/O
= 0mA ,
-15 - 130 mA
-10 - 70 mA
-12 - 60 mA
ISB
CE
=V
IH
other pins are at V
IH
or VIL
-15 - 50 mA
-10 - 20 mA
-12 - 20 mA
Standby Power
Supply Current
I
SB1
CE
=V
IH
other pins are at Vcc-0.2V
or 0.2V
-15 - 20 mA
Page 3
UTRON
UT61L5128
Rev. 1.0
512K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C
IN
-
8 pF
Input/Output Capacitance C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 5ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -1mA/4mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V±10% , TA = 0℃ to 70℃)
(1) READ CYCLE
PARAMETER
SYMBOL UT61L5128-10* UT61L5128-12 UT61L5128-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
tRC 10 - 12 - 15 - ns
Address Access Time
tAA - 10 - 12 - 15 ns
Chip Enable Access Time
t
ACE
- 10 - 12 - 15 ns
Output Enable Access Time
tOE - 4.5 - 5 - 7 ns
Chip Enable to Output in Low Z
t
CLZ*
3 - 3 - 3 - ns
Output Enable to Output in Low Z
t
OLZ*
0 - 0 - 0 - ns
Chip Disable to Output in High Z
t
CHZ*
- 4 - 5 - 6 ns
Output Disable to Output in High Z
t
OHZ*
- 4 - 5 - 6 ns
Output Hold from Address Change
tOH 3 - 3 - 3 - ns
(2) WRITE CYCLE
PARAMETER
SYMBOLUT61L5128-10* UT61L5128-12 UT61L5128-15 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Write Cycle Time
tWC 10 - 12 - 15 - ns
Address Valid to End of Write
tAW 8 - 8 - 10 - ns
Chip Enable to End of Write
tCW 8 - 8 - 10 - ns
Address Set-up Time
tAS 0 - 0 - 0 - ns
Write Pulse Width
tWP 8 - 8 - 10 - ns
Write Recovery Time
tWR 0 - 0 - 0 - ns
Data to Write Time Overlap
tDW 6 - 6 - 7 - ns
Data Hold from End of Write Time
tDH 0 - 0 - 0 - ns
Output Active from End of Write
t
OW*
2 - 2 - 2 - ns
Write to Output in High Z
t
WHZ*
- 5 - 6 - 7 ns
*These parameters are guaranteed by device characterization, but not production tested.
* Vcc = 3.15V to 3.6V
Page 4
UTRON
UT61L5128
Rev. 1.0
512K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
(1,2,4)
t
RC
Address
DOUT Data Valid
t
AA
t
OH
t
OH
READ CYCLE 2
(CE and
OE
Controlled)
(1,3,5,6)
D
OUT
Address
CE
OE
t
RC
t
AA
t
ACE
t
OE
t
CLZ
t
OLZ
High-z
t
OHZ
t
CHZ
Data valid
High-Z
t
OH
Notes :
1.
WE
is HIGH for read cycle.
2. Device is continuously selected
CE
=V
IL.
3. Address must be valid prior to or coincident with
CE
transition; otherwise t
AA
is the limiting parameter.
4.
OE
is LOW.
5. t
CLZ
, t
OLZ
, t
CHZ
and t
OHZ
are specified with CL = 5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, t
CHZ
is less than t
CLZ
, t
OHZ
is less than t
OLZ.
Page 5
UTRON
UT61L5128
Rev. 1.0
512K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
WRITE CYCLE 1
(WEControlled)
(1,2,3,5)
D
OUT
t
WC
t
AW
t
CW
t
WP
t
OW
t
AS
t
WHZ
(4)
High-Z
t
DW
t
DH
(4)
Address
CE
D
IN
Data Valid
WE
t
WR
WRITE CYCLE 2
(
CE
Controlled)
(1,2,5)
High-Z
(4)
Data Valid
D
OUT
t
WC
t
AW
t
CW
t
WP
t
WHZ
t
AS
t
WR
t
DW
t
DH
Address
CE
WE
D
IN
Notes :
1.
WE
or
CE
must be HIGH during all address transitions.
2. A write occurs during the overlap of a low
CE
and a low
WE
.
3. During a
WE
controlled with write cycle with
OE
LOW, t
WP
must be greater than t
WHZ+tDW
to allow the drivers to turn off and
data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the
CE
LOW transition occurs simultaneously with or after
WE
LOW transition, the outputs remain in a high
impedance state.
6. t
OW
and t
WHZ
are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Page 6
UTRON
UT61L5128
Rev. 1.0
512K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
PACKAGE OUTLINE DIMENSION
44pin 400mil TSOP-Ⅱ Package Outline Dimension
θ
1. CONTROLLING DIMENSION: INCH
2. LEAD FRAME MATERIAL: ALLOY 42
3. DIMENSION “D” DOES NOT INCLUDE MOLD FLASH, THE BAR BURRS AND GATE BURRS.MOLD FLASH, TIE BAR BURRS
AND GATE BURRS SHALL NOT EXCEED 0.006”[0.15mm] PER END DIMENSION “E1” DOES NOT INCLUDE INTERLEAD
FLASH, INTERLEAD FLASH SHALL NOT EXCEED 0.010”[0.25mm] PER SIDE.
4. DIMENSION “b” DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALLBE
0.003”[0.008mm] TOTAL IN EXCEED OF THE “b” DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.0028”[0.07mm]
5. TOLERANCE: ±0.010”[0.25mm] UNLESS OTHERWISE SPECIFIED.
6. OTHERWISE DIMENSION FOLLOW ACCEPTABLE SPEC.
7. REFERENCE DOCUMENT: JEDEC SPEC. MS-024
DIMENSIONS IN MILLMETERS DIMENSIONS IN INCHS SYMBOLS
MIN NOM MAX. MIN. NOM. MAX.
A 1.00 - 1.20 0.039 - 0.047
A1 0.05 - 0.15 0.002 - 0.006
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.30 0.35 0.45 0.012 0.014 0.018
c 0.12 - 0.21 0.0047 - 0.083
D 18.313 18.415 18.517 0.721 0.725 0.728
E 11.854 11.836 11.838 0.460 0.466 0.470
E1 10.058 10.180 10.282 0.398 0.400 0.404
e - 0.800 - - 0.0315 -
L 0.40 0.50 0.60 0.0157 0.020 0.0236
2D - 0.805 - - 0.0317 -
y 0.00 - 0.076 0.000 - 0.003
Θ
0
o
- 5o 0
o
- 5o
Page 7
UTRON
UT61L5128
Rev. 1.0
512K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
ORDERING INFORMATION
PART NO. ACCESS TIME
(ns)
PACKAGE
UT61L5128MC-10 10
44 PIN TSOP-Ⅱ
UT61L5128MC-12 12
44 PIN TSOP-Ⅱ
UT61L5128MC-15 15
44 PIN TSOP-Ⅱ
Page 8
UTRON
UT61L5128
Rev. 1.0
512K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80061
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
REVISION HISTORY
REVISION DESCRIPTION DATE
Preliminary Rev. 0.1 Original. Jun 5, 2001
Rev.1.0 1. Add test condition for I
SB.
2. Add note to Vcc for access time=10ns.
Jun 23,2001
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