Datasheet UT6164CLC-15, UT6164CLC-12, UT6164CLC-10, UT6164CJC-15, UT6164CJC-10 Datasheet (UTRON)

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

1



FEATURES



Fast access time : 10/12/15 ns (max.)



Low operating power consumption :

80 mA (typical)



Single 5V power supply



All inputs and outputs TTL compatible



Fully static operation



Three state outputs



Package : 28-pin 300 mil SOJ

28-pin 8mm×13.4mm STSOP

FUNCTIONAL BLOCK DIAGRAM

MEMORY ARRAY

128 ROWS X 512 COLUMNS

COLUMN I/O

COLUMN DECODER

ROW

DECODER

I/O

CONTROL

LOGIC

CONTROL

A4

I/O1

V

V

WE

OE

1CE

I/O8

.

.

.

.

.
.

. .

.

A5

A6 A7 A

8

A11

A12

A

9 A3 A2 A1 A0

A

10

.

.

.

.

.

.

CE2

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A12 Address Inputs

I/O1 - I/O8 Data Inputs/Outputs

1CE

、

CE2

Chip Enable Input

WE

Write Enable Input

OE

Output Enable Input

VCC Power Supply

VSS Ground

GENERAL DESCRIPTION

The UT6164C is a 65,536-bit high-speed CMOS
static random access memory organized as 8,192
words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.

The UT6164C is designed for high-speed system
applications. It is particularly suited for use in
high-density high-speed system applications.

The UT6164C operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible.

PIN CONFIGURATION

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

Vcc

A8

A9

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

UT6164C

SOJ

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

WE

OE

CE2

NC

CE1

I/O4

A11

A9

A8

CE2

I/O3

A10

NC

A12

A7

A6

A5

Vcc

I/O8

I/O7

I/O6

I/O5

Vss

I/O2

I/O1

A0

A1

A2

A4

A3

UT6164C

STSOP

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

WE

OE

CE1

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

2



ABSOLUTE MAXIMUM RATINGS

*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to Vss V

TERM

-0.5 to +6.5 V

Operating Temperature TA 0 to +70

℃

Storage Temperature T

STG

-65 to +150

℃
Power Dissipation PD 1 W
DC Output Current I

OUT

50 mA

Soldering Temperature (under 10 sec) Tsolder 260

℃

*Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect device reliability.

TRUTH TABLE

MODE

1

CE

CE2

OE

WE

I/O OPERATION SUPPLY CURRENT

Standby H X X X High - Z

I

SB

,

I

SB1

Standby X L X X High - Z

I

SB

,

I

SB1

Output Disable L H H H High - Z I

CC

Read L H L H D

OUT

I

CC

Write L H X L D

IN

I

CC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

(VCC = 5V±10%, TA = 0℃ to 70℃)

PARAMETER SYMBOL TEST CONDITION MIN. MAX. UNIT

Input High Voltage

V

IH

2.2 VCC+0.5 V

Input Low Voltage

V

IL

- 0.5 0.8 V

Input Leakage Current

I

LI

V

SS

≦

V

IN

≦

VCC

- 1 1

µ

A

Output Leakage Current I

LO

V

SS

≦

V

I/O

≦

V

CC

1CE

=V

IH

or CE2=VIL or

OE

=V

IH

or

WE

=VIL

- 1 1

µ

A

Output High Voltage

V

OH

I

OH

= - 4mA 2.4 - V

Output Low Voltage

V

OL

I

OL

= 8mA - 0.4 V

- 10 - 180 mA

- 12 - 160 mA

Operating Power
Supply Current

I

CC

Cycle time=Min.

1CE

= V

IL ,

CE2= VIH

I

I/O

=

0mA

- 15 - 140 mA

Standby Current (TTL) I

SB

1CE

= V

IH or

CE2= V

IL

- 30 mA

Standby Current (CMOS) I

SB1

1CE

≧

V

CC

-0.2V or CE2

≦

0.2V

- 5 mA

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

3



CAPACITANCE

(TA=25℃, f=1.0MHz)

PARAMETER SYMBOL MIN. MAX. UNIT

Input Capacitance

C

IN

-

8 pF

Input/Output Capacitance

C

I/O

-

10 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL=30pF, IOH/IOL=-4mA/8mA

AC ELECTRICAL CHARACTERISTICS

(VCC = 5V±10% , TA = 0℃ to 70℃)

(1) READ CYCLE

UT6164C-10 UT6164C-12 UT6164C-15 UNIT

PARAMETER

SYMBOL

MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

tRC

10

- 12 - 15 -

ns

Address Access Time

tAA

-

10 - 12 - 15

ns

Chip Enable Access Time

t

ACE

-

10 - 12 - 15

ns

Output Enable Access Time

tOE

-

5 - 6 - 7

ns

Chip Enable to Output in Low Z

t

CLZ*

2

- 3 - 4 -

ns

Output Enable to Output in Low Z

t

OLZ*

0

- 0 - 0 -

ns

Chip Disable to Output in High Z

t

CHZ*

-

5 - 6 - 7

ns

Output Disable to Output in High Z

t

OHZ*

-

5 - 6 - 7

ns

Output Hold from Address Change

tOH

3

- 3 - 3 -

ns

(2) WRITE CYCLE

UT6164C-10 UT6164C-12 UT6164C-15 UNIT

PARAMETER SYMBOL

MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time

tWC

10

- 12 - 15 - ns

Address Valid to End of Write

tAW

8

- 10 - 12 - ns

Chip Enable to End of Write

tCW

8

- 10 - 12 - ns

Address Set-up Time

tAS

0

- 0 - 0 - ns

Write Pulse Width

tWP

8

- 9 - 10 - ns

Write Recovery Time

tWR

0

- 0 - 0 - ns

Data to Write Time Overlap

tDW

6

- 7 - 8 - ns

Data Hold from End of Write Time

tDH

0

- 0 - 0 - ns

Output Active from End of Write

t

OW*

2

- 3 - 4 - ns

Write to Output in High Z

t

WHZ*

- 6 - 7 - 8

ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

4



TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2,4)

t

RC

Address

DOUT Data Valid

t

AA

t

OH

t

OH

READ CYCLE 2

(

1CE

、

CE2

and

OE

Controlled)

(1,3,5,6)

t

RC

t

AA

t

ACE1

t

ACE2

t

OE

t

CHZ1

t

CHZ2

t

OHZ

t

CLZ1

t

CLZ2

t

OH

t

OLZ

HIGH-Z

Data Valid

HIGH-Z

Address

CE1

CE2

OE

Dout

Notes :

1.

WE

is high for read cycle.

2. Device is continuously selected

1CE

=V

IL

and CE2=V

IH.

3. Address must be valid prior to or coincident with

1CE

and CE2 transition; otherwise t

AA

is the limiting parameter.

4.

OE

is low.

5. t

CLZ1

, t

CLZ2

, t

OLZ

, t

CHZ1

, t

CHZ2

and t

OHZ

are specified with CL=5pF. Transition is measured ±500mV from steady

state.

6. At any given temperature and voltage condition, t

CHZ1

is less than t

CLZ1

, t

CHZ2

is less than t

CLZ2

, t

OHZ

is less than

t

OLZ.

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

5



WRITE CYCLE 1

(WEControlled)

(1,2,3,5)

t

WC

t

AW

t

CW1

t

AS

t

WP

t

WH

t

OW

t

DW

t

DH

t

CW2

t

WR

Address

CE1

CE2

WE

Dout

Din

Data Valid

High-Z

(4) (4)

WRITE CYCLE 2

(

1CE

、

CE2

Controlled)

(1,2,5)

t

WC

t

AW

t

CW1

t

AS

t

WR

t

CW2

t

WP

t

WHZ

t

DW

t

DH

Data Valid

Address

CE1

CE2

WE

Dout

Din

High-Z

Notes :

1.

WE

or

1CE

must be high or CE2 must be low during all address transitions.

2. A write occurs during the overlap of a low

1CE

, a high CE2 and a low

WE

.

3. During a

WE

controlled with write cycle with

OE

low, t

WP

must be greater than t

WHZ+tDW

to allow the I/O drivers

to turn off and data to be placed on the bus.

4. During this period, I/O pins are in the output state, and input singals must not be applied.

5. If the

1CE

low and CE2 high transition occurs simultaneously with or after

WE

low transition, the outputs remain in a high

impedance state.

6. t

OW

and t

WHZ

are specified with CL=5pF. Transition is measured ±500mV from steady state.

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

6



PACKAGE OUTLINE DIMENSION

28 pin 300 mil SOJ Package Outline Dimension

1

28

14

15

A2

L

C

XX

X

Note:

1.

S/E/D DIM NOT INCLUDEING MOLD FLASH.

2.

THE END FLASH IN PACKAGE LENGTHWISE IS
NOT MORE THAN 10 MILS EACH SIDE

UNIT

SYMBOL

INCH(BASE) MM(REF)

A 0.148 (MAX) 3.759 (MAX)
A1 0.026(MIN) 0.660(MIN)
A2

0.100±0.005 2.540±0.127

B 0.018 (TYP) 0.457(TYP)
B1 0.028 (TYP) 0.711(TYP)

c 0.010 (TYP) 0.254 (TYP)
D 0.710 (TYP) 18.034 (TYP)
E 0.335(TYP) 8.509(TYP)

E1 0.3 (TYP) 7.620(TYP)

e 0.050 (TYP) 1.270 (TYP)

L

0.087±0.010 2.210±0.254
S 0.030 (TYP) 0.762 (TYP)
Y 0.003(MAX) 0.076(MAX)

D

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

7



28 pin 8x13.4mm STSOP PACKAGE OUTLINE DIMENSION

1

14 15

28

c

L

HD

D

"A"

b

E

e

12°(2x)12°(2x)

Seating Plane

y

28

15

14

1

c

A2A1

L

A

0.254

0

GAUGE PLANE

12°(2X)

12°(2X)

SEATING PLANE

"A" DATAIL VIEW

L1

Note：
E dimension is not including end flash
the total of both sides’ end flash is
not above 0.3mm.

UNIT

SYMBOL

INCH(BASE) MM(REF)

A 0.047 (MAX) 1.20 (MAX)

A1

0.004±0.002 0.10±0.05

A2

0.039±0.002 1.00±0.05

b

0.008±0.001 0.200±0.025

c 0.005 (TYP) 0.127(TYP)

Db

0.465±0.004 11.80±0.10

E

0.315±0.004 8.00±0.10

e 0.022 (TYP) 0.55(TYP)

D

0.528±0.008 13.40±0.20

L

0.0236±0.004 0.50±0.10

L1

0.0315±0.004 0.80±0.10

y 0.003(MAX) 0.076(MAX)

Θ

0

o

〜

5

o

0

o

〜

5

o

H H C

H

F

C

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

8



ORDERING INFORMATION

PART NO. ACCESS TIME (ns) PACKAGE

UT6164CJC-10 10 28 PIN SOJ
UT6164CJC-12 12 28 PIN SOJ
UT6164CJC-15 15 28 PIN SOJ
UT6164CLS-10 10 28 PIN STSOP
UT6164CLS-12 12 28 PIN STSOP
UT6164CLS-15 15 28 PIN STSOP

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

9



REVISION HISTORY

REVISION DESCRIPTION DATE

Rev. 1.0 Original Oct 15,2001

UTRON

UT6164C

Rev. 1.0

8K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80074
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

10



THIS PAGE IS LEFT BLANK INTENTIONALLY.