Fast access time : 10/12/15ns (max.)
Low operating power consumption:
Single5V power supply
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Package : 32-pin 288 mil skinny PDIP
FUNCTIONAL BLOCK DIAGRAM
A4
A5
A6
7
A8
A12
DECODER
A13
A14
A15
A16
I/O 1
.
.
.
.
.
CONTROL
.
I/O 8
1CE
CE2
CONTROL
WE
OE
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A16 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
100 mA (typical.)
32-pin 300 mil SOJ
32-pin 8mm×20mm TSOP-1
32-pin 8mm×13.4mm STSOP
The UT611024 is a 1,048,576-bit high speed
CMOS static random access memory organized
as 131,072 words b y 8 bits. It is fabricated usi ng
high performance, high reliability CMOS
technology.
The UT611024 is designed for high-sp eed s ystem
application. It is particularly suited for use in high
speed and high density system applications.
The UT611024 operates from a signal 5 V power
supply and all inputs and outputs are fully TTL
compatible
PIN CONFIGURATION
A11
A9
A8
A13
WE
CE2
A15
Vcc
NC
A16
A14
A12
A7
A6
A5
A4A3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
31
30
29
UT611024
28
27
26
25
24
23
22
21
20
19
18
1716
PDIP / SOJ
UT611024
STSOP / TSOP-1
A15
CE2
A13
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
Vcc
WE
A8
A9
OE
1CE
32
OE
A10
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
Page 2
Rev. 1.5
UTRON
128K X 8 BIT HIGH SPEED CMOS SRAM
UT611024
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Terminal Voltage w ith Respect to VSS V
Operating Temperature TA 0 to +70
Storage Temperature T
Power Dissipation PD 1 W
DC Output Current I
Soldering Temperature (under 10 sec) Tsolder 260
*Stresses greater than those listed under “Absolute Maxim um Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.
TRUTH TABLE
MODE
Standby H X X X High - Z ISB, ISB1
Standby X L X X High - Z ISB, ISB1
Output Disable L H H H High - Z ICC
Read L H L H D
Write L H X L DIN I
Note: H = VIH, L=VIL, X = Don't care.
CE
1
DC ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITION MIN. MAX. UNIT
Input High Voltage VIH 2.2 VCC+0.5 V
Input Low Voltage VIL -0.5 0.8 V
Input Leakage Current ILI
Output Leakage
Current
Output High Voltage VOH IOH= - 4mA 2.4 - V
Output Low Voltage VOL IOL= 8mA - 0.4 V
Operating Power
Supply Current
Standby Power
Supply Current
Notes : VIL = -3.0V for pulse width less than 10ns.
ILO
ICC Cycle time =Min., I
ISB
I
SB1
*
CE2
≦VIN ≦VCC
V
SS
V
≦V
SS
or
OE
1CE
1CE
≧
V
IN
1CE
≧
V
IN
-0.5 to + 7.0 V
TERM
-65 to +150
STG
50 mA
OUT
I/O OPERATION SUPPLY CURRENT
OE
WE
(VCC = 5V±10%, TA = 0℃ to 70℃)
- 1 1
≦V
= V
=V
V
IH
≧
V
CC
I/O
=V
IL
or V
V
CC,
or
WE
IH
,CE2= VIH
or CE2=V
IH
≦
V
IN
-0.2V or CE2≦0.2V
CC
-0.2V or V
= V
I/O
IL
IN
or CE2=VIL
=V
1CE
IH
IL
= 0mA ,
IL
≦
0.2V
℃
℃
℃
I
OUT
CC
CC
- 1 1
- 10 - 180 mA
- 12 - 160 mA
- 15 - 140 mA
- 30 mA
- 5 mA
A
µ
A
µ
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
Page 3
Rev. 1.5
CAPACITANCE
PARAMETER SYMBOL MIN. MAX UNIT
Input Capacitance C
Input/Output Capacitance C
Note : These parameters are guarant eed by devi ce characterization, but not production tested.
UTRON
(TA=25℃, f=1.0MHz)
128K X 8 BIT HIGH SPEED CMOS SRAM
I/O
IN
-
-
UT611024
8 pF
10 pF
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -1mA/4 mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z
*These parameters are guaranteed by device characterization, but not production tested.
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
Page 4
A
UTRON
Rev. 1.5
TIMING WAVEFO RMS
READ CYCLE 1
(Address Controlled)
ddress
t
OH
D
OUT
,
READ CYCLE 2
(
CE2
1CE
128K X 8 BIT HIGH SPEED CMOS SRAM
(1,2,4)
t
RC
t
AA
Data Valid
OE
Controlled)
t
(1,3,5,6)
RC
and
UT611024
t
OH
Address
AA
t
ACE1
CE1
CE2
OE
CLZ1
t
CLZ2
t
, t
OLZ
HIGH-Z
, t
CHZ1
Dout
Notes :
1.
2. Device is continuousl y selected
3. Address must be val i d pri o r t o or coincident with
4.
5. t
6. At any given temperature and voltage condition, t
is HIGH for read cycle.
WE
is low.
OE
, t
CLZ1
CLZ2
, t
CHZ2
t
and t
t
ACE2
t
OLZ
=V
and CE2=V
IL
CE
1
are specified with CL=5pF. Transition is measured ±500mV from st eady state.
OHZ
CHZ1
OE
t
t
Data Valid
IH.
and CE2 transit i on; otherwise tAA is the limiting parameter.
CE
1
is less than t
CHZ1
CLZ1
, t
CHZ2
t
OHZ
t
OH
is less than t
t
CHZ2
CLZ2
, t
OHZ
HIGH-Z
is less than t
OLZ.
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
Page 5
Rev. 1.5
WRITE CYCLE 1
Address
CE1
CE2
WE
Dout
Din
WRITE CYCLE 2
UTRON
(
Controlled)
WE
t
AS
(
and CE2 Controlled)
CE
1
128K X 8 BIT HIGH SPEED CMOS SRAM
(1,2,3,5)
WC
t
AW
t
CW1
t
CW2
t
WR
t
WP
t
WH
t
(4)(4)
(1,2,5)
WC
t
High-Z
t
DW
Data Valid
t
DH
t
UT611024
OW
Address
AW
t
CE1
CE2
WE
Dout
Din
AS
t
WHZ
t
t
t
CW1
t
WP
CW2
High-Z
DW
t
Data Valid
WR
t
DH
t
Notes :
1.
2. A write occurs during the overlap of a l ow
3. During a
4. During this period, I/O pins are in the output state, and i nput singals must not be appl i ed.
4. If the
6. t
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
or
WE
off and data to be placed on the bus.
Impedance state.
and t
OW
must be HIGH or CE2 must be LOW during all address transi t i ons.
CE
1
controlled with write cycle with OE LOW, tWP must be greater than t
WE
LOW transition occurs s i multaneously with or after WE LOW transition, the outputs remain in a high
CE
1
are specified with CL=5pF. Transition is measured ±500mV from st eady state.
WHZ
, a high CE2 and a low WE.
CE
1
5
WHZ+tDW
to allow the I/O drivers to turn
Page 6
Rev. 1.5
UTRON
PACKAGE OUTLINE DIMENSION
32 pin 288 mil PDIP Package Outline Dimension
UT611024
128K X 8 BIT HIGH SPEED CMOS SRAM
UNIT
INCH(BASE) MM(REF)
SYMBOL
A
0.130 ±0.005 3.302 ±0.127
A1 0.015(MIN) 0.381 (MIN)
B
B1
c
D
E
E1
0.018 ±0.004 0.457 ±0.102
0.050 ±0.008 1.270 ±0.203
0.010 ±0.004 0.254 ±0.102
1.600 ±0.005 40.640 ±0.127
0.315 ±0.010 8.001 ±0.254
0.288 ±0.004 7.315 ±0.102
e1 0.100 TYP 2.540 TYP
eB
0.350 ±0.020 8.890 ±0.508
L 0.125 (MIN) 3.175 (MIN)
C
Q1
1c
0.060 ±0.005 1.524 ±0.127
o
o
〜
0
10
0
o
o
〜
10
Note:
1. All EDGE WITH MATTE FINIS H.
2.
DIMENSION D AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSION.
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
Page 7
Rev. 1.5
32 pin SOJ Package Outline Dimension
UTRON
UT611024
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
B 0.018 (TYP) 0.457(TYP)
B1 0.028 (TYP) 0.711 (TYP)
C 0.010 (TYP) 0.254 (TYP)
D 0.830 (MAX) 21.082 (MAX)
E 0.335 (TYP) 8.509 (TYP)
E1
e 0.050 (TYP) 1.270 (TYP)
L
y 0.003 (MAX) 0.076 (MAX)
0.100 ±0.005 2.540 ±0.127
0.300 ±0.005 7.620 ±0.127
0.086 ±0.010 2.184 ±0.254
7
Page 8
Rev. 1.5
32 pin TSOP-I Package Outline Dimension
UTRON
UT611024
128K X 8 BIT HIGH SPEED CMOS SRAM
UNIT
SYMBOL
A 0.047 (MAX) 1.20 (MAX)
A1
A2
b
C 0.005 (TYP) 0.127 (TYP)
D
E
E 0.020 (TYP) 0.50 (TYP)
HD
L
L1
y 0.003 (MAX) 0.076 (MAX)
Θ
0
INCH(BASE) MM(REF)
0.004 ±0.002 0.10 ±0.05
0.039 ±0.002 1.00 ±0.05
0.008 + 0.002
- 0.001
0.724 ±0.004 18.40 ±0.10
0.315 ±0.004 8.00 ±0.10
0.787 ±0.008 20.00 ±0.20
0.0197 ±0.004 0.50 ±0.10
0.0315 ±0.004 0.08 ±0.10
o
o
〜
5
0
0.20 + 0.05
-0.03
o
o
〜
5
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
Page 9
y
Rev. 1.5
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
UTRON
128K X 8 BIT HIGH SPEED CMOS SRAM
HD
D
UT611024
E
b
Unit
Symbol
A 1.20(Max.) 0.047(Max).
A1
A2
b 020(typ.) 0.006(typ.)
c 0.15(typ.) 0.006(typ.)
D
Db
E
e 0.50(typ.) 0.020(typ.)
L
L1
0.08(Max.) 0.003(Max.)
e
MM(REF) INCH(BASE)
0.1060.05 0.00460.002
1.0060.05 0.03960.002
13.4060.20 0.52660.006
11.8060.10 0.46560.004
8.00060.10 0.31560.004
0.5060.10 0.02060.004
0.8060.10 0.031560.004
08~58 08~58
0
0.254
Note:
1.E dinmension is not including end
flash.
2.The total of both sides’ end flash Is not
above 0.3mm.
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
Page 11
Rev. 1.5
UTRON
128K X 8 BIT HIGH SPEED CMOS SRAM
UT611024
REVISION HISTORY
REVISION DESCRIPTION DATE
Rev. 1.0 Original.
Rev. 1.1 Add Data Retention Section Jan 14,2000
Rev. 1.2 NA Nov,2000
Rev 1.4 1. The symbols CE1#,OE# and WE# are revised as
Rev.1.5
and
1CE,OE
2. Delete data retention section.
Add note in DC ELECTRICAL CHARACTERISTICS section:
V
= -3.0V for pulse width less than 10ns.
IL
WE
Jun 18,2001
Oct 30,2001
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
Page 12
Rev. 1.5
UTRON
THIS PA GE IS LEFT BLANK INTENTIONALLY.
UT611024
128K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
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