Page 1
1 RadHard MSI Logic
UT54ACS00/UT54ACTS00
Radiation-Hardened
Quadruple 2-Input NAND Gates
FEATURES
• 1.2µ radiation-hardened CMOS
- Latchup immune
• High speed
• Low power consumption
• Single 5 volt supply
• Available QML Q or V processes
• Flexible package
- 14-pin DIP
- 14-lead flatpack
DESCRIPTION
The UT54ACS00 and the UT54ACTS00 are quadruple, twoinput NAND gates. The circuits perform the Boolean functions
Y = A⋅B or Y = A + B in positive logic.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
LOGIC SYMBOL
PINOUTS
14-Pin DIP
Top View
14-Lead Flatpack
Top View
LOGIC DIAGRAM
INPUTS OUTPUT
A B Y
H H L
L X H
X L H
Y1
(3)
(6)
Y2
Y3
(8)
(11)
Y4
(1)
A1
(2)
B1
(4)
A2
(5)
B2
(9)
A3
(10)
B3
(12)
A4
(13)
B4
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
&
1 14
2 13
3 12
4 11
5 10
6 9
7 8
A1
B1
Y1
A2
B2
Y2
V
SS
V
DD
B4
A4
Y4
B3
A3
Y3
V
DD
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
V
SS
1 14
2 13
3 12
4 11
5 10
6 9
7 8
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
Page 2
RadHard MSI Logic 2
UT54ACS00/UT54ACTS00
RADIATION HARDNESS SPECIFICATIONS
1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1.Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold
2
80
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence 1.0E14
n/cm
2
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage -0.3 to 7.0 V
V
I/O
Voltage any pin -.3 to VDD +.3 V
T
STG
Storage Temperature range -65 to +150 °C
T
J
Maximum junction temperature +175 °C
T
LS
Lead temperature (soldering 5 seconds) +300 °C
Θ
JC
Thermal resistance junction to case 20 °C/W
I
I
DC input current ±10 mA
P
D
Maximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage 4.5 to 5.5 V
V
IN
Input voltage any pin 0 to V
DD
V
T
C
Temperature range -55 to + 125 °C
Page 3
3 RadHard MSI Logic
UT54ACS00/UT54ACTS00
DC ELECTRICAL CHARACTERISTICS
7
(V
DD
= 5.0V ±10%; V
SS
= 0V 6, -55°C < TC < +125°C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
IL
Low-level input voltage
1
ACTS
ACS
0.8
.3V
DD
V
V
IH High-level input voltage
1
ACTS
ACS
.5V
DD
.7V
DD
V
I
IN
Input leakage current
ACTS/ACS VIN = V
DD
or V
SS
-1
1 µA
V
OL
Low-level output voltage
3
ACTS
ACS
I
OL
= 8.0mA
I
OL
= 100µA
0.40
0.25
V
V
OH High-level output voltage
3
ACTS
ACS
I
OH
= -8.0mA
I
OH
= -100µA
.7V
DD
VDD - 0.25
V
I
OS Short-circuit output current
2 ,4
ACTS/ACS
VO = VDD and V
SS
-200 200 mA
I
OL
Output current
10
(Sink)
VIN = VDD or V
SS
VOL = 0.4V
8 mA
I
OH
Output current
10
(Source)
VIN = VDD or V
SS
VOH = VDD - 0.4V
-8 mA
P
total
Power dissipation
2, 8, 9
CL = 50pF 1.8 mW/
MHz
I
DDQ
Quiescent Supply Current VDD = 5.5V 10 µA
∆I
DDQ
Quiescent Supply Current Delta
ACTS
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or V
SS
V
DD
= 5.5V
1.6 mA
C
IN
Input capacitance
5
ƒ = 1MHz @ 0V 15 pF
C
OUT Output capacitance
5
ƒ = 1MHz @ 0V 15 pF
Page 4
RadHard MSI Logic 4
UT54ACS00/UT54ACTS00
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
AC ELECTRICAL CHARACTERISTICS
2
(V
DD
= 5.0V ±10%; V
SS
= 0V 1, -55°C < TC < +125°C)
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
t
PHL
Input to Yn 1 14 ns
t
PLH
Input to Yn 1 11 ns
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