Datasheet UT54ACTS74, UT54ACS74 Datasheet (Aeroflex UTMC)

UT54ACS74/UT54ACTS74

Radiation-Hardened
Dual D Flip-Flops with Clear & Preset

FEATURES

• radiation-hardened CMOS

- Latchup immune

• High speed

• Low power consumption

• Single 5 volt supply

• Available QML Q or V processes

• Flexible package

- 14-pin DIP

- 14-lead flatpack

DESCRIPTION

The UT54ACS74 and the UT54ACTS74 contain two indepen­dent D-type positive triggered flip-flops. A low level at the
Preset or Clear inputs sets or resets the outputs regardless of the
levels of the other inputs. When Preset and Clear are inactive
(high), data at the D input meeting the setup time requirement
is transferred to the outputs on the positive-going edge of the
clock pulse. Following the hold time interval, data at the D
input may be changed without affecting the levels at the outputs.

The devices are characterized over full military temperature
range of -55 C to +125 C.

FUNCTION TABLE

INPUTS OUTPUT

PRE CLR CLK D Q Q

L H X X H L

H L X X L H

L L X X

H H H H L
H H L L H
H H L X Q

Note:

1. The output levels in this configuration are not guaranteed to meet the mini­mum levels for VOH if the lows at preset and clear are near VIL maximum.

In addition, this configuration is nonstable; that is, it will not persist when
either preset or clear returns to its inactive (high) level.

H

1

o

H

1

Q

o

PINOUTS

14-Pin DIP

Top View

CLR1

CLK1
PRE1

V

D1

Q1
Q1

SS

1

14

V

DD

2

13

CLR2

3

12

D2

4

11

CLK2

5

10

PRE2

6

9

Q2

7

8

Q2

14-Lead Flatpack

Top View

CLR1

D1
CLK1
PRE1

Q1

Q1

V

SS

14

2

13

3

12

4

11

5

10

6

9

7

8

V

DD

CLR2
D2
CLK2
PRE2
Q2
Q2

1

LOGIC SYMBOL

(4)

PRE1

(3)

CLK1

(2)

D1

(1)

CLR1

(10)

PRE2

(11)

CLK2

(12)

D2

(13)

CLR2

Note:

1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.

S

D1
R

C1

(5)

(6)

(9)

(8)

Q1

Q1

Q2

Q2

45 RadHard MSI Logic

LOGIC DIAGRAM

PRE

UT54ACS74/UT54ACTS74

CLR

CLK

D

Q

Q

RadHard MSI Logic 46

UT54ACS74/UT54ACTS74

RADIATION HARDNESS SPECIFICATIONS

PARAMETER LIMIT UNITS

Total Dose 1.0E6 rads(Si)

SEU Threshold

2

1

80

MeV-cm2/mg

SEL Threshold 120

Neutron Fluence 1.0E14

Notes:

1. Logic will not latchup during radiation exposure within the limits defined in the table.

2. Device storage elements are immune to SEU affects.

MeV-cm2/mg

2

n/cm

ABSOLUTE MAXIMUM RATINGS

SYMBOL PARAMETER LIMIT UNITS

V

DD

V

I/O

T

STG

T

J

T

LS

JC

I

I

P

D

Note:

1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Maximum junction temperature +175 C

Lead temperature (soldering 5 seconds) +300 C

Thermal resistance junction to case 20 C/W

Supply voltage -0.3 to 7.0 V

Voltage any pin -.3 to VDD +.3 V

Storage Temperature range -65 to +150 C

DC input current 10 mA

Maximum power dissipation 1 W

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMIT UNITS

V

DD

V

IN

T

C

Supply voltage 4.5 to 5.5 V

Input voltage any pin 0 to V

DD

Temperature range -55 to + 125 C

V

47 RadHard MSI Logic

UT54ACS74/UT54ACTS74

DC ELECTRICAL CHARACTERISTICS

7

(VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C)

SYMBOL PARAMETER CONDITION MIN MAX UNIT

V

IL

Low-level input voltage

ACTS
ACS

V

IH

High-level input voltage

ACTS
ACS

I

IN

Input leakage current

ACTS/ACS VIN = V

V

OL

Low-level output voltage

ACTS
ACS

V

OH

High-level output voltage

ACTS
ACS

I

OS

Short-circuit output current

ACTS/ACS

1

0.8

.3V

DD

1

.5V

DD

.7V

DD

or V

DD

3

I

= 8.0mA

OL

I

= 100 A

OL

3

I

= -8.0mA

OH

I

= -100 A

OH

2 ,4

VO = VDD and V

SS

SS

-1

.7V

DD

VDD - 0.25

-200 200 mA

1 A

0.40

0.25

V

V

V

V

I

OL Output current

(Sink)

I

OH

Output current
(Source)

P

total

I

DDQ

I

DDQ

Power dissipation
Quiescent Supply Current VDD = 5.5V 10 A

Quiescent Supply Current Delta
ACTS

C

C

IN

OUT

Input capacitance

Output capacitance 5

10

VIN = VDD or V

SS

8 mA

VOL = 0.4V

10

VIN = VDD or V

SS

-8 mA

VOH = VDD - 0.4V

2, 8, 9

CL = 50pF 1.9 mW/MHz

For input under test

1.6 mA

VIN = VDD - 2.1V
For all other inputs

VIN = VDD or V
V

= 5.5V

DD

5

= 1MHz @ 0V 15 pF

SS

= 1MHz @ 0V 15 pF

RadHard MSI Logic 48

UT54ACS74/UT54ACTS74

Notes:

1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,

- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).

2. Supplied as a design limit but not guaranteed or tested.

3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.

4. Not more than one output may be shorted at a time for maximum duration of one second.

5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at a frequency of 1MHz and a signal amplitude of 50mV rms maximum.

6. Maximum allowable relative shift equals 50mV.

7. All specifications valid for radiation dose 1E6 rads(Si).

8. Power does not include power contribution of any TTL output sink current.

9. Power dissipation specified per switching output.

10. This value is guaranteed based on characterization data, but not tested.

49 RadHard MSI Logic

UT54ACS74/UT54ACTS74

AC ELECTRICAL CHARACTERISTICS

(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)

2

SYMBOL PARAMETER MINIMUM MAXIMUM UNIT

t

PHL

t

PLH

t

PLH

t

PHL

t

PHL

t

PLH

f

MAX

t

SU1

CLK to Q, Q 3 21 ns
CLK to Q, Q 1 20 ns
PRE to Q 1 15 ns
PRE to Q 3 19 ns
CLR to Q 3 19 ns
CLR to Q 1 15 ns
Maximum clock frequency 71 MHz
PRE or CLR inactive

5 ns

Setup time before CLK

t

SU2

t

t

H

W

Data setup time before CLK 5 ns

3

Data hold time after CLK 2 ns

Minimum pulse width

7 ns
PRE or CLR low
CLK high
CLK low

Notes:

1. Maximum allowable relative shift equals 50mV.

2. All specifications valid for radiation dose 1E6 rads(Si).

3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (t

) is >10ns. This is guaranteed, but not tested.

SU2

RadHard MSI Logic 50