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UT54ACS374/UT54ACTS374
Radiation-Hardened
Octal D-Type Flip-Flops with Three-State Outputs
FEATURES
8 latches in a single package
Three-state bus-driving true outputs
Full parallel access for loading
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
DESCRIPTION
The UT54ACS374 and the UT54ACTS374 are non-inverting
octal D type flip-flops with three-state outputs designed for driving highly capacitive or relatively low-impedance loads. The
device is suitable for buffer registers, I/O ports, and bidirectional
bus drivers.
The eight flip-flops are edge triggered D-type flip-flops. On the
positive transition of the clock the Q outputs will follow the data
(D) inputs.
An output-control input (OC) places the eight outputs in either
a normal logic state (high or low logic level) or a high-impedance state. The high-impedance third state and increased drive
provide the capability to drive the bus line in a bus-organized
system without the need for interface or pull-up components.
The output control OC does not affect the internal operations of
the flip-flops. Old data can be retained or new data can be
entered while the outputs are off.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
INPUTS OUTPUT
OC CLK nD nQ
L H H
L L L
L L X nQ
H X X
0
Z
PINOUTS 20-Pin DIP
Top View
1
OC
1Q
1D
2D
2Q
3Q
3D
SS
20
V
2
19
8Q
3
18
8D
4
17
7D
5
16
7Q
6
15
6Q
7
14
6D
8 134D 5D
9 124Q 5Q
10 11V
CLK
DD
20-Lead Flatpack
Top View
1
OC
1Q
1D
2D
2Q
3Q
3D
SS
20
2
19
3
18
4
17
5
16
6
15
7
14
8 134D 5D
9 124Q 5Q
10 11V
V
8Q
8D
7D
7Q
6Q
6D
CLK
DD
LOGIC SYMBOL
(1)
OC EN
(11)
CLK C1
(3)
1D
(4)
2D
(7)
3D
(8)
4D
(13)
5D
(14)
6D
(17)
7D
(18)
8D
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1D
(2)
(5)
(6)
(9)
(12)
(15)
(16)
(19)
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
223 RadHard MSI Logic
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LOGIC DIAGRAM
UT54ACS374/UT54ACTS374
C
D
CD
Q
CD
QQ
RADIATION HARDNESS SPECIFICATIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold
2
SEL Threshold 120
Neutron Fluence 1.0E14
1D2D3D4D5D6D7D8D
(13)(14)(17)(18)
CDCD
Q
1
CD
(4)(7)(8)
(3)
D CCD
QQQQ
1Q2Q3Q4Q5Q6Q7Q8Q
80
OC
CLK
(11)
(1)
(2)(5)(6)(9)(12)(15)(16)(19)
MeV-cm2/mg
MeV-cm2/mg
2
n/cm
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATING
SYMBOL PARAMETER LIMIT UNITS
V
DD
V
I/O
T
STG
T
J
T
LS
JC
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Maximum junction temperature +175 C
Lead temperature (soldering 5 seconds) +300 C
Thermal resistance junction to case 20 C/W
Supply voltage -0.3 to 7.0 V
Voltage any pin -.3 to VDD +.3 V
Storage Temperature range -65 to +150 C
DC input current 10 mA
Maximum power dissipation 1 W
RadHard MSI Logic 224
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UT54ACS374/UT54ACTS374
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMIT UNITS
V
DD
V
IN
T
C
Supply voltage 4.5 to 5.5 V
Input voltage any pin 0 to V
DD
Temperature range -55 to + 125 ×C
V
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UT54ACS374/UT54ACTS374
DC ELECTRICAL CHARACTERISTICS
7
(VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
IL
Low-level input voltage
ACTS
ACS
V
IH
High-level input voltage
ACTS
ACS
I
IN
Input leakage current
ACTS/ACS VIN = V
V
OL
Low-level output voltage
ACTS
ACS
V
OH
High-level output voltage
ACTS
ACS
I
OZ
Three-state output leakage current VO = VDD and V
1
0.8
.3V
DD
1
.5V
DD
.7V
DD
or V
DD
3
I
= 8.0mA
OL
I
= 100 A
OL
3
I
= -8.0mA
OH
I
= -100 A
OH
SS
SS
-1
.7V
DD
VDD - 0.25
-20 20 A
1 A
0.40
0.25
V
V
V
V
I
OS Short-circuit output current
ACTS/ACS
I
OL
Output current
10
(Sink)
I
OH
Output current
10
(Source)
P
total
I
DDQ
I
DDQ
Power dissipation
Quiescent Supply Current VDD = 5.5V 10 A
Quiescent Supply Current Delta
2, 8, 9
ACTS
C
IN Input capacitance
C
OUT
Output capacitance 5
5
2 ,4
VO = VDD and V
VIN = VDD or V
SS
SS
-200 200 mA
8 mA
VOL = 0.4V
VIN = VDD or V
SS
-8 mA
VOH = VDD - 0.4V
CL = 50pF 1.9 mW/
MHz
For input under test
1.6 mA
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or V
V
= 5.5V
DD
SS
= 1MHz @ 0V 15 pF
= 1MHz @ 0V 15 pF
RadHard MSI Logic 226
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UT54ACS374/UT54ACTS374
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
227 RadHard MSI Logic
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UT54ACS374/UT54ACTS374
AC ELECTRICAL CHARACTERISTICS
2
(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
f
MAX
t
SU
t
t
H
W
CLK to Qn 1 15 ns
CLK to Qn 1 18 ns
OC low to Qn active 1 13 ns
OC low to Qn active 1 13 ns
OC high to Qn three-state 1 11 ns
OC high to Qn three-state 1 12 ns
Maximum clock frequency 71 MHz
Data setup time before CLK 5 ns
Data hold time after CLK 2 ns
Minimum pulse width
7 ns
CLK high, CLK low
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
RadHard MSI Logic 228
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