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205 RadHard MSI Logic
UT54ACS283/UT54ACTS283
Radiation-Hardened
4-Bit Binary Full Adders
FEATURES
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS283 and the UT54ACTS283 are 4-bit binary
adders. The adders perform addition of two 4-bit binary words.
The sum ( ) outputs are provided for each bit and the resultant
carry (C4) is obtained as the fifth bit. The adders feature full
internal look-ahead across all four bits for fast carry generation.
The devices are characterized over full military temperature
range of -55 C to +125 C.
LOGIC SYMBOL
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpack
Top View
0
(1)
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
(5)
A1
(3)
A2
(14)
A3
(12)
A4 3
(6)
B1 0
(2)
B2
(15)
B3
(11)
B4 3
(7)
C0 C1
(4)
1
P
Q
2
(10)
(13)
3
4
0
3
(9)
C4
C0
1
2
3
4
5
7
6
16
15
14
13
12
10
11
B2
A2
1
A1
B1
C0
V
DD
B3
A3
3
A4
B4
4
8 9
V
SS
C4
2
1
2
3
4
5
7
6
16
15
14
13
12
10
11
8 9
B2
A2
1
A1
B1
C0
V
SS
2
V
DD
B3
A3
3
A4
B4
4
C4
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RadHard MSI Logic 206
UT54ACS283/UT54ACTS283
FUNCTION TABLE
H = high level, L = low level
Note:
Input conditions at A1, A2, B1, B2, and C0 are used to determine outputs 1 and 2 and the value of the internal carry C2. The values at C2, A3, B3, A4, and
B4 are then used to determine outputs 3, 4, and C4.
INPUT OUTPUT
When C0 = L When C2 = L When C0 = H When C2 = H
A1 A3 B1 B3 A2 A4 B2 B4 1 3 2 4 C2 C4 1 3 2 4 C2 C4
L L L L L L L H L L
H L L L H L L L H L
L H L L H L L L H L
H H L L L H L H H L
L L H L L H L H H L
H L H L H H L L L H
L H H L H H L L L H
H H H L L L H H L H
L L L H L H L H H L
H L L H H H L L L H
L H L H H H L L L H
H H L H L L H H L H
L L H H L L H H L H
H L H H H L H L H H
L H H H H L H L H H
H H H H L H H H H H
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207 RadHard MSI Logic
UT54ACS283/UT54ACTS283
LOGIC DIAGRAM
C4
(9)
(10)
(13)
(1)
(4)
(12)
(11)
(15)
(14)
(2)
(3)
(6)
(5)
(7)
B4
A4
B3
A3
B2
A2
B1
A1
C0
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RadHard MSI Logic 208
UT54ACS283/UT54ACTS283
RADIATION HARDNESS SPECIFICATIONS
1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold
2
80
MeV-cm2/mg
SEL Threshold 120
MeV-cm2/mg
Neutron Fluence 1.0E14
n/cm
2
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage -0.3 to 7.0 V
V
I/O
Voltage any pin -.3 to VDD +.3 V
T
STG
Storage Temperature range -65 to +150 C
T
J
Maximum junction temperature +175 C
T
LS
Lead temperature (soldering 5 seconds) +300 C
JC
Thermal resistance junction to case 20 C/W
I
I
DC input current 10 mA
P
D
Maximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage 4.5 to 5.5 V
V
IN
Input voltage any pin 0 to V
DD
V
T
C
Temperature range -55 to + 125 C
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209 RadHard MSI Logic
UT54ACS283/UT54ACTS283
DC ELECTRICAL CHARACTERISTICS
7
(VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
IL
Low-level input voltage
1
ACTS
ACS
0.8
.3V
DD
V
V
IH
High-level input voltage
1
ACTS
ACS
.5V
DD
.7V
DD
V
I
IN
Input leakage current
ACTS/ACS VIN = V
DD
or V
SS
-1
1 A
V
OL
Low-level output voltage
3
ACTS
ACS
I
OL
= 8.0mA
I
OL
= 100 A
0.40
0.25
V
V
OH
High-level output voltage
3
ACTS
ACS
I
OH
= -8.0mA
I
OH
= -100 A
.7V
DD
VDD - 0.25
V
I
OS
Short-circuit output current
2 ,4
ACTS/ACS
VO = VDD and V
SS
-200 200 mA
I
OL Output current
10
(Sink)
VIN = VDD or V
SS
VOL = 0.4V
8 mA
I
OH
Output current
10
(Source)
VIN = VDD or V
SS
VOH = VDD - 0.4V
-8 mA
P
total
Power dissipation
2, 8, 9
CL = 50pF 1.9 mW/
MHz
I
DDQ
Quiescent Supply Current VDD = 5.5V 10 A
I
DDQ
Quiescent Supply Current Delta
ACTS
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or V
SS
V
DD
= 5.5V
1.6 mA
C
IN
Input capacitance
5
= 1MHz @ 0V 15 pF
C
OUT
Output capacitance 5
= 1MHz @ 0V 15 pF
Page 6
RadHard MSI Logic 210
UT54ACS283/UT54ACTS283
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
AC ELECTRICAL CHARACTERISTICS
2
(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
t
PLH
Propagation delay C0 to n 2 16 ns
t
PHL
Propagation delay C0 to n 2 19 ns
t
PLH
Propagation delay C0 to C4 2 16 ns
t
PHL
Propagation delay C0 to C4 2 17 ns
t
PLH
Propagation delay An, Bn to C4 2 16 ns
t
PHL
Propagation delay An, Bn to C4 2 15 ns
t
PLH
Propagation delay An, Bn to n 2 14 ns
t
PHL
Propagation delay An, Bn to n 2 16 ns
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