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153 RadHard MSI Logic
UT54ACS240/UT54ACTS240
Radiation-Hardened
Octal Buffers & Line Drivers, Inverted Three-State Outputs
FEATURES
Three-state outputs drive bus lines or buffer memory address
registers
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
DESCRIPTION
The UT54ACS240 and the UT54ACTS240 are inverting octal
buffer and line drivers which improve the performance and denÂsity of three-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
LOGIC SYMBOL
PINOUTS
20-Pin DIP
Top View
20-Lead Flatpack
Top View
INPUTS OUTPUT
1G, 2G A Y
L L H
L H L
H X Z
(1)
1G EN
(2)
1A1
(4)
1A2
(6)
1A3
(8)
1A4
(18)
1Y1
(12)
1Y4
(14)
(16)
1Y2
(19)
2G EN
(11)
2A1
(13)
2A2
(15)
2A3
(17)
2A4
(9)
2Y1
(3)
2Y4
(5)
2Y3
(7)
2Y2
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
1Y3
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
V
DD
2G
1Y1
2A4
1Y2
1Y3
1A4
2A2
2A3
2Y1
1Y4
V
SS
2A1
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
1G
1A1
2Y4
1A2
2Y3
1A3
2Y2
V
DD
2G
1Y1
2A4
1Y2
1Y3
1A4 2A2
2A3
2Y1 1Y4
V
SS
2A1
1 20
2 19
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
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RadHard MSI Logic 154
UT54ACS240/UT54ACTS240
LOGIC DIAGRAM
RADIATION HARDNESS SPECIFICATIONS
1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold
2
80
MeV-cm2/mg
SEL Threshold 120
MeV-cm2/mg
Neutron Fluence 1.0E14
n/cm
2
1A1
1A2
1A3
1A4
1G
(2)
(4)
(6)
(8)
(1)
(16)
(14)
(12)
(18)
1Y1
1Y2
1Y3
1Y4
2A1
2A2
2A3
2A4
2G
(11)
(13)
(15)
(17)
(19)
(7)
(5)
(3)
(9)
2Y1
2Y2
2Y3
2Y4
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage -0.3 to 7.0 V
V
I/O
Voltage any pin -.3 to VDD +.3 V
T
STG
Storage Temperature range -65 to +150 C
T
J
Maximum junction temperature +175 C
T
LS
Lead temperature (soldering 5 seconds) +300 C
JC
Thermal resistance junction to case 20 C/W
I
I
DC input current 10 mA
P
D
Maximum power dissipation 1 W
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155 RadHard MSI Logic
UT54ACS240/UT54ACTS240
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage 4.5 to 5.5 V
V
IN
Input voltage any pin 0 to V
DD
V
T
C
Temperature range -55 to + 125 C
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RadHard MSI Logic 156
UT54ACS240/UT54ACTS240
DC ELECTRICAL CHARACTERISTICS
7
(VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
IL Low-level input voltage
1
ACTS
ACS
0.8
.3V
DD
V
V
IH
High-level input voltage
1
ACTS
ACS
.5V
DD
.7V
DD
V
I
IN
Input leakage current
ACTS/ACS VIN = V
DD
or V
SS
-1
1 A
V
OL
Low-level output voltage
3
ACTS
ACS
I
OL
= 12.0mA
I
OL
= 100 A
0.40
0.25
V
V
OH High-level output voltage
3
ACTS
ACS
I
OH
= -12.0mA
I
OH
= -100 A
.7V
DD
VDD - 0.25
V
I
OZ
Three-state output leakage current VO = VDD and V
SS
-30 30 A
I
OS
Short-circuit output current
2 ,4
ACTS/ACS
VO = VDD and V
SS
-300 300 mA
I
OL Output current
10
(Sink)
VIN = VDD or V
SS
VOL = 0.4V
12 mA
I
OH
Output current
10
(Source)
VIN = VDD or V
SS
VOH = VDD - 0.4V
-12 mA
P
total
Power dissipation
2, 8, 9
CL = 50pF 2.1 mW/
MHz
I
DDQ
Quiescent Supply Current VDD = 5.5V 10 A
I
DDQ
Quiescent Supply Current Delta
ACTS
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or V
SS
V
DD
= 5.5V
1.6 mA
C
IN Input capacitance
5
= 1MHz @ 0V 15 pF
C
OUT
Output capacitance 5
= 1MHz @ 0V 15 pF
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157 RadHard MSI Logic
UT54ACS240/UT54ACTS240
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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RadHard MSI Logic 158
UT54ACS240/UT54ACTS240
AC ELECTRICAL CHARACTERISTICS
2
(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
t
PLH
Input to Yn 1 10 ns
t
PHL
Input to Yn 1 13 ns
t
PZL
G low to Yn active 1 11 ns
t
PZH
G low to Yn active 2 13 ns
t
PLZ
G high to Yn three-state 2 11 ns
t
PHZ
G high to Yn three-state 2 14 ns
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