Page 1
125 RadHard MSI Logic
UT54ACS190/UT54ACTS190
Radiation-Hardened
Synchronous 4-Bit Up-Down BCD Counters
FEATURES
Single down/up count control line
Look-ahead circuitry enhances speed of cascaded counters
Fully synchronous in count modes
Asynchronously presettable with load control
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS190 and the UT54ACTS190 are synchronous 4bit reversible up-down BCD decade counters. Synchronous
counting operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each
other when so instructed. Synchronous operation eliminates the
output counting spikes associated with asynchronous counters.
The outputs of the four flip-flops are triggered on a low-to-highlevel transition of the clock input if the enable input (CTEN) is
low. A logic one applied to CTEN inhibits counting. The direction of the count is determined by the level of the down/up
(D/U) input. When D/U is low, the counter counts up and when
D/U is high, it counts down.
The counters feature a fully independent clock circuit. Changes
at control inputs (CTEN and D/U) that will modify the operating
mode have no effect on the contents of the counter until clocking
occurs.
The counters are fully programmable. The outputs may be preset to either logic level by placing a low on the load input and
entering the desired data at the data inputs. The output will
change to agree with the data inputs independently of the level
of the clock input. The asynchronous load allows counters to
be used as modulo-N dividers by simply modifying the count
length with the preset inputs.
If preset to an illegal state, the counter returns to a normal sequence in one or two counts.
PINOUTS
16-Pin DIP
Top View
16-Lead Flatpack
Top View
Two outputs have been made available to perform the cascading
function: ripple clock and maximum/minimum (MAX/MIN)
count. The MAX/MIN output produces a high-level output
pulse with a duration approximately equal to one complete cycle
of the clock while the count is zero (all outputs low) counting
down or maximum (9) counting up.
The ripple clock output (RCO) produces a low-level output
pulse under those same conditions but only while the clock input
is low. The counters easily cascade by feeding the RCO to the
enable input of the succeeding counter if parallel clocking is
used, or to the clock input if parallel enabling is used. Use the
MAX/MIN count output to accomplish look-ahead for highspeed operation.
The devices are characterized over full military temperature
range of -55 C to +125 C.
1
2
3
4
5
7
6
16
15
14
13
12
10
11
B
Q
B
Q
A
CTEN
D/U
Q
C
Q
D
V
DD
A
CLK
RCO
MAX/MIN
C
8 9V
SS
D
LOAD
1
2
3
4
5
7
6
16
15
14
13
12
10
11
V
DD
8 9
B
Q
B
Q
A
CTEN
D/U
Q
C
Q
D
A
CLK
RCO
MAX/MIN
LOAD
C
V
SS
D
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RadHard MSI Logic 126
UT54ACS190/UT54ACTS190
FUNCTION TABLE LOGIC SYMBOL
LOGIC DIAGRAM
Function LOAD CTEN D/U CLK
Count up H L L
Count down H L H
Asynchronous L X X
No change H X
(4)
CTEN
D/U
G
CTRDIV 10
CLK
(15)
(1)
B
C
(9)
(12)
MAX/MIN
Q
A
Q
D
(6)
Q
(2)
Q
5D
(1)
(4)
(8)
M2 (DOWN)
G4
(11)
LOAD
(13)
RCO
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
7
(14)
(5)
(15)
(4)
(1)
(10)
(13)
(12)
(3)
(2)
(6)
(7)
RCO
Q
A
Q
B
Q
C
Q
D
(9)
(11)
LOAD
CTEN
CLK
D/U
MAX/MIN
A
B
C
D
R
S
J Q
C
K
Q
R
J Q
C
K
Q
S
R
S
J Q
C
K
Q
R
S
J Q
C
K
Q
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127 RadHard MSI Logic
UT54ACS190/UT54ACTS190
RADIATION HARDNESS SPECIFICATIONS
1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold
2
80
MeV-cm2/mg
SEL Threshold 120
MeV-cm2/mg
Neutron Fluence 1.0E14
n/cm
2
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage -0.3 to 7.0 V
V
I/O
Voltage any pin -.3 to VDD +.3 V
T
STG
Storage Temperature range -65 to +150 C
T
J
Maximum junction temperature +175 C
T
LS
Lead temperature (soldering 5 seconds) +300 C
JC
Thermal resistance junction to case 20 C/W
I
I
DC input current 10 mA
P
D
Maximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage 4.5 to 5.5 V
V
IN
Input voltage any pin 0 to V
DD
V
T
C
Temperature range -55 to + 125 C
Page 4
RadHard MSI Logic 128
UT54ACS190/UT54ACTS190
DC ELECTRICAL CHARACTERISTICS
7
(VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
IL
Low-level input voltage
1
ACTS
ACS
0.8
.3V
DD
V
V
IH
High-level input voltage
1
ACTS
ACS
.5V
DD
.7V
DD
V
I
IN
Input leakage current
ACTS/ACS VIN = V
DD
or V
SS
-1
1 A
V
OL
Low-level output voltage
3
ACTS
ACS
I
OL
= 8.0mA
I
OL
= 100 A
0.40
0.25
V
V
OH
High-level output voltage
3
ACTS
ACS
I
OH
= -8.0mA
I
OH
= -100 A
.7V
DD
VDD - 0.25
V
I
OS
Short-circuit output current
2 ,4
ACTS/ACS
VO = VDD and V
SS
-200 200 mA
I
OL Output current
10
(Sink)
VIN = VDD or V
SS
VOL = 0.4V
8 mA
I
OH
Output current
10
(Source)
VIN = VDD or V
SS
VOH = VDD - 0.4V
-8 mA
P
total
Power dissipation
2, 8, 9
CL = 50pF 2.2 mW/MHz
I
DDQ
Quiescent Supply Current VDD = 5.5V 10 A
I
DDQ
Quiescent Supply Current Delta
ACTS
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or V
SS
V
DD
= 5.5V
1.6 mA
C
IN Input capacitance
5
= 1MHz @ 0V 15 pF
C
OUT Output capacitance
5
= 1MHz @ 0V 15 pF
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129 RadHard MSI Logic
UT54ACS190/UT54ACTS190
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
Page 6
RadHard MSI Logic 130
UT54ACS190/UT54ACTS190
AC ELECTRICAL CHARACTERISTICS
2
(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
3. Based on characterization, hold time (tH2) of 0ns can be assumed if data setup time (t
SU3
) is >10ns. This is guaranteed, but not tested.
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
t
PLH
LOAD to Q
n
2 19 ns
t
PHL
LOAD to Q
n
2 22 ns
t
PLH
Data In to Q
n
2 19 ns
t
PHL
Data In to Q
n
2 21 ns
t
PLH
CLK to Q
n
2 18 ns
t
PHL
CLK to Q
n
2 20 ns
t
PLH
CLK to RCO 2 16 ns
t
PHL
CLK to RCO 2 16 ns
t
PLH
CLK to MAX/MIN 2 18 ns
t
PHL
CLK to MAX/MIN 2 23 ns
t
PLH
D/U to RCO 2 16 ns
t
PHL
D/U to RCO 2 18 ns
t
PLH
D/U to MAX/MIN 1 14 ns
t
PHL
D/U to MAX/MIN 2 18 ns
t
PLH
CTEN to RCO 2 12 ns
t
PHL
CTEN to RCO 2 16 ns
f
MAX
Maximum clock frequency 71 MHz
t
SU1
CTEN, D/U
Setup time before CLK
13 ns
t
SU2
LOAD
Setup time before CLK
2 ns
t
SU3
A, B, C, D setup time before LOAD 7 ns
t
H1
CTEN and D/U hold time after CLK 2 ns
t
H2
3
A, B, C, D hold time after LOAD 2 ns
t
W
Minimum pulse width
CLK high
CLK low
LOAD low
7 ns
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