Page 1
107 RadHard MSI Logic
UT54ACS164/UT54ACTS164
Radiation-Hardened
8-Bit Shift Registers
FEATURES
AND-gated (enable/disable) serial inputs
Fully buffered clock and serial inputs
Direct clear
radiation-hardened CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
DESCRIPTION
The UT54ACS164 and the UT54ACTS164 are 8-bit shift registers which feature AND-gated serial inputs and an asynchronous clear. The gated serial inputs (A and B) permit complete
control over incoming data. A low at either input inhibits entry
of new data and resets the first flip-flop to the low level at the
next clock pulse. A high-level at both serial inputs sets the first
flip-flop to the high level at the next clock pulse. Data at the
serial inputs may be changed while the clock is high or low,
providing the minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition of the clock
input.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
Notes:
1. QA0, QB0, QH0 = the level of QA, QB or QH, respectively, before the indicated
steady-state input conditions were established.
2. QAn and QGn = the level of QA or QG before the most recent transition of
the clock; indicates a one-bit shift.
PINOUTS
14-Pin DIP
Top View
14-Lead Flatpack
Top View
LOGIC SYMBOL
INPUTS OUTPUTS
CLR CLK A B Q
A
Q
B ... QH
L X X X L L L
H L X X Q
A0
Q
B0
Q
H0
H H H H Q
An
Q
Gn
H L X L Q
An
Q
Gn
H X L L Q
An
Q
Gn
1
2
3
4
5
7
6
14
13
12
11
10
8
9
A
B
Q
A
Q
B
Q
C
Q
D
V
SS
V
DD
Q
H
Q
G
Q
F
Q
E
CLR
CLK
1
2
3
4
5
7
6
14
13
12
11
10
8
9
V
DD
Q
H
Q
G
Q
F
Q
E
CLR
CLK
A
B
Q
A
Q
B
Q
C
Q
D
V
SS
(9)
CLR
(8)
CLK
R
1D
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
(1)
A
(2)
B
(3)
Q
A
SRG8
&
(4)
Q
B
(5)
Q
C
(6)
Q
D
(10)
Q
E
(11)
Q
F
(12)
Q
G
(13)
Q
H
C1/
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RadHard MSI Logic 108
UT54ACS164/UT54ACTS164
LOGIC DIAGRAM
RADIATION HARDNESS SPECIFICATIONS
1
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold
2
80
MeV-cm2/mg
SEL Threshold 120
MeV-cm2/mg
Neutron Fluence 1.0E14
n/cm
2
Q
A
(8)
CLK
K K
R
S
K
R
S
K
R
S
K
R
S
K
R
S
K
R
S
K
R
S
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
CLR
(9)
(2)
(1)
A
B
SERIAL
R
S
C
C
C C C
C
C
C
(3)
(4) (5) (6) (10) (11) (12) (13)
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage -0.3 to 7.0 V
V
I/O
Voltage any pin -.3 to VDD +.3 V
T
STG
Storage Temperature range -65 to +150 C
T
J
Maximum junction temperature +175 C
T
LS
Lead temperature (soldering 5 seconds) +300 C
JC
Thermal resistance junction to case 20 C/W
I
I
DC input current 10 mA
P
D
Maximum power dissipation 1 W
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109 RadHard MSI Logic
UT54ACS164/UT54ACTS164
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMIT UNITS
V
DD
Supply voltage 4.5 to 5.5 V
V
IN
Input voltage any pin 0 to V
DD
V
T
C
Temperature range -55 to + 125 C
Page 4
RadHard MSI Logic 110
UT54ACS164/UT54ACTS164
DC ELECTRICAL CHARACTERISTICS
7
(VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
IL
Low-level input voltage
1
ACTS
ACS
0.8
.3V
DD
V
V
IH
High-level input voltage
1
ACTS
ACS
.5V
DD
.7V
DD
V
I
IN
Input leakage current
ACTS/ACS VIN = V
DD
or V
SS
-1
1 A
V
OL
Low-level output voltage
3
ACTS
ACS
I
OL
= 8.0mA
I
OL
= 100 A
0.40
0.25
V
V
OH
High-level output voltage
3
ACTS
ACS
I
OH
= -8.0mA
I
OH
= -100 A
.7V
DD
VDD - 0.25
V
I
OS
Short-circuit output current
2 ,4
ACTS/ACS
VO = VDD and V
SS
-200 200 mA
I
OL Output current
10
(Sink)
VIN = VDD or V
SS
VOL = 0.4V
8 mA
I
OH
Output current
10
(Source)
VIN = VDD or V
SS
VOH = VDD - 0.4V
-8 mA
P
total
Power dissipation
2, 8, 9
CL = 50pF 1.9 mW/
MHz
I
DDQ
Quiescent Supply Current VDD = 5.5V 10 A
I
DDQ
Quiescent Supply Current Delta
ACTS
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or V
SS
V
DD
= 5.5V
1.6 mA
C
IN
Input capacitance
5
= 1MHz @ 0V 15 pF
C
OUT
Output capacitance 5
= 1MHz @ 0V 15 pF
Page 5
111 RadHard MSI Logic
UT54ACS164/UT54ACTS164
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
Page 6
RadHard MSI Logic 112
UT54ACS164/UT54ACTS164
AC ELECTRICAL CHARACTERISTICS
2
(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (t
SU2
) is >10ns. This is guaranteed, but not tested.
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
t
PHL
CLK to Qn 4 21 ns
t
PLH
CLK to Qn 2 18 ns
t
PHL
CLR to Qn 5 21 ns
f
MAX
Maximum clock frequency 83 MHz
t
SU1
CLR inactive
Setup time before CLK
4 ns
t
SU2
Data setup time before CLK 4 ns
t
H
3
Data hold time after CLK 2 ns
t
W
Minimum pulse width
CLR low
CLK high
CLK low
6 ns
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