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UT54ACS109/UT54ACTS109
Radiation-Hardened
Dual J-K Flip-Flops
FEATURES
• radiation-hardened CMOS
- Latchup immune
• High speed
• Low power consumption
• Single 5 volt supply
• Available QML Q or V processes
• Flexible package
- 16-pin DIP
- 16-lead flatpack
DESCRIPTION
The UT54ACS109 and the UT54ACTS109 are dual J-K positive triggered flip-flops. A low level at the preset or clear inputs
sets or resets the outputs regardless of the other input levels.
When preset and clear are inactive (high), data at the J and K
input meeting the setup time requirements are transferred to the
outputs on the positive-going edge of the clock pulse. Following
the hold time interval, data at the J and K input can be changed
without affecting the levels at the outputs. The flip-flops can
perform as toggle flip-flops by grounding K and tying J high.
They also can perform as D flip-flops if J and K are tied together.
The devices are characterized over full military temperature
range of -55 C to +125 C.
FUNCTION TABLE
PINOUTS
CLR1
J1
K1
CLK1
PRE1
Q1
Q1
V
SS
16-Pin DIP
Top View
SS
1
2
J
3
4
5
6
7
8 9
CLR1
K1
CLK1
PRE1
Q1
Q1
V
16-Lead Flatpack
Top View
1
2
3
4
5
6
7
8 9
16
15
14
13
12
11
10
16
15
14
13
12
11
10
V
DD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
V
DD
CLR2
J2
K2
CLK2
PRE2
Q2
Q2
INPUTS OUTPUT
PRE CLR CLK J K Q Q
L H X X X H L
H L X X X L H
L L X X X
H H L L L H
H H H L Toggle
H H L H No Change
H H H H H L
H H L X X No Change
Note:
1. The output levels in this configuration are not guaranteed to meet the minimum levels for VOH if the lows at preset and clear are near V
addition, this configuration is nonstable; that is, it will not persist when either
preset or clear returns to its inactive (high) level.
1
H
maximum. In
IL
H
LOGIC SYMBOL
1
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
PRE1
J1
CLK1
K1
CLR1
PRE2
J2
CLK2
K2
CLR2
(5)
(2)
(4)
(3)
(1)
(11)
(14)
(12)
(13)
(15)
S
J1
K1
R
C1
(6)
(7)
(10)
(9)
Q1
Q1
Q2
Q2
61 RadHard MSI Logic
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LOGIC DIAGRAM
UT54ACS109/UT54ACTS109
PRE
CLK
J
K
CLR
RADIATION HARDNESS SPECIFICATIONS
1
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Threshold
2
80
SEL Threshold 120
Neutron Fluence 1.0E14
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Q
Q
MeV-cm2/mg
MeV-cm2/mg
n/cm
2
SYMBOL PARAMETER LIMIT UNITS
V
DD
V
I/O
T
STG
T
J
T
LS
JC
I
I
P
D
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Maximum junction temperature +175 C
Lead temperature (soldering 5 seconds) +300 C
Thermal resistance junction to case 20 C/W
Supply voltage -0.3 to 7.0 V
Voltage any pin -.3 to VDD +.3 V
Storage Temperature range -65 to +150 C
DC input current 10 mA
Maximum power dissipation 1 W
RadHard MSI Logic 62
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UT54ACS109/UT54ACTS109
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMIT UNITS
V
DD
V
IN
T
C
Supply voltage 4.5 to 5.5 V
Input voltage any pin 0 to V
DD
Temperature range -55 to + 125 C
V
63 RadHard MSI Logic
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UT54ACS109/UT54ACTS109
DC ELECTRICAL CHARACTERISTICS
7
(VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
V
IL
Low-level input voltage
ACTS
ACS
V
IH
High-level input voltage
ACTS
ACS
I
IN
Input leakage current
ACTS/ACS VIN = V
V
OL
Low-level output voltage
ACTS
ACS
V
OH
High-level output voltage
ACTS
ACS
I
OS
Short-circuit output current
ACTS/ACS
1
0.8
.3V
DD
1
.5V
DD
.7V
DD
or V
DD
3
I
= 8.0mA
OL
I
= 100 A
OL
3
I
= -8.0mA
OH
I
= -100 A
OH
2 ,4
VO = VDD and V
SS
SS
-1
.7V
DD
VDD - 0.25
-200 200 mA
1 A
0.40
0.25
V
V
V
V
I
OL Output current
(Sink)
I
OH
Output current
(Source)
P
total
I
DDQ
I
DDQ
Power dissipation
Quiescent Supply Current VDD = 5.5V 10 A
Quiescent Supply Current Delta
ACTS
C
IN Input capacitance
C
OUT Output capacitance
10
VIN = VDD or V
SS
8 mA
VOL = 0.4V
10
VIN = VDD or V
SS
-8 mA
VOH = VDD - 0.4V
2, 8 ,9
CL = 50pF 2.0 mW/
MHz
For input under test
1.6 mA
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or V
V
= 5.5V
DD
5
5
= 1MHz @ 0V 15 pF
= 1MHz @ 0V 15 pF
SS
RadHard MSI Logic 64
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UT54ACS109/UT54ACTS109
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%,
- 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but
are guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed
3,765 pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
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UT54ACS109/UT54ACTS109
AC ELECTRICAL CHARACTERISTICS
(VDD = 5.0V 10%; VSS = 0V 1, -55 C < TC < +125 C)
2
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
t
PHL
t
PLH
t
PLH
t
PHL
t
PHL
t
PLH
f
MAX
t
SU1
CLK to Q, Q 5 27 ns
CLK to Q, Q 4 23 ns
PRE to Q 1 16 ns
PRE to Q 1 19 ns
CLR to Q 2 19 ns
CLR to Q 2 16 ns
Maximum clock frequency 62 MHz
PRE or CLR inactive
5 ns
Setup time before CLK
t
SU2
t
H
t
W
Data setup time before CLK 5 ns
3
Data hold time after CLK 3 ns
Minimum pulse width
8 ns
PRE or CLR low
CLK high
CLK low
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose 1E6 rads(Si).
3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (t
) is >10ns. This is guaranteed, but not tested.
SU2
RadHard MSI Logic 66
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