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US1881
CMOS Multi-Purpose Latch
Features and Benefits
• Chopper stabilized amplifier stage
• Optimized for BDC motor applications
• New miniature package / thin, high reliability package
• Operation down to 3.5V
• CMOS for optimum stability, quality and cost
Applications
• Solid state switch
• Brushless DC motor commutation
• Speed sensing
• Linear position sensing
• Angular position sensing
• Current sensing
Ordering Information
Part No. Temperature Suffix Package Temperature Range
US1881 E SO or UA -40oC to 85oC Commercial
US1881 L SO or UA -40oC to 150oC Automotive
*Contact factory or sales representative for legacy temperature options
Functional Diagram
SO Package
Pin 1 - V
DD
Pin 2 - Output
Pin 3 - GND
Output
V
DD
Voltage
Regulator
Chopper
GND
UA Package
Pin 1 - V
DD
Pin 2 - GND
Pin 3 - Output
Note: Static sensitive device; please observe ESD precautions. Reverse VDD protection is not included. For reverse voltage protection, a 100Ω resistor in series with VDD is recommended.
Description
The US1881 is the industry’s first Hall integrated
circuit in a SOT-23 package. The US1881 is a bipolar Hall effect sensor IC fabricated from mixed
signal CMOS technology. It incorporates advanced
chopper stabilization techniques to provide accurate and stable magnetic switch points. There are
many applications for this HED in addition to those
listed above. The design, specifications and performance have been optimized for commutation
applications in 5V and 12V brushless DC motors.
The output transistor will be latched on (BOP) in the
presence of a sufficiently strong South pole magnetic field facing the marked side of the package.
Similarly, the output will be latched off (BRP) in the
presence of a North field.
The SOT-23 device is reversed from the UA package. The SOT-23 output transistor will be latched
on in the presence of a sufficiently strong North
pole magnetic field applied to the marked face.
US1881 CMOS Multi-Purpose Latch 3901001881 Rev. 5.2 7/23/01 Page 1
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US1881
CMOS Multi-Purpose Latch
US1881 Electrical Specifications
DC Operating Parameters: TA = 25, VDD = 12VDC (unless otherwise specified).
Parameter Symbol Test Conditions Min Typ Max Units
Supply Voltage VDD Operating 3.5 24 V
Supply Current IDD B<BOP 1.5 2.5 4.0 mA
Saturation Voltage V
Output Leakage I
I
DS(on)
B<BRP, V
OFF
OUT
= 20 mA, B>BOP 0.4 0.5 V
= 20V 0.01 5.0 ì A
OUT
Output Rise Time tr VDD = 12V, RL = 1.1KÙ, CL = 20pf 0.04 ì s
Output Fall Time tf VDD = 12V, RL = 1.1KÙ, CL = 20pf 0.18 ì s
Parameter Symbol Test Conditions Min Typ Max Units
Operating Point BOP 1.0 5.0 9.0 mT
Release Point BRP -9.0 -5.0 -1.0 mT
Hysteresis B
Performance Graphs
Power Dissipation
versus
Temperature
5.5 10.0 12.0 mT
hys
Wave Soldering Parameters
500
400
300
200
All Devices
UA Package
R
=206oC/W
θJA
280
260
C)
o
240
220
All Devices
Solder Temperature (
100
Package Power Dissipation (mW)
0
SO Package
R
θ
JA
0-40 120 160 20040
=575oC/W
80
Temperature (oC)
US1881 CMOS Multi-Purpose Latch 3901001881 Rev. 5.2 7/23/01 Page 2
200
1050 20 25 30
Time in Wave Solder (Seconds)
15
Page 3
Performance Graphs
US1881
CMOS Multi-Purpose Latch
Typical Magnetic Switch Points
versus
Supply Voltage
12.5
7.5
B
OP
2.5
-2.5
Flux Density (mT)
B
-7.5
-12.5
RP
15
1050 20 25 30
Supply Voltage (V)
1881
Typical Magnetic Switch Points
versus
Temperature
12
B
HYS
7.5
B
2.5
-2.5
Flux Density (mT)
-7.5
-12.5
0-40 120 160 20040
Temperature (oC)
OP
B
RP
80
1881
Min/Max Magnetic Switch Range
versus
Temperature
12.5
B
Max
7.5
2.5
-2.5
Flux Density (mT)
-7.5
-12.5
0-40 120 160 20040
Temperature (oC)
OP
B
Min
OP
B
Max
RP
B
Min
RP
80
1881
Output Voltage
versus
Flux Density
30
24
18
12
Output Voltage (V)
6
0
V
DD
B
-10-20-30 10 20 30
Flux Density (mT)
1881
B
OP
RP
V
out
0
US1881 CMOS Multi-Purpose Latch 3901001881 Rev. 5.2 7/23/01 Page 3
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Performance Graphs
US1881
CMOS Multi-Purpose Latch
Typical Supply Current
versus
Supply Voltage
5
4
TA = -40oC
3
TA = 25oC
2
Supply Current (mA)
1
0
1050 20 25 30
Supply Voltage (V)
15
TA = 125oC
1881
Typical Saturation Voltage
versus
Temperature
VDD = 12 V, I
500
400
300
(mV)
DS(ON)
200
V
100
0
0-40 120 160 20040
Temperature (oC)
= 20mA
OUT
V
DS(ON)
80
1881
Unique Features
CMOS Hall IC Technology
The chopper stabilized amplifier uses switched
capacitor techniques to eliminate the amplifier
offset voltage, which, in bipolar devices, is a
major source of temperature-sensitive drift.
CMOS makes this advanced technique possible. The CMOS chip is also much smaller than
a bipolar chip, allowing very sophisticated circuitry to be placed in less space. The small chip
size also contributes to lower physical stress
and less power consumption.
Installation
Consider Temperature Coefficients of Hall IC
and magnetics, as well as air gap and life time
variations. Observe ESD control procedures.
Observe temperature limits during wave soldering.
Applications
If reverse supply protection is desired, use a resistor in series with the VDD pin that will limit the
Supply Current (Fault), IDD, to 50 mA. For se-
vere EMC conditions, use the application circuit
on the following page.
US1881 CMOS Multi-Purpose Latch 3901001881 Rev. 5.2 7/23/01 Page 4
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Applications Examples
US1881
CMOS Multi-Purpose Latch
Automotive and Severe
Environment Protection Circuit
R1 100 Ω
Supply
Voltage
D1
Z1
C1
4.7nF
Hall IC
Two Wire Optional Current
Biasing Circuit
R
Iout
V
DD
R
L
1.2K
OUT
C2
4.7nF
V
SS
V
DD
The resistors Rb and RL can be used to bias the input current, Iin.
Refer to the part specification for limiting values. This circuit will help in
getting the precise ON and OFF currents desired.
I
IN
DD
I
R
b
BRP = Ioff = (VDD / Rb + I
BOP = Ion = (Ioff + VDD / RL )
L
Hall IC
)
DD
Absolute Maximum Ratings
Supply Voltage (Operating), VDD 3.5V to 24V
Supply Current (Fault), IDD 50mA
Output Voltage, V
Output Current (Fault), I
Power Dissipation, PD 100mW
Operating Temperature Range, TA -40 to 150°C
Storage Temperature Range, TS -65°C to 150°C
Maximum Junction Temp, TJ 175°C
ESD Sensitivity (All Pins) +/- 4KV
US1881 CMOS Multi-Purpose Latch 3901001881 Rev. 5.2 7/23/01 Page 5
3.5V to 24V
OUT
50mA
OUT
Page 6
Physical Characteristics
UA Package Dimensions
o
1.60
1.40
0.84
0.63
4.30
3.90
2.64
2.34
U18
805
0.48
0.43
0.20
0.00
0.41
0.35
1 2 3
1.30
1.24
45
Typical
*
3.20
2.80
1.75
1.55
NOTES:
1.) Controlling dimension: mm
2.) Leads must be free of flash and
plating voids
3.) Do not bend leads within 1mm of
the lead to package interface.
4.) Package dimensions exclude
molding flash
5.) Tolerance is 0.254mm unless
otherwise specified
2.57
2.51
US1881
CMOS Multi-Purpose Latch
UA Hall Plate / Chip Location
2.13
o
5
Typical
o
45
Typical
0.38
Typical
(see note 3)
* MARKING:
Line 1:
1st digit (U) = Supplier (Melexis)
15.5
14.5
0.41
0.35
2nd and 3rd digits (18) = Series (1880)
Line 2:
1st digit (8) = Year (1998)
2nd and 3rd digits(05) = Week of Year
PINOUT:
Pin 1 V
Pin 2 GND
Pin 3 Output
1.87
1.53
1.27
Marked
Surface
All Dimensions in millimeters
DD
0.45
0.41
SOT-23 Package Dimensions
(Top View)
0.50
0.35
3
3.00
2.60
1651
Melexis Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Melexis does
not assume any liability arising from the use of any product or application of any product or circuit described herein.
1 2
2.10
1.70
3.10
2.70
*
1.80
1.50
Pin #
0.10
0.00
1.30
0.90
1.00
0.70
NOTES:
1. MARKING:
1st Digit (1) = Series (1880)
2nd Digit(6) = Year - 1996
0.20
MIN
Last Digits (51) = Week of Year
2. PINOUT (See Top View at left):
Pin 1 VDD
Pin 2 Output
Pin 3 GND
chip
0.66
3. Controlling dimension: mm.
0.56
4. Lead thickness after solder plating will be 0.254
0.25
0.10
5. Package dimensions exclude molding flash.
6. The end flash shall not exceed 0.127 mm on each
7. Tolerance is +/- 0.254 mm unless otherwise
mm maximum.
side of package.
specified.
SOT-23 Hall Plate /
Chip Location
(Bottom View)
1.55
1.45
0.95
0.85
For the latest version of this document,
Go to our website at:
WWW.melexis.com
Or for additional information
Contact Melexis Direct:
Europe and Japan USA and rest of the world
E-mail: [email protected] E-mail: [email protected]
Phone: 011-32-13-670-780 Phone: (603)-223-2362
US1881 CMOS Multi-Purpose Latch 3901001881 Rev. 5.2 7/23/01 Page 6
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