Page 1
US1050
5V
5A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
FEATURESFEATURES
Guaranteed < 1.3V Dropout at Full Load
Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Output Current Limiting
Built-in Thermal Shutdown
APPLICATIONSAPPLICATIONS
Low Voltage Processor Applications such as :
P54C,P55C,Cyrix M2,
POWER PC,AMD
GTL+ Termination
PENTIUM PRO, KLAMATH
Low Voltage Memory Termination Applications
Standard 3.3V Chip-Set and Logic Applications
TYPICAL APPLICATIONTYPICAL APPLICATION
DESCRIPTIONDESCRIPTION
The US1050 product is a low dropout three terminal adjustable regulator with minimum of 5A output current
capability. This product is specifically designed to provide well regulated supply for low voltage IC applications
such as Pentium P54C,P55C as well as GTL+
termination for Pentium Pro and Klamath pro-
cessor applications . The US1050 is also well suited for
other processors such as Cyrix,AMD and Power
PCapplications. The US 1050 is guaranteed to have
<1.3V drop out at full load current making it ideal to
provide well regulated outputs of 2.5V to 3.6V with 4.75V
to 7V input supply.
C1
1500uF
Vin
3
Vout
Adj
2
1
R1
121
R2
205
US1050
1050app1-1.1
Typical Application of US1050 in a 5V to 3.38V regulator designed
to meet the Intel P54C Processors.
Notes: Pentium P54C,P55C ,Klamath,Pentium Pro,VRE,are trade marks of Intel Corp.Cyrix M2 is trade mark of Cyrix Corp.
Power PC is trade mark of IBM Corp.
3.38V / 5A
C2
2x 1500uF
PACKAGE ORDER INFORMATIONPACKAGE ORDER INFORMATION
Tj (°C) 3 PIN PLASTIC 3 PIN PLASTIC 2 PIN PLASTIC 3 PIN PLASTIC
TO220 (T) TO263 (M) POWER FLEX (P) TO252 (D)
0 TO 150 US1050CT US1050CM US1050CP US1050CD
Rev. 1.3
10/27/00
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US1050
ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS
Input Voltage (Vin) .................................................................. 7V
Power Dissipation ............................................ Internally Limited
Storage Temperature Range .............................. -65°C TO 150°C
Operating Junction Temperature Range .................. 0°C TO 150°C
PACKAGE INFORMATIONPACKAGE INFORMATION
3 PIN PLASTIC TO220 ( T ) 3 PIN PLASTIC TO263 ( M ) 2 PIN PLASTIC POWER FLEX ( P ) 3 PIN PLASTIC TO252 ( D )
Tab is
Vout
FRONT VIEW
4
Tab is
Vout
FRONT VIEW
4
3
Vin
1
Adj
3
Vin
1
Adj
Tab is
Vout
FRONT VIEW
3
2
1
Vin
Vout
Adj
Tab is
Vout
FRONT VIEW
3
Vin
2
Vout
1
Adj
θJT=2.7°C/W θJA=60°C/W θJA=35°C/W for 1" Square pad θJA=70°C/W for 1" Square pad θJA=70°C/W for 0.5" Sq pad
ELECTRICAL SPECIFICATIONSELECTRICAL SPECIFICATIONS
Unless otherwise specified ,these specifications apply over ,Cin=1uF,Cout=10uF,and Tj=0 to 150°C.Typical
values refer to Tj=25°C.
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Reference Voltage VREF Io=10mA,Tj=25°C,(Vin-Vo)=1.5V 1.243 1.250 1.257 V
Io=10mA, (Vin-Vo)=1.5V 1.237 1.250 1.263
Line Regulation Io=10mA,1.3V<(Vin-Vo)<7V 0.2 %
Load Regulation (note 1) Vin=3.3V,Vadj=0,10mA<Io<5A 0.4 %
Dropout Voltage
(note 2) ∆VO Note 2 , Io=5A 1.1 1.3 V
Current Limit Vin=3.3V,dVo=100mV 5.1 A
Minimum Load Current Vin=3.3V,Vadj=0V 5 10 mA
(note 3)
Thermal Regulation 30 mS PULSE,Vin-Vo=3V,Io=5A 0.01 0.02 %/W
Ripple Rejection f=120HZ ,Co=25uF Tan
Io=2.5A,Vin-Vo=3V 60 70 dB
Adjust Pin Current IADJ Io=10mA,Vin-Vo=1.5V,Tj=25
Io=10mA,Vin-Vo=1.5V 55 120 uA
Adjust Pin Current Change Io=10mA,Vin-Vo=1.5V,Tj=25 0.2 5 uA
Temperature Stability Vin=3.3V,Vadj=0V,Io=10mA 0.5 %
Long Term Stability Tj=125°C,1000 Hrs 0.3 1 %
RMS Output Noise Tj=25°C 10hz<f<10khz 0.003 %Vo
Note 1 : Low duty cycle pulse testing with Kelvin connections are required in order to maintain accurate data.
Note 2 : Drop-out voltage is defined as the minimum
differential voltage between Vin and Vout required to maintain regulation at Vout. It is measured when the output
Note 3 : Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor
dividers are selected such that it automatically maintains this current.
voltage drops 1% below its nominal value.
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US1050
PIN DESCRIPTIONSPIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1 Adj A resistor divider from this pin to the Vout pin and ground sets the output voltage.
2 Vout The output of the regulator. A minimum of 10uF capacitor must be connected
from this pin to ground to insure stability.
3 Vin The input pin of the regulator. Typically a large storage capacitor is connected
from this pin to ground to insure that the input voltage does not sag below the
minimum drop out voltage during the load transient response. This pin must
always be 1.3V higher than Vout in order for the device to regulate properly.
BLOCK DIAGRAMBLOCK DIAGRAM
Vin 3
+
CURRENT
LIMIT
THERMAL
SHUTDOWN
Figure 1 - Simplified block diagram of the US1050
APPLICATION INFORMATIONAPPLICATION INFORMATION
Introduction
The US1050 adjustable Low Dropout (LDO) regulator is
a 3 terminal device which can easily be programmed
with the addition of two external resistors to any voltages within the range of 1.25 to 5.5 V.This regulator
unlike the first generation of the 3T regulators such as
LM117 that required 3V differential between the input
and the regulated output,only needs 1.3V differential to
maintain output regulation. This is a key requirement for
today’s microprocessors that need typically 3.3V supply and are often generated from the 5V supply. Another
major requirement of these microprocessors such as
the Intel P54C is the need to switch the load current
from zero to several amps in tens of nanoseconds at
2 Vout
1.25V
1050blk1-1.0
the processor pins ,which translates to an approximately
300 to 500 nS current step at the regulator . In addition,
the output voltage tolerances are also extremely tight
and they include the transient response as part of the
specification.For example Intel VRE specification calls
for a total of ±100mV including initial tolerance,load regu-
lation and 0 to 4.6A load step.
The US1050 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage , reducing the overall system cost with the
need for fewer output capacitors.
+
1 Adj
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US1050
PARASITIC LINE
Output Voltage Setting
The US1050 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
R
2
V V
OUT REF ADJ
Where : V Typically
I lly
ADJ
= uA Typica
R in figure
1 2
& R as shown
= +
REF
V = .
50
Vin
+ ×1
R
1
125
US1050
Adj
I R
VoutVin
IAdj = 50uA
2
2
Vout
R1
Vref
R2
1050app2-1.0
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the Vout pin of the
regulator and not to the load. In fact , if R1 is connected
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+R2/
R1) ,or the effective resistance will be ,Rp(eff)=Rp*(1+R2/
R1).It is important to note that for high current applications, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to minimize this effect.
RESISTANCE
Rp
Vin
VoutVin
US1050
Adj
R1
R2
R
L
Figure 2 - Typical application of the US1050
for programming the output voltage.
The US1050 keeps a constant 1.25V between the output pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, adding to the Iadj current and into the R2 resistor producing
a voltage equal to the (1.25/R1)*R2 + Iadj*R2 which will
be added to the 1.25V to set the output voltage. This is
summarized in the above equation. Since the minimum
load current requirement of the US1050 is 10 mA , R1 is
typically selected to be 121Ω resistor so that it automatically satisfies the minimum current requirement.
Notice that since Iadj is typically in the range of 50uA it
only adds a small error to the output voltage and should
only be considered when a very precise output voltage
setting is required. For example, in a typical 3.3V application where R1=121Ω and R2=200Ω the error due to
Iadj is only 0.3% of the nominal set point.
Load Regulation
Since the US1050 is only a 3 terminal device , it is not
possible to provide true remote sensing of the output
voltage at the load.Figure 3 shows that the best load
1050app3-1.0
Figure 3 - Schematic showing connection for best load
regulation
Stability
The US1050 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor applications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100 mΩ and an output
capacitance of 500 to 1000uF. Fortunately as the capacitance increases, the ESR decreases resulting in a
fixed RC time constant. The US1050 takes advantage of
this phenomena in making the overall regulator loop
stable.For most applications a minimum of 100uF aluminum electrolytic capacitor such as Sanyo MVGX series ,Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
2-36
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US1050
=
(
)
(
)
∆
TTC
=−=−=°1163581
6
9
Thermal Design
The US1050 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 150°C ,it is recommended that the
selected heat sink be chosen such that during maximum continuous load operation the junction temperature is kept below this number. The example below
shows the steps in selecting the proper Regulator heat
sink for the worst case current consumption using Intel
200MHz microprocessor as the load .
Assuming the following specifications :
V V
IN
5
V V
O
=
35
.
I A
OUT
MAX
=
46
.
T C
A
= °
35
The steps for selecting a proper heat sink to keep the
junction temperature below 135°C is given as :
1) Calculate the maximum power dissipation using :
∆T=Temperature Rise Above Ambient
T
∆
θ
SA
=
D
P
81
θ
SA
= = °
C W
117.. /
5) Next , a heat sink with lower θsa than the one calculated in step 4 must be selected. One way to do this is
to simply look at the graphs of the “Heat Sink Temp
Rise Above the Ambient” vs. the “Power Dissipation” and
select a heat sink that results in lower temperature rise
than the one calculated in previous step. The following
heat sinks from AAVID and Thermaloy meet this criteria.
Air Flow (LFM)
0 100 200 300 400
Thermalloy 6021PB 6021PB 6073PB 6109PB 7141D
AAVID 534202B 534202B 507302 575002 576802B
Note : For further information regarding the above companies and their latest product offerings and application
support contact your local representative or the numbers listed below:
P I V V
D O UT IN O UT
= × −
P . . . W
D
= × − =46 5 3 5 69
( )
2) Select a package from the Regulator data sheet
and record its junction to case (or Tab) thermal
resistance.
Selecting TO220 package gives us :
θJC C W= °27. /
3) Assuming that the heat sink is Black Anodized, calculate the maximum Heat sink temperature allowed :
Assume , θcs=0.05°C/W (Heat sink to Case thermal
resistance for Black Anodized)
T T P
S J D= − × +
= − × + = °
ST C135 6 9 27 0 05 116
θ θJC CS
. . .
( )
4) With the maximum heat sink temperature calculated in the previous step, the Heat Sink to Air thermal
resistance (θsa) is calculated by first calculating the
temperature rise above the ambient as follows :
T S A
AAVID PH# (603) 528 3400
Thermalloy PH# (214) 243-4321
Designing for Microprocessor Applications
As it was mentioned before the US1050 is designed specifically to provide power for the new generation of the
low voltage processors requiring voltages in the range
of 2.5V to 3.6V generated by stepping down the
5V supply. These processors demand a fast regulator
that supports their large load current changes. The worst
case current step seen by the regulator is anywhere in
the range of 1 to 7A with the slew rate of 300 to 500 nS
which could happen when the processor transitions from
“Stop Clock” mode to the “Full Active” mode. The load
current step at the processor is actually much faster ,in
the order of 15 to 20 nS,however the decoupling capacitors placed in the cavity of the processor socket handle
this transition until the regulator responds to the load
current levels. Because of this requirement the selection of high frequency low ESR and low ESL output capacitor is imperative in the design of these regulator circuits.
Figure 4 shows the effects of a fast transient on the
Rev. 1.3
10/27/00
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US1050
∆
∆
×=×
output voltage of the regulator. As shown in this figure,
the ESR of the output capacitor produces an instanta-
neous drop equal to the (∆VESR=ESR*∆I) and the ESL
effect will be equal to the rate of change of the output
current times the inductance of the capacitor. (∆VESL
=L*∆I/∆t) . The output capacitance effect is a droop in
the output voltage proportional to the time it takes for
the regulator to respond to the change in the current ,
(∆VC = ∆t * ∆I / C ) where ∆t is the response time of the
regulator.
V
ESR
V
ESL
LOAD
CURRENT
T
1050plt1-1.0
LOAD CURRENT RISE TIME
V
C
ESR ≤ =
37
468.
mΩ
The Sanyo MVGX series is a good choice to achieve
both price and performance goals.The 6MV1500GX ,
1500uF, 6.3V has an ESR of less than 36 mΩ typ .
Selecting 5 of these capacitors in parallel has an ESR
of ≈7.2 mΩ which achieves our design goal.
The next step is to calculate the drop due to the capacitance discharge and make sure that this drop in voltage
is less than the selected ESL drop in the previous step.
2) The output capacitance is 5X1500 uF = 7500uF
∆
t I
V
C =
C
2 4 6
7500
=
12.. mV
Where :
∆
t he regulator response time
=2 uS is t
To set the output DC voltage, we need to select R1 and
R2 :
Figure 4 - Typical Regulator response to the fast load
current step.
An example of a regulator design to meet the Intel
P54C VRE specification is given below .
Assume the specification for the processor as shown in
Table 1:
Type of Vout Imax Max Allowed
Processor Nominal Output Tolerance
Intel-P54C VRE 3.50 V 4.6 A ±100 mV
Table 1 - Processr Specification
The first step is to select the voltage step allowed in the
output due to the output capacitor’s ESR :
1) Assuming the regulator’s initial accuracy plus the resistor divider tolerance is ≈ ±53 mV (±1.5% of 3.5V nominal) ,then the total step allowed for the ESR and the
ESL, is −47 mV .
Assuming that the ESL drop is −10mV ,the remaining
ESR step will be −37 mV . Therefore the output capacitor ESR must be :
3) Assuming R1=121 Ω , 0.1%
V
OUT
R
2 1 121
V
REF
× = −
35
.
125
.
1 121 2178= −
× =
. Ω
Select R2=218 ΩΩ ,0.1%
Selecting both R1 and R2 resistors to be 0.1% toler-
ance, results in the least amount of error introduced by
the resistor dividers leaving ≈ ±1.3% error budget for
the US1050 reference which is within the initial accu-
racy of the device.
Finally , the input capacitor is selected as follows :
4) Assuming that the input voltage can drop 150mV before the main power supply responds, and that the main
power supply response time is ≈ 50 uSec, then the minimum input capacitance for a 4.6A load step is given by
×=46 50
.
CIN =
015
1530
.
Fµ
2-38
Rev. 1.3
10/27/00
Page 7
The ESR should be less than ;
(
)
(
)
ESR
− − −
=
∆
I
∆
V V V V
IN OUT DROP
Where :
V Input voltage drop
DROP
≡
allowed
V egulator
≡
∆
Maximum r
d
∆
ESR =
ropout voltage
I ent step
≡
Load curr
− − −
5 3 5 12 015
in step
. . .
46
.
4
=
0032
. Ω
Selecting two Sanyo 1500 uF the same type as the
output capacitors meets our requirements.
Figure 5 shows the completed schematic for our
example.
US1050
5V
1500uF
C1
US1050
Adj
VoutVin
R1
121
0.1%
R2
218
0.1%
3.50V
C2
5x 1500uF
1050app4-1.1
Figure 5 - Final Schematic for the
Intel VRE Application
Layout Consideration
The output capacitors must be located as close to
the Vout terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the Vout pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
Rev. 1.3
10/27/00
2-39
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