Page 1
FEATURESFEATURES
D1
Guaranteed < 1.3V Dropout at Full Load
Current
Fast Transient Response
1% Voltage Reference Initial Accuracy
Built-in Thermal Shutdown
Available in SOT-223, D-PAK , Power Flex
and 8 pin SOIC Surface Mount Packages
APPLICATIONSAPPLICATIONS
VGA & Sound Card Applications
Low Voltage High Speed Termination Applications
Standard 3.3V Chip-Set and Logic Applications
US1010
1A LOW DROPOUT POSITIVE
ADJUSTABLE REGULATOR
PRELIMINARY DATASHEET
DESCRIPTIONDESCRIPTION
The US1010 is a low dropout three terminal adjustable
regulator with minimum of 1A output current capability.
This product is specifically designed to provide well regulated supply for low voltage IC applications such as high
speed bus termination and low current 3.3V logic
supply. The US1010 is also well suited for other appli-
cations such as VGA and sound cards. The US 1010 is
guaranteed to have <1.3V drop out at full load current making it ideal to provide well regulated outputs of
2.5V to 3.6V with 4.75V to 7V input supply.
TYPICAL APPLICATIONTYPICAL APPLICATION
5V
C1
10uF
Vin
3
US1010
Vout
2
Adj
1
1010app1-1.4
Typical Application of US1010 in a 5V to 2.85V SCSI termination regulator .
PACKAGE ORDER INFORMATIONPACKAGE ORDER INFORMATION
R1
121
R2
154
2.85V / 1A
C2
22uF
Tj (°C) 2 PIN PLASTIC 3 PIN PLASTIC 2 PIN PLASTIC 8 PIN PLASTIC
TO252 (D) SOT223 (Y) POWER FLEX (P) SOIC (S)
0 TO 150 US1010CD US1010CY US1010CP US1010CS
Rev. 1.3
10/30/00
2-1
Page 2
US1010
ABSOLUTE MAXIMUM RATINGSABSOLUTE MAXIMUM RATINGS
Input Voltage (Vin) .................................................................. 7V
Power Dissipation ............................................ Internally Limited
Storage Temperature Range .............................. -65°C TO 150°C
Operating Junction Temperature Range .................. 0°C TO 150°C
PACKAGE INFORMATIONPACKAGE INFORMATION
2 PIN PLASTIC TO252 ( D ) 3 PIN PLASTIC SOT223 ( Y ) 2 PIN PLASTIC PFLEX ( P ) 8 PIN PLASTIC SOIC (S)
Tab is
Vout
FRONT VIEW
4
3
Vin
Tab is
1
Adj
Vout
TOP VIEW
3
Vin
2
Vout
1
Adj
θJA=70°C/W for 0.5" Sq pad θJA=90°C/W for 0.4" Sq pad θJA=70°C/W for 0.5" Sq pad θJA=55°C/W for 1" Sq pad
ELECTRICAL SPECIFICATIONSELECTRICAL SPECIFICATIONS
Unless otherwise specified, these specifications apply over, Cin=1uF, Cout=10uF, and Tj=0 to 150°C.Typical
values refer to Tj=25°C.
Tab is
Vout
FRONT VIEW
4
3
Vin
1
Adj
Vin
NC
NC
TOP VIEW
1
2
3
4
8
Vout
7
Vout
6
Vout
5
VoutAdj
PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS
Reference Voltage VREF Io=10mA,Tj=25°C,(Vin-Vo)=1.5V 1.243 1.250 1.257 V
Io=10mA, (Vin-Vo)=1.5V 1.237 1.250 1.263
Line Regulation Io=10mA,1.3V<(Vin-Vo)<7V 0.2 %
Load Regulation (note 1) Vin=3.3V,Vadj=0,10mA<Io<1A 0.4 %
Dropout Voltage
(note 2) ∆VO Note 2 , Io=1A 1.1 1.3 V
Current Limit Vin=3.3V,dVo=100mV 1.1 A
Minimum Load Current Vin=3.3V,Vadj=0V 5 10 mA
(note 3)
Thermal Regulation 30 mS PULSE,Vin-Vo=3V,Io=1A 0.01 0.02 %/W
Ripple Rejection f=120HZ ,Co=25uF Tan
Io=0.5A,Vin-Vo=3V 60 70 dB
Adjust Pin Current IADJ Io=10mA,Vin-Vo=1.5V,Tj=25
Io=10mA,Vin-Vo=1.5V 55 120 uA
Adjust Pin Current Change Io=10mA,Vin-Vo=1.5V,Tj=25 0.2 5 uA
Temperature Stability Vin=3.3V,Vadj=0V,Io=10mA 0.5 %
Long Term Stability Tj=125°C,1000 Hrs 0.3 1 %
RMS Output Noise Tj=25°C 10hz<f<10khz 0.003 %Vo
Note 1 : Low duty cycle pulse testing with Kelvin connections are required in order to maintain accurate data.
Note 2 : Drop-out voltage is defined as the minimum
differential voltage between Vin and Vout required to maintain regulation at Vout. It is measured when the output
Note 3 : Minimum load current is defined as the minimum current required at the output in order for the output voltage to maintain regulation. Typically the resistor
dividers are selected such that it automatically maintains this current.
voltage drops 1% below its nominal value.
2-2
Rev. 1.3
10/30/00
Page 3
US1010
PIN DESCRIPTIONSPIN DESCRIPTIONS
PIN # PIN SYMBOL PIN DESCRIPTION
1 Adj A resistor divider from this pin to the Vout pin and ground sets the output voltage.
2 Vout The output of the regulator. A minimum of 10uF capacitor must be connected
from this pin to ground to insure stability.
3 Vin The input pin of the regulator. Typically a large storage capacitor is connected
from this pin to ground to insure that the input voltage does not sag below the
minimum drop out voltage during the load transient response. This pin must
always be 1.3V higher than Vout in order for the device to regulate properly.
BLOCK DIAGRAMBLOCK DIAGRAM
Vin 3
+
CURRENT
LIMIT
THERMAL
SHUTDOWN
Figure 1 - Simplified block diagram of the US1010
APPLICATION INFORMATIONAPPLICATION INFORMATION
Introduction
The US1010 adjustable Low Dropout (LDO) regulator is
a 3 terminal device which can easily be programmed
with the addition of two external resistors to any voltages within the range of 1.25 to 5.5 V.This regulator
unlike the first generation of the 3T regulators such as
LM117 that required 3V differential between the input
and the regulated output,only needs 1.3V differential to
maintain output regulation. This is a key requirement for
today’slow voltage IC applications that typically need
3.3V supply and are often generated from the 5V supply. Other applications such as high speed memory termination need to switch the load current from zero to full
load in tens of nanoseconds at the their pins ,which
2 Vout
1.25V
1010blk1-1.0
translates to an approximately 300 to 500 nS current
step at the regulator . In addition, the output voltage tolerances are sometimes tight and they include the transient response as part of the specification.
The US1010 is specifically designed to meet the fast
current transient needs as well as providing an accurate
initial voltage , reducing the overall system cost with the
need for fewer output capacitors.
+
1 Adj
Rev. 1.3
10/30/00
2-3
Page 4
US1010
PARASITIC LINE
Output Voltage Setting
The US1010 can be programmed to any voltages in the
range of 1.25V to 5.5V with the addition of R1 and R2
external resistors according to the following formula:
R
2
V V
OUT REF ADJ
Where : V Typically
I lly
ADJ
= uA Typica
R in figure
1 2
& R as shown
= +
REF
V = .
50
Vin
+ ×1
R
1
125
US1010
Adj
I R
2
VoutVin
IAdj = 50uA
2
Vref
Vout
R1
R2
1010app2-1.0
regulation is achieved when the bottom side of R2 is
connected to the load and the top side of R1 resistor is
connected directly to the case or the Vout pin of the
regulator and not to the load. In fact , if R1 is connected
to the load side, the effective resistance between the
regulator and the load is gained up by the factor of (1+R2/
R1) ,or the effective resistance will be ,Rp(eff)=Rp*(1+R2/
R1).It is important to note that for high current applications, this can represent a significant percentage of the
overall load regulation and one must keep the path from
the regulator to the load as short as possible to minimize this effect.
RESISTANCE
Rp
Vin
VoutVin
US1010
Adj
R1
R2
R
L
Figure 2 - Typical application of the US1010
for programming the output voltage.
The US1010 keeps a constant 1.25V between the output pin and the adjust pin. By placing a resistor R1 across
these two pins a constant current flows through R1, adding to the Iadj current and into the R2 resistor producing
a voltage equal to the (1.25/R1)*R2 + Iadj*R2 which will
be added to the 1.25V to set the output voltage. This is
summarized in the above equation. Since the minimum
load current requirement of the US1010 is 10 mA , R1 is
typically selected to be 121Ω resistor so that it automatically satisfies the minimum current requirement.
Notice that since Iadj is typically in the range of 50uA it
only adds a small error to the output voltage and should
only be considered when a very precise output voltage
setting is required. For example, in a typical 3.3V application where R1=121Ω and R2=200Ω the error due to
Iadj is only 0.3% of the nominal set point.
Load Regulation
Since the US1010 is only a 3 terminal device , it is not
possible to provide true remote sensing of the output
voltage at the load.Figure 3 shows that the best load
1010app3-1.0
Figure 3 - Schematic showing connection for best load
regulation
Stability
The US1010 requires the use of an output capacitor as
part of the frequency compensation in order to make the
regulator stable. Typical designs for microprocessor applications use standard electrolytic capacitors with a
typical ESR in the range of 50 to 100 mΩ and an output
capacitance of 500 to 1000uF. Fortunately as the capacitance increases, the ESR decreases resulting in a
fixed RC time constant. The US1010 takes advantage of
this phenomena in making the overall regulator loop
stable.For most applications a minimum of 100uF aluminum electrolytic capacitor such as Sanyo MVGX series ,Panasonic FA series as well as the Nichicon PL
series insures both stability and good transient response.
2-4
Rev. 1.3
10/30/00
Page 5
Thermal Design
(
)
1
32
T
C
=
°
35
D1
US1010
The US1010 incorporates an internal thermal shutdown
that protects the device when the junction temperature
exceeds the maximum allowable junction temperature.
Although this device can operate with junction tempera-
tures in the range of 150°C ,it is recommended that the
selected heat sink be chosen such that during maximum continuous load operation the junction temperature is kept below this number. The example below for
a SCSI terminator application shows the steps in selecting the proper regulator in a surface mount package .(See US1015 for non surface mount packages)
Assuming the following specifications :
V V
IN
=
5
V V
F
=
05
.
V V
O
=
285
.
I A
OUT
MAX
=
0 8
.
A
Where ; VF is the forward voltage drop of the D1diode
as shown in figure 4.
The steps for selecting the right package with proper
board area for heatsinking to keep the junction tem-
perature below 135°C is given as :
To set the output DC voltage, we need to select R1 and
R2 :
3) Assuming R1=121 Ω , 1%
V
OUT
R
2 1 121
V
REF
× = −
285
.
125
.
1 121= −
× =
154.8 Ω
Select R2=154 ΩΩ ,1%
5V
C1
10uF
US1010
Adj
VoutVin
R1
121
1%
R2
154
1%
C2
22uF
1010app4-1.3
2.85V
Figure 4 - Final Schematic for half of the
GTL+ termination regulator.
1) Calculate the maximum power dissipation using :
P I V V
D OUT IN OUT
= × − −
P W
D
= × − − =
08 5 05 285 132. . . .
VF
( )
2) Calculate the maximum θJA allowed for our ex-
ample:
JA
JA
MAX
MAX
T T
=
P
135 35
=
D
−
= °
C W
756.. /
θ
θ
J A
−
2) Select a package from the datasheet with lower θJA
than the one calculated in the previous step.
Selecting TO252 (D Pak) with at least 0.5" square of
0.062" FR4 board using 1OZ copper has 70°C/W
which is lower than the calculated number.
Layout Consideration
The output capacitors must be located as close to
the Vout terminal of the device as possible. It is recom-
mended to use a section of a layer of the PC board as a
plane to connect the Vout pin to the output capacitors to
prevent any high frequency oscillation that may result
due to excessive trace inductance.
Rev. 1.3
10/30/00
2-5
Loading...