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UR5HCFJ8-P
Datasheet (Semtech)
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Datasheet UR5HCFJ8-P, UR5HCFJ8-FN, UR5HCFJ8-FB Datasheet (Semtech)

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Page 1
LapCoderTMUR5HCFJ8
Low-Power Keyboard
Encoder for Portable Systems
LapCoder is a trademark of Semtech Corp. All other trademarks belong to their respective companies.
www.semtech.com
1
HID & SYSTEM MANAGEMENT PRODUCTS, KEYCODERTMFAMILY
DESCRIPTION FEATURES
The LapCoderTMis a versatile, low­power keyboard encoder for portable systems. The UR5HCFJ8 provides two bi-directional channels for communication with a BIOS­compatible system as well as any optional keyboard-compatible devices, such as a 101/102 desktop keyboard.
The UR5HCFJ8 fully supports the IBM standard keyboard communication protocol; each key press generates one of the scan codes designated in the IBM Technical Reference Manuals. The keyboard encoder handles the scanning, debounce, and encoding of 82 keys organized on an 8x16 matrix and supports embedded numeric keypad functions as well as alternate scan codes for specific keys, so that a keyboard with only 82 keys is able to emulate the functionality of a 101/102 keyboard.
In addition to the system’s keyboard communication port the UR5HCFJ8 provides a fully functional keyboard input port that can be used by a standard 82/101/102 keyboard or another 8042-compatible device, such as an external numeric keypad, an OCR, or a bar-code reader. Input from both the matrix and the external device is multiplexed and presented to the system as if it were coming from a single source.
The features of UR5HCFJ8 make it ideal for use in PC/AT/PS/2 laptop/notebook designs that utilize the Fujitsu FKB7211 low-profile, full­travel membrane keyboard.
• Laptop/Notebook
• Portable Equipment
• Industrial Keyboards
• POS Terminals
• Public Information Kiosks
• Low-power, single IC suitable for 3V battery-operated systems
• Implements all functions of an 101/102 keyboard with only 82-keys
• Available in DIP, PLCC and Quad Flat packages
• Custom versions available in small or large quantities
• Interfaces the Fujitsu FKB7211 or other similar laptop/notebook keyboards to a BIOS-compatible systems
• AT / PS/2-compatible
• Interfaces an external keyboard / keypad or other 8042-compatible devices
APPLICATIONS
PIN DESCRIPTIONS
_RESET
_IRQ
KD
KC EKC EKD
VSS
VX NL R6 RP
CL C0 C1 C2 C3 C4 C5 C6 C7
1 2 3 4 5 6 7 8 9 10
DIP
11 12 13 14 15 16 17 18 19 20
VCC
40
OSCI
39
OSCO
38
EKC1
37
R7
36
SL
35
R5
34
R4
33
R3
32
R2
31
R1
30
R0
29
C8
28
C9
27
C10
26
C11
25
C12
24
C13
23
C14
22
C15
21
R6NLVX
VXA
_IRQ
_RESET
VCC
OSCI
OSC0
EKC1
NC
EKC EKD
KD
KC EKC EKD
6
7
RP KD KC
CL
12
C0
C1
C2
C3
C4
17
18
NC
NLVX_IRQ
R6 RP
CL C0 C1 C2 C3
C4C5C6
C5C6C7
_RESETNCNC
C7
1
PLCC
23
NC
GND
QFP
NC
GND
C14
C15/KT
VCC
OSCI
C15
C14
C13
C12
OSCO
C13
40
39
34
29
28
C11
EKC1
C12
R7
NC
R7 SL R5 R4 R3 R2 R1 R0 C8 C9 C10
SL R5 R4 R3 R2 R1 R0 C8 C9 C10 C11
Page 2
FUNCTIONAL DIAGRAM
ORDERING CODE
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2
Data Buffer
Interrupt Control
PC
Communication
Channel
EKC1
KC KD
Keyboard Encoder
Mode Control
Status LEDs
Row Data Inputs
Column Select
Ouputs
NL/CL/SL
3
8
16
C0­C15
R0­R7
Package options
40-pin Plastic DIP 44-pin, Plastic PLCC 44-pin, Plastic QFP
Pitch In mm’s
2 54 mm
1.27 mm
0.8 mm
TA = -40°C to +85°C
UR5HCFJ8-P UR5HCFJ8-FN UR5HCFJ8-FB
8042 Emulation
(External Keyboard)
Communication
Channel
EKC EKD
Page 3
FUNCTIONAL DESCRIPTION PIN DEFINITIONS
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3
The UR5HCFJ8 consists functionally of six major sections (see Functional Diagram, previous page). These are the Keyboard Encoder, the Mode Control Unit, the PC Communication Channel, the Data Buffer, the Interrupt Control and the 8042 Emulation Channel. All sections communicate with each other and operate concurrently.
Mnemonic DIP PLCC QFP Type Name and Function
VCC 40 44 38 I Power Supply: +5V VSS 20 22 17 I Ground OSCI 39 43 37 I Oscillator input OSCO 38 42 36 O Oscillator output _RESET 1 1 41 I Reset: Apply 0V to provide orderly start-up EKC1 37 41 35 External Keyboard Clock 1: Connects
to external keyboard Clock Line and is used to generate an interupt for every Clock Line
transition. VX 3 4 43 I Tie to Vcc VXA 3 I Tie to Vcc RP 6 7 2 I Reserved: Ties to Vcc KC 8 9 4 I/O Keyboard Clock: Connects to PC
keyboard port clock line KD 7 8 3 I/O Keyboard Data: Connects to
PC port data line EKD 10 11 6 I/O External Keyboard Data: Connects to
external keyboard Data Lne ECK 9 10 5 I/O External Keyboard Clock: Connects
to external keyboard Clock Line _IQR 2 2 42 I Interrupt Line: Reserved for low-power
applications R0-R5 29-34 32-37 27-32 I Row Data Inputs R6 5 6 1 I R7 36 39 34 I C0-C7 12-19 13-17 8-15 O Column Select Outputs: Selects 1 of
19-21 O 16 columns
C8-C15 28-21 31-24 26-23 O
21-18 O CL 11 12 7 O Caps Lock LED NL 4 5 44 O Num Lock LED SL 35 38 33 O Scroll Lock LED NC 18 16,22 No Connects: These pins are unused.
23,40 39,40
Note: An underscore before a pin mnemonic denotes an active low signal.
KEYBOARD ENCODER
The controller continuously scans a keyboard organized as an 8 row by 16 column matrix for a maximum of 128 keys. Smaller-size keyboards are supported provided that all unused row lines are pulled to Vcc.
The IC selects 1 of the 16 column lines (C0-C15) every 512 mS and then reads the row data lines (R0­R7). A key closure is detected as a 0 in the corresponding position of the matrix. A complete scan cycle for the entire keyboard takes approximately 9.2 mS. Each key found pressed is debounced for a period of 20 mS. Once the key is verified, the corresponding key code(s) are loaded into the transmit buffer of the PC Communication Channel.
Switch Matrix Encoding
Each matrix location is programmed to represent either a single key or a key combination of the IBM 101/102 standard keyboard.
Scan Code Table Sets
The UR5HCFJ8 supports all three scan code table sets. Scan Code Sets 1 and 2 are the default sets for AT/PS/2 systems. Scan Code Table Set 3 allows the user to program individual key attributes such as Make/Break and Typematic or Single-Touch Action. For more information, refer to the IBM Technical Reference Manuals.
Page 4
KEYBOARD ENCODER, (CON’T) MODE CONTROL
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4
Embedded Numeric Keypad
The UR5HCFJ8 implements an embedded numeric keypad. The Numeric Keypad Function is invoked by pressing the Num Lock Key.
FN Key
A special FN Key has been implemented to perform the following functions while it is held pressed:
• Function Key F1 becomes F11
• Function Key F2 becomes F12
• Ctrl Left Key becomes Ctrl Right
•
Alt Left Key becomes Alt Right
If Num Lock is set:
• Embedded numeric keypad keys become regular keys.
If Num Lock is not set:
• Embedded numeric keypad keys provide the same codes as a numeric keypad when the Num Lock is not set (Arrow Keys, PgUp, PgDn, etc.)
Status LED indicators
The controller provides interfacing for three LED shift status indicators. All three pins are active low to indicate the status of the host system (Num Lock, Caps Lock and Scroll Lock). They are set by the system (AT/PS/2 protocol).
Operating modes are defined by the logic level of the mode pin in the Mode Control Unit.
N-Key Rollover
In this mode, the code(s) corresponding to each key press are transmitted to the host system as soon as that key is debounced, independently of the release of other keys. If a key is defined to be Typematic, the corresponding code(s) will be transmitted while that key is held pressed. When the key is released, the corresponding break code(s) are then transmitted to the host system. If the released key happens to be the most recently pressed, then Typematic Action is terminated. There is no limitation to the number of keys that can be held pressed at the same time. However, two or more key closures, occurring within a time interval of less than 5 mS, will set an error flag and will not be processed. This procedure protects against the effects of accidental key presses.
“Ghost” Keys
In any scanned contact switch matrix, whenever three keys defining a rectangle on the switch matrix are held pressed at the same time, a fourth key positioned on the fourth corner of the rectangle is sensed as being pressed. This is known as the “ghost” or “phantom” key problem. Although the problem cannot be totally eliminated without using external hardware, there are methods to neutralize its negative effects for most practical applications. Keys that are intended to be used in combinations or are likely to be pressed at the same time by a fast typist (i.e., keys located in adjacent positions on the keyboard) should be placed in the same row or column of the matrix, whenever possible. Shift keys (Shift, Alt, Ctrl) should not reside in the same row (or column) with any other keys.
The UR5HCFJ8 has built-in mechanisms to detect the presence of “ghost” keys, thus eliminating the necessity of external hardware.
Actual key presses
“Ghost”
Key
Figure 1: “Ghost” or “Phantom” Key Problem
Page 5
SPECIAL HANDLING PC COMMUNICATION
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5
The UR5HCFJ8 implements all the standard functions of communication with a BIOS­compatible PC/XT or AT/PS/2 host system. Two lines, KC and KD, provide bi-directional clock and data signals. In addition, the UR5HCFJ8 supports all commands from and to the system, as described in the IBM Technical Reference Manuals.
The following table shows the commands that the system may send and their values in hex.
Command Hex Value
Set/Reset Status ED Indicators
Echo EE Invalid Command EF Select Alternate F0
Scan Codes Invalid Command F1 Read ID F2 Set Typematic F3
Rate/Delay Enable F4 Default Disable F5 Set Default F6 Set All Keys
Typematic F7 Make/Break F8 Make F9 Typematic/Make/Break FA
Set Key Type
Typematic FB Make/Break FC
Make FD Resend FE Reset FF
Table 2: Keyboard Commands from the
System (AT/PS/2 protocol)
These commands are supported in the AT/PS/2 protocol and can be sent to the keyboard at any time.The following table shows the commands that the keyboard may send to the system.
Command Hex Value
Key Detection 00* Error/Overrun
Keyboard ID 83AB BAT Completion Code AA BAT Failure Code FC Echo EE Acknowledge (Ack) FA Resend FE Key Detection
Error/Overrun FF**
*Code Sets 2 and 3
**Code Set 1 Table 3: Keyboard Commands to the
System (AT/PS/2 protocol)
8042 Emulation Channel
The UR5HCFJ8 fully emulates a system’s keyboard port, available to a standard 82/101/102 external keyboard or other 8042-compatible device. Communication with a keyboard-compatible device is accomplished by clock and data lines via EKC and EKD pins, respectively. A third pin, EKC1, connects to the Clock Line and interrupts the controller whenever the external device initiates a communication session. When power is first applied, the controller proceeds with the standard reset sequence with the external device. Data and commands initiated from the external device are buffered in the controller’s FIFO along with data from the scanned matrix, and then are presented to the system as if they were coming from a single source. After they are acknowledged, commands and data from the system are transmitted to the external device.
Hot Plug-Ins of External Device
The UR5HCFJ8 will detect the presence of an external device. If an external keyboard or other device was not connected during power-on and is connected at a later time, the encoder will proceed with the normal reset routine in order to properly initialize the external keyboard. After communication has been established, the encoder will continue to check for the presence of the external keyboard. While the external device is connected, the encoder will not enter the sleep mode. If the device is disconnected at a later time, the encoder will become aware of it. If a subsequent connection takes place, the controller will reinitiate a reset sequence. This unique feature allows the user to connect or disconnect an external device at any time without having to reset the system.
Shift Status LEDs
Shift Status LEDs (Num Lock, Caps Lock and Scroll Lock) indicate the status of the system and are controlled by commands sent from the system. Set/Reset Status Indicator commands from the system will be executed both by the external keyboard and the scanned matrix. For example, if the user presses the Caps Lock Key on either keyboard, the Caps Lock LED will be affected in both keyboards. The LED status indicators are properly set after every new connection of an external keyboard.
Page 6
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6
KEY MAP FOR FKB7211 (UR5HCFJ8)
Columns (C0–C13)
012345678910111213 LCtrl* Esc Tab Fn LAlt* Space ` (BkQt) Insert Delete ArrLft ArrDn LShift ArrRt
F1* Z X C . (per) / ArrUp RShift End
Pad . Pad /
1 CapLk V B N M , (com) , (appos) Enter PgDn
Pad 0
F2 A S D F J K L ; PgUp
Pad 1 Pad 2 Pad 3 Pad +
2 3 4 T Y U I O P BkSpc
Pad 4 Pad 5 Pad 6 Pad -
F4 F5 F6 F7 F8 F9 F10 NumLk ScrLk PrtScr
F3% 67890- (dash) = Pause
5 Pad 7 Pad 8 Pad 9 Pad *
Q W E R G H [ ] \ Home
Rows (R0–R7)
Page 7
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7
KEYBOARD LAYOUTS (US ENGLISH)
110
Esc
112
F1
113F2114F3115F4116
F5
118F7119F8120F9121
F10
90
125
ScLk
124
PrSc
126
Brk
1
2
2
3
3
4
4
5
5
6
6
7
7
8
9
9
10
0
11
-
12
=
13
Home
80
Tab16Q
17
W
18
E
19
R
20
T
21
Y
22
23
I
24
0
25
P
26
27
[
28
\]
29
PgUp
85
A
31
S
32
D
33
F
34
G
35
H
36
J
37
38
L
39
;
40
,
41
PgDn
86
Z
46
X
47
C
48
V
49
B
50
N
51
M
52
,
53
.
54
/
55
83
End
81
FN
Alt
60
,
1
Ins75Del
76
79
84
89
61
43
Enter
BkSp
15
Shift
57
CpsLck
30
Shift
44
58
Ctrl
SPACE
117
F6
NmLk
8
U
K
Depending on the status of the Num Lock and the FN Key, the UR5HCFJ8 implements one of four keyboard layouts. (Key numbering of a standard 101/102 keyboard is shown.)
Layout A (Default layout)
110
Esc
112
F1
113F2114F3115F4116
F5
118F7119F8120
F9
121
F10
90
125
ScLk
124
PrSc
126
Brk
1
2
2
3
3
4
4
5
5
6
6
7
7
8
9
9
10
0
11
-
12
=
13
Home
80
Tab16Q
17
W
18
E
19
R
20
T
21
Y
22
23
I
24
0
25
P
26
27
[
28
\]
29
PgUp
85
A
31
S
32
D
33
F
34
G
35
H
36
J
37
38
L
39
;
40
,
41
PgDn
86
Z
46
X
47
C
48
V
49
B
50
N
51
M
52
,
53
.
54
/
55
83
End
81
FN
Alt
60
,
1
Ins
75
Del
76
79
84
89
61
43
Enter
BkSp
15
Shift
57
CpsLck
30
Shift
44
58
Ctrl
SPACE
117
F6
NmLk
8
U
K
Layout B (Num Lock is set)
CpsLck
110
Esc
Tab16Q
Shift
Ctrl
112
F1
2
1
17
30
44
58
113F2114F3115F4116
3
2
18
W
31
A
Z
46
FN
S
X
Alt
117
F5
4
3
E
32
47
60
19
5
4
R
33
D
48
C
20
F
V
34
49
5
6
T
F6
7
6
21
22
Y
35
G
50
B
SPACE
118F7119F8120F9121
4
92
1
0
93
99
8
96
5
61
97
2
,
98
53
91
7
36
H
51
N
101
9
102
6
,
3
.
1
103
104
*
F10
100
-
Ins
105
75
+
106
/
-
95
90
NmLk
12
27
[
76
Del
,
Shift
=
41
ScLk
13
125
28
57
79
BkSp
Enter
PrSc
15
\]
43
124
29
83
84
126
Brk
80
Home
85
PgUp
86
PgDn
81
End
89
Page 8
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8
KEYBOARD LAYOUTS (US ENGLISH)
Depending on the status of the Num Lock and the FN Key, the LapCoderTMimplements one of four keyboard layouts. (Key numbering of a standard 101/102 keyboard is shown.)
Layout C (FN key pressed)
Layout D (Num Lock set and FN key pressed)
110
Esc
1
Tab16Q
30
CpsLck
44
Shift
64
Ctrl
F11
2
122
17
A
Z
31
46
FN
123
F12
3
2
18
W
114F3115F4116
4
3
19
E
32
S
47
X
62
Alt
33
D
48
C
F5
5
4
R
20
6
5
34
F
49
V
6
21
T
35
G
50
B
SPACE
110
Esc
1
Tab16Q
122
F1
2
17
123F2114F3115F4116
3
2
W
18
4
3
E
19
5
4
20
R
F5
6
5
6
21
T
126
Brk
80
Home
85
PgUp
86
PgDn
81
End
89
126
Brk
80
Home
85
PgUp
106
95
-
-
NmLk
12
[
76
NmLk
12
27
[
90
,
Shift
90
41
125
ScLk
13
=
28
PrSc
15
BkSp
124
29
\]
43
Enter
2
79
125
ScLk
13
=
28
PrSc
15
BkSp
83
84
124
29
\]
117
F6
7
22
Y
117
F6
7
22
Y
118F7119F8120F9121
91
Home
36
H
51
N
7
96
PgUp
92
118F7119F8120F9121
8
23
U
End
Ins
93
99
97
5
98
53
,
61
9
8
9
24
I
101
,
10
102
PgDn
25
0
*
103
104
Del
1
0
F10
100
105 27
­+
/
Ins75Del
F10
11
26
P
30
CpsLck
44
Shift
64
Ctrl
31
A
46
Z
FN
S
X
Alt
32
47
62
33
D
48
C
34
F
49
V
35
G
50
B
SPACE
36
H
51
N
37
J
52
M
38
K
53
,
61
39
L
54
.
1
,
40
;
55
/
Ins75Del
76
41
,
Shift
57
79
43
Enter
83
84
86
PgDn
81
End
89
Page 9
IMPLEMENTATION NOTES FOR THE UR5HCFJ8
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9
The following notes pertain to the suggested schematics found on the next pages.
The Built-in Oscillator on the UR5HCFJ8 requires the attachment of the 4.00 MHz Ceramic Resonators with built-in Load Capacitors.. You can use either an AVX, part number PBRC-1.00 BR; or a Murata part number CSTCC4.00MG ceramic resonator.
It may also be possible to operate with the 4.00 MHz Crystal, albeit with reduced performance. Due to their high Q, the Crystal oscillator circuits start-up slowly. Since the LapCoderTMconstantly switches the clock on and off, it is important that the Ceramic Resonator is used (it starts up much quicker than the Crystal). Resonators are also less expensive than Crystals.
Also, if Crystal is attached, two Load Capacitors (33pF to 47pF) should be added, a Capacitor between each side of the Crystal and ground.
In both cases, using Ceramic Resonator with built-in Load Capacitors, or Crystal with external Load Capacitors, a feedback Resistor of 1 Meg should be connected between OSCin and OSCout.
Troubleshoot the circuit by looking at the Output pin of the Oscillator. If the voltage it half-way between Supply and Ground (while the Oscillator should be running) --- the problem is with the Load Caps / Crystal. If the voltage it all the way at Supply or Ground (while the Oscillator should be running) --­there are shorts on the PCB.
NOTE: when the Oscillator is intentionally turned OFF, the voltage on the Output pin of the Oscillator is High (at the Supply rail).
Page 10
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10
SUGGESTED INTERFACING FOR THE LAPCODERTMUR5HCFJ8
Vcc
EKDAT
EKBCLK
KBCLK
KBDAT
4 x 47 Pf
Vcc
4.7K
2K4.7K
2K
GND
LINE INTERFACE
Vcc
11
10
41
2
9
8
23
100K
1uF
GND
RST Vcc NL CL SL
EKD
8042 EMULATION
EKC
PORT
EKC1
IRQ
KC
PC KEYBOARD PORT
KD
COMMUNICATIONS
NC
OSCI OSCO Vss RP VXA VX
43
1 MEG
4.00 MHz
Vcc
441
44 Pin PLCC
42 22
GND
7
Vcc
Vcc
5
12 38
3 4
Vcc
STATUS LEDs
C15 24 CS15
C14 25 CS14 C13 26 CS13 C12 27 CS12 C11 28 CS11 C10 29 CS10 C9 30 CS9 C8 31 CS8
COLUMN
C7 21 CS7
SELECT
C6 20 CS6
OUTPUTS
C5 19 CS5 C4 17 CS4 C3 16 CS3 C2 15 CS2 C1 14 CS1 C0 13 CS0 C4A 18
R7A 40 R7 39 RDAT7 R6 6 RDAT6
ROW
R5 37 RDAT5
DATA
R4 36 RDAT4
INPUTS
R3 35 RDAT3 R2 34 RDAT2 R1 33 RDAT1 R0 32 RDAT0
Vcc
Vcc
8 x 22K
TO SWITCH MATRIX
22pF 22pF
GND GND
Page 11
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11
MECHANICALS FOR THE UR5HCFJ8-P
40 21
1 20
A
H
G
F
D
Seating Plane
B
L
C
J
N
M
K
Notes:
1. Positional tolerance of leads (D) shall be within 0.25 mm (0.010) at maximum material condition, in relation to the seating plane and each other.
2. Diminsion L is to the center of the leads when the leads are formed parallel.
3. Dimension B does not include mold flash.
MILLIMETERS INCHES
MIN MAX
DIM
A 51.69 52.45 B
13.72
C
3.94
D
0.36
1.02
F
G
2.54 BSC 0.100 BSC
H
1.65
J
0.20 0.008
K
2.92 0.015
L
15.24 BSC 0.600 BSC
0
M
0
N
0.51
MIN MAX
2.065
2.035
0.540
0.560
14.22
5.08 0.155 0.200
0.56 0.014
0.022
1.52 0.040 0.060
2.16 0.085
0.065
0.38
0.015
0.1353.43
0
0
0
15 0 15
1.02 0.020 0.040
Page 12
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12
MECHANICALS FOR THE UR5HCFJ8-FN
44
(Note 1)
(Note 1) 44
Z
C
+
G
G1
0.25 (0.010) T-LSMSNSP
M
N
L
44
Leads
PLCC
Y BRK
M
D
0.18 (0.007) T LSM
B
M
NSP
S
0.18 (0.007) T L
U
S
--
M
NSP
S
-
Note 1
SMS
-
W
Z1
K1
D
View D-D
H
X
0.18 (0.007)
0.18 (0.007)TT
0.25 (0.010) T
M M
G1
M
NSP
LSMSNSP
-
LSM
NSP
S
-
LSM
S
S
-
-
S
-
S
-
1
P
0.18 (0.007) T-LSMSNSP
A
0.18 (0.007) T-LSMSNSP
R
+
E
V
M
M
S
-
S
-
K
M
LSMSNSP
-
M
DIM
A B C E
F G H
J K
R
U
V W
X
Y
Z G1 K1 Z1
LSM
NSP
S
--
MILLIMETERS INCHES
MAX MIN MAX
MIN
17.40 17.65
17.65 0.685 0.695
17.40
4.20 4.57 0.165 0.180
2.29 2.79 0.090 0.110
0.33 0.48 0.013 0.019
1.27 BSC 0.050 BSC
0.66 0.81 0.026 0.032
0.51 - 0.020 -
0.64 - 0.025 -
16.51 16.66 0.650 0.656
16.51 16.66 0.650 0.656
1.21 0.042 0.048
1.07
1.07 1.21 0.042 0.048
1.07 1.42 0.042 0.056
- 0.50 - 0.020
00
2 10 2 10
15.50 16.00 0.610 0.630
1.02 - 0.040 -
00
0
2 10 2 10
-
0.685
S S
0.695
0
0
Detail S
-
0.18 (0.007)
F
J
0.010 (0.004)
T
Seating Plane
S
Notes:
1. Due to space limitation, the chip is represented by a general (smaller) case outline drawing rather than showing all 44 leads.
2. Datums L, M, N, and P determine where the top of the lead shoulder exits plastic body at mold parting line
3. DIM G1, true position to be measured at Datum T, Seating Plane
4. DIM R and U do not include mold protusion. Allowable mold protusion is
0.25 (0.010) per side.
5. Dimensioning and tolerancing per Ansi Y14.5M, 1982
6. Controlling dimension: Inch
Detail S
0.18 (0.007)TT
Page 13
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13
MECHANICALS FOR THE UR5HCFJ8-FB
L
L
A
Datum Plane
H
Detail C
C
C Seating Plane
33 23
34
Detail A
44
1
D
A
M
0.20 (0.008) C
0.05 (0.002) A-B
A-B
S
S
M
0.20 (0.008) H
A-B
S
W
X
E
G
H
B
22
B
M
S
D
S
A-B
S
D
S
A-B
V
M
B
A,B,D
Detail A
0.20 (0.008) C
0.05 (0.002) A-B
12
11
S
D
S
D
JN
M
T
R
0.20 (0.008) C
Section B-B
K
Q
M
0.20 (0.008) H
Notes
1. Dimensioning and tolerancing per Ansi Y14.5-M, 1982
2. Controlling dimension: Millimeter
3. Datum Plane "H" is located at the bottom of the lead and is coincident
F
Base Metal
D
M
A-B
S
S
D
M
Detail C
Datum
H
Plane
0.01 (0.004)
with the lead where the lead exits the plastic body at the bottom of the parting line.
4. Datums -A-, -B-, and -D- to be determined at Datum Plane -H-.
5. Dimensions S and V to be determined at seating plane -C-.
6. Dimensions A and B do not include Mold protusion. Allowable protusion is 0.25 (0.010) per side. Dimensions A and B do include mold mismatch and are determined at Datum Plane -H-.
7. Dimension D does not include Danbar protrusion. Allowable Danbar protrusion is 0.08 (0.003) total in excess of the D dimension at Maximum Material Condition. Danbar cannot be located on the lower radius or the foot.
MILLIMETERS INCHES
MIN MAX MIN MAX
DIM
A 9.90 10.10 B
9.90 10.10
2.45 0.083 0.096
C
2.10
D
0.30 0.45 0.012 0.018
E
2.00 2.10 0.079 0.083
0.30 0.40 0.012 0.016
F G
0.80 BSC 0.031 BSC
H
0.25 0.010
-
J K L M N
Q
R S
T U V W X
0.23
0.13
0.65
8.00 REF 0.315 REF
0
5 10 5 10
0.17 0.005 0.007
0.13
0
0
0 7 0 7
0.13 .30 0.005 0.012
13.45 0.530
12.95 0.510
0.13 0.005
-
0
0
--
12.95
13.45
0.40 0.016
1.6 REF
0
0.390
0.390
-
0.005
0.026
0
0
0
0
0.510
0.063 REF
0.398
0.398
0.009
0.0370.95
0
0
-
0.530
--
Page 14
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14
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Ratings Symbol Value Unit
Supply Voltage VDD -0.3 to +7.0 V Input Voltage VIN
Vss -0.3 to VDD +0.3 V Current Drain per Pin I 25 mA (not including Vss or Vdd) Operating Temperature TA T low to T high °C UR5HCFJ8-XX -40 to +85 Storage Temperature Range T
STG -65 to +150 °C
Thermal Characteristics Characteristic Symbol Value Unit
Thermal Resistance TJA
°C per W Plastic DIP 60 Plastic PLCC 70
DC Electrical Characteristics (VDD=5.0 VDC +/-10%, VSS=0 VDC, Temperature range=T low to T high unless otherwise noted) Characteristic Symbol Min Typ Max Unit
Output Voltage (I load<10µA) V
OL
0.1 V
VOH VDD–0.1 Output High Voltage (I load=0.8mA) VOH VDD–0.8 V Output Low Voltage (I load=1.6mA) V
OL
0.4 V Input High Voltage VIH 0.7xVDD VDD V Input Low Voltage VIL Vss 0.2xVDD V User Mode Current I
PP 510
mA
Data Retention Mode (0 to 70
°C) VRM 2.0 V
Supply Current* (Run) I DD 4.7 7.0 mA
I/O Ports Hi-Z Leakage Current I
IL +/-10 µA
Input Current I
IN +/- 1 µA
I/O Port Capacitance CIO 812pF *In a typical application circuit, including external A/D.
Control Timing (VDD=5.0 VDC +/-10%, VSS=0 VDC, Temperature range=T low to T high unless otherwise noted) Characteristic Symbol Min Max Unit
Frequency of Operation fOSC MHz
Crystal Option 2.0
External Clock Option dc 2.0
Crystal Oscillator Startup Time fOP MHz
Crystal (FOSC/2) 2.0
External Clock Option dc 2.0 Cycle Time tCYC 1000 ns Crystal Oscillator Startup Time toxov 100 ms Stop Recovery Startup Time ti
LCH 100 ms
Reset Pulse Width tRL 8 tcyc Interrupt Pulse Width Low tLIH 125 ns Interrupt Pulse Period ti
LIL
*tcyc
OSC1Pulse Width tOH,
TOL
90 ns
*The minimum period ti
LIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus 21 tcyc.
Page 15
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15
UR5HCFJ8 BILL OF MATERIALS FOR PAGE 10 SCHEMATIC
UR7HCFJ8-XX BOM Description Quantity Manufacturer Part# Description Bare PCB
PCB 1 PCB5-FJ8-100 PCB for UR5EVB. Thru Hole
Capacitors:
C1, C2 2 Generic Any .1uF Ceramic disk or Monolythic cap, THD C3, C4 2 Generic Any 22pF, Ceramic disk cap, THD C5, C7 2 Generic Any .01uF Ceramic disk cap, THD C6 1 Generic Any 10uF, 16V Tantalum Cap, THD C8, C9, C10, C11 4 Generic Any 47pF Ceramic disk cap, THD
ICs:
U1 1 Semtech UR7HCFJ8 LapCoder
TM
Connectors:
J1 1 Molex 39-51-3144 14 pos, ZIF Conn, Straight J2 1 Molex 39-51-3084 8 pos ZIF Conn, Straight J5 1 AMP 640456-5 5 positions .1”ST/Header J6 1 AMP 640456-6 6 positions .1”ST/Header
JP1, JP2 JP1-JP2 1 AMP 103322-3 Header, 2x3 positions, 1” E1, E2 2 S.E. PH1-025-2G Male Str Header 1x2 pos
Diode:
D1-D8 8 Generic Any Diode, small signal, THD, DO-35
LED:
J4 3 King Bright L113GDT Rect LED, cross to SSL-LX2573GD, THD
Resistors:
R1, R6, R7 3 Generic Any 1M Resistor, Carbon Film, THD R2, R3, R4 3 Generic Any 330 Ohm Resistor, Carbon Film R5 1 Generic Any 1M Resistor, Carbon Film R8, R9 2 Generic Any 4.7K Resistor, Carbon Film, THD R10, R11 2 Generic Any 2K Resistor, Carbon Film, THD R12 1 Generic Any 100K Resistor, Carbon Film, THD R13-R16 4 Generic Any 47 Ohm Resistor, Carbon Film, THD R20 1 Generic Any 22K Resistor, Carbon Fil, THD
Resistor Net:
RP1, RP2, RP3 3 CTS 761-3-332G 3.3K, 8 Resistor, 16 pins, THD, DIP RP4 1 KOA RKC82223G 22K, 8 Resistor, 9 pins, THD, SIP
Crystal:
Y1 1 ECS EC2-040-4.00 4.00MHz Low Profile Crystal, THD
Shunts:
E1-S, JP1-S, JP2-S 3 Solid Electronics MJ-254M Standard Gold 2 Position Jumper
Socket:
U1_S 1 McKenzie PLCC44P-T 44PLCC THD Socket
Notes: J3 not installed. Install shunts as follow: JP1, JP2 between pins 2 & 3; also installs in E1 Updated 2000/08/01
Page 16
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16
For sales information and product literature, contact:
HID & System Mgmt Division Semtech Corporation 568 Broadway New York, NY 10012
hidinfo@semtech.com http://www.semtech.com
212 226 2042 Telephone 212 226 3215 Telefax
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Central European Sales Office +49 (0)8161 140 123 Telephone +49 (0)8161 140 124 Telefax
Copyright 1997-2001 Semtech Corporation. All rights reserved. KeyCoder, LapCoder, Zero-Power and Self-Power Management are trademarks of Semtech Corporation. Semtech is a registered trademark of Semtech Company. All other trademarks belong to their respective companies.
INTELLECTUAL PROPERTY DISCLAIMER This specification is provided "as is" with no warranties whatsoever including any warranty of merchantability, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. A license is hereby granted to reproduce and distribute this specification for internal use only. No other license, expressed or implied to any other intellectual property rights is granted or intended hereby. Authors of this specification disclaim any liability, including liability for infringement of proprietary rights, relating to the implementation of information in this specification. Authors of this specification also do not warrant or represent that such implementation(s) will not infringe such rights.
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