Datasheet UPSD3212CV, UPSD3212C, UPSD3212 Datasheet (SGS Thomson Microelectronics)

Flash Programmabl e System Dev i c es

with 8032 Microcontroller Core and 16Kbit SRAM

FEATURES SUMMARY

■ The uPSD321X Devices combine a Flash PSD

architecture with an 8032 microcontroller core.
The uPSD321X Devices of Flas h PSDs feat ure

dual banks of Flash memory, SRAM, general
purpose I/O and programmable logic, supervi­sory functions and access via I
PWM channels, and an on-board 8032 micro­controller core, with two UARTs, three 16-bit
Timer/Counters and two External Interrupts. As
with other Flash PSD families, the uPSD321X
Devices are also in-system programmable (ISP)
via a JTAG ISP interface.

■ Large 2KByte SRAM with battery back-up

option

■ Dual bank Flash memories

– 64KByte ma in Flash me mory
– 16KByte secondary Flash memory

■ Content Security

– Block access to Flash memory

■ Programmable Decode PLD for flexible address

mapping of all memories within 8032 space.

■ High-speed clock standard 8032 core (12-cycle)

2

■ I

C interface for peripheral connections

■ 5 Pulse Width Modulator (PWM) channels

■ Analog-to-Digital Converter (ADC)

■ Six I/O ports with up to 46 I/O pin s

■ 3000 gate PLD with 16 macrocells

■ Supervisor functions with Watchdog Timer

■ In-System Programming (ISP) via JTAG

■ Zero-Power Technology

■ Single Supply Voltage

– 4.5 to 5.5V
– 3.0 to 3.6V

2

C, ADC and

UPSD321 2C

UPSD3212C V

Figure 1. 52-lead, Thin, Quad, Flat Package

TQFP52 (T)

Figure 2. 80-lead, Thin, Quad, Flat Package

TQFP80 (U)

Rev. 1.2

1/152September 2003

UPSD3212C, UPSD3212CV

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

uPSD321X Devices Product Matrix (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TQFP52 Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2

TQFP80 Connections (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3

80-Pin Package Pin Description (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

52 PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Map and Address Space (Figure 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

8032 MCU Registers (Figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Configuration of BA 16-bit Registers (Figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Stack Pointer (Figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PSW (Program Status Word) Register (Figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Interrupt Location of Program Memory (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

XRAM-PSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

RAM Address (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Direct Addressing (Figure 11.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0

Indirect Addressing (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Indexed Addressing (Figure 13.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Arithmetic Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Arithmetic Instructions (Table 4.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Logical Instructions (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Data T r a nsfer In stru c ti ons th a t Acce ss Inter n al Da ta Memo ry Space (Tabl e 6.) . . . . . . . . . . . . . . 24

Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes) (Table 7.). . . . . . . 25

Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes) (Table 8.) . . . . . . . . 25

Shifting a BCD Number One Digit to the Right (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data T r a nsfer In stru c ti on tha t Acces s Exte rnal Da ta Memo ry Space (Table 10 .) . . . . . . . . . . . . . . 26

Lookup Table READ Instruction (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

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Boolean Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Boolean Instructions (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Relative Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Unconditional Jump Instructions (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Machine Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Conditional Jump Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

State Sequence in uPSD321X Devices (Figure 14.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

uPSD3200 HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

uPSD321X Devices Functional Modules (Figure 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

MCU MODULE DISCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SFR Memory Map (Table 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

List of all SFR (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PSD Module Register Address Offset (Table 17.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

INTERRUPT SYSTEM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

External Int0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Timer 0 and 1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8

Timer 2 Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

I2C Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

External Int1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

USART Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupt System (Figure 16.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9

Interrupt Priority Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Priority Levels (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

SFR Register (Table 19.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Description of the IE Bits. (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IEA Bits (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IP Bits (Table 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Description of the IPA Bits (Table 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Vector Addresses (Table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

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POWER-SAVING MODE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power-Saving Mode Power Consumption (Table 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Power Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3

Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3

Pin Status During Idle and Power-down Mode (Table 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Description of the PCON Bits (Table 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

I/O PORTS (MCU Module) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

I/O Port Functions (Table 28.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

P1SFS (91H) (Table 29.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

P3SFS (93H) (Table 30.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

P4SFS (94H) (Table 31.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

PORT Type and Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PORT Type and Description (Part 1) (Figure 17.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

PORT Type and Description (Part 2) (Figure 18.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

OSCILLATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Oscillat o r (Figu re 19 . ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

SUPERVISORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

RESET Configuration (Figure 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8

External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Low VDD Voltage Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Watchdog Timer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

WATCHDOG TIMER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Watchdog Timer Key Register (WDKEY: 0AEH) (Table 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Description of the WDKEY Bits (Table 33.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

RESET Pulse Width (Figure 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Watchdog Timer Clear Register (WDRST: 0A6H) (Table 34.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Description of the WDRST Bits (Table 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Timer 0 and Timer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1

Control Register (TCON) (Table 36.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Description of the TCON Bits (Table 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

TMOD Register (TMOD) (Table 38.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Description of the TMOD Bits (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Timer/Counter Mode 0: 13-bit Counter (Figure 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

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Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timer/Counter Mode 2: 8-bit Auto-reload (Figure 23.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Timer/Counter 2 Control Register (T2CON) (Table 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Timer/Counter 2 Operating Modes (Table 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Description of the T2CON Bits (Table 42.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Timer 2 in Capture Mode (Figure 24.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Timer 2 in Auto-Reload Mode (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Timer/Counter Mode 3: Two 8-bit Counters (Figure 26.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

STANDARD SERIAL INTERFACE (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Multiprocessor Comm u nications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Serial Port Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Serial Port Mode 0, Block Diagram (Figure 27.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Serial Port Control Register (SCON) (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Description of the SCON Bits (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Timer 1-Generated Commonly Used Baud Rates (Table 45.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Serial Port Mode 0, Waveforms (Figure 28.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

Serial Port Mode 1, Block Diagram (Figure 29.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Serial Port Mode 1, Waveforms (Figure 30.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Serial Port Mode 2, Block Diagram (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Serial Port Mode 2, Waveforms (Figure 32.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Serial Port Mode 3, Block Diagram (Figure 33.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Serial Port Mode 3, Waveforms (Figure 34.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

ANALOG-TO-DIGITAL CONVERTOR (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

ADC Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

A/D Block Diagram (Figure 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8

ADC SFR Memory Map (Table 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Description of the ACON Bits (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

ADC Clock Input (Table 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9

PULSE WIDTH MODULATION (PWM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4-channel PWM Unit (PWM 0-3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Four-Channel 8-bit PWM Block Diagram (Figure 36.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

PWM SFR Memory Map (Table 49.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Programmable Period 8-bit PWM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Programmable PWM 4 Channel Block Diagram (Figure 37.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4

PWM 4 With Programmable Pulse Width and Frequency (Figure 38.) . . . . . . . . . . . . . . . . . . . . . . 74

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I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Block Diagram of the I2C Bus Serial I/O (Figure 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Serial Control Register (S2CON) (Table 50.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Description of the S2CON Bits (Table 51.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Selection of the Serial Clock Frequency SCL in Master Mode (Table 52.) . . . . . . . . . . . . . . . . . . . 76

Serial Status Register (S2STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Data Shift Register (S2DAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Serial Status Register (S2STA) (Table 53.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Description of the S2STA Bits (Table 54.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Data Shift Register (S2DAT) (Table 55.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Address Register (S2ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8

Address Register (S2ADR) (Table 56.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Start /Stop Hold Time Detection Register (S2SETUP) (Table 57.). . . . . . . . . . . . . . . . . . . . . . . . .78

System Cock of 40MHz (Table 58.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

System Clock Setup Examples (Table 59.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

PSD MODULE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

PSD MODULE Block Diagram (Figure 40.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Methods of Programming Different Functional Blocks of the PSD MODULE (Table 60.). . . . . . . . 81

DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

PSDsoft Express Development Tool (Figure 41.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET . . . . . . . . . . . . . . . . . . . . . . . . 83

Register Address Offset (Table 61.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

MEMORY BLOCKS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Primary Flash Memory and Second ary Flash memo ry Descr ip tion . . . . . . . . . . . . . . . . . . . . . 84

Memory Block Select Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Instructions (Table 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7

Status Bit (Table 63.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89

Data Polling Flowchart (Figure 42.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9

Data Toggle Flowchart (Figure 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

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Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Specific Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

Sector Protection/Security Bit Definition – Flash Protection Register (Table 64.). . . . . . . . . . . . . .92

Sector Protection/Security Bit Definition – Secondary Flash Protection Register (Table 65.). . . . . 92

SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Sector Select and SRAM Select. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93

Priority Level of Memory and I/O Components in the PSD MODULE (Figure 44.) . . . . . . . . . . . . . 93

VM Register (Table 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Separate Space Mode (Figure 45.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Combined Space Mode (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Page Register (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

DPLD and CPLD Inputs (Table 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

The Turbo Bit in PSD MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

PLD Diagram (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

DPLD Logic Array (Figure 49.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 0

Macrocell and I/O Port (Figure 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Output Macrocell Port and Data Bit Assignments (Table 68.). . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 2

CPLD Output Macrocell (Figure 51.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Input Macrocell (Figure 52.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

I/O PORTS (PSD MODULE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

General Port Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4

General I/O Port Architecture (Figure 53.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

PLD I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Address Out Mod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

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JTAG In-System Programming (ISP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Peripheral I/O Mode (Figure 54.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Port Operating Modes (Table 69.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106

Port Operating Mode Settings (Table 70.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

I/O Port Latched Address Output Assignments (Table 71.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Port Configuration Registers (PCR) (Table 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107

Port Pin Direction Control, Output Enable P.T. Not Defined (Table 73.). . . . . . . . . . . . . . . . . . . . 107

Port Pin Direction Control, Output Enable P.T. Defined (Table 74.) . . . . . . . . . . . . . . . . . . . . . . . 107

Port Direction Assignment Example (Table 75.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

Port Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Drive Register Pin Assignment (Table 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Ports A and B – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Port A and Port B Structure (Figure 55.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Port C – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Port C Structure (Figure 56.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Port D Structure (Figure 57.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112

Port D External Chip Select Signals (Figure 58.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3

APD Unit (Figure 59.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Enable Power-down Flow Chart (Figure 60.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Power-down Mode’s Effect on Ports (Table 78.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 5

Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Power Management Mode Registers PMMR0 (Table 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Power Management Mode Registers PMMR2 (Table 80.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

APD Counter Operation (Table 81.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Reset (RESET) Timing (Figure 61.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Status During Power-on RESET, Warm RESET and Power-down Mode (Table 82.). . . . . . . . . .117

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PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . 118

Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

JTAG Port Signals (Table 83.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PLD ICC /Frequency Consumption (5V range) (Figure 62.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PLD ICC /Frequency Consumption (3V range) (Figure 63.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

PSD MODULE Example, Typ. Power Calculation at V

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Absolute Maximum Ratings (Table 85.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Operating Conditions (5V Devices) (Table 86.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

Operating Conditions (3V Devices) (Table 87.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

AC Symbols for Timing (Table 88.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Switching Waveforms – Key (Figure 64.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

DC Characteristics (5V Devices) (Table 89.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

DC Characteristics (3V Devices) (Table 90.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

External Program Memory READ Cycle (Figure 65.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

External Program Memory AC Characteristics (with the 5V MCU Module) (Table 91.) . . . . . . . . 128

External Program Memory AC Characteristics (with the 3V MCU Module) (Table 92.) . . . . . . . . 129

External Clock Drive (with the 5V MCU Module) (Table 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

External Clock Drive (with the 3V MCU Module) (Table 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . .129

External Data Memory READ Cycle (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

External Data Memory WRITE Cycle (Figure 67.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

External Data Memory AC Characteristics (with the 5V MCU Module) (Table 95.). . . . . . . . . . . . 131

External Data Memory AC Characteristics (with the 3V MCU Module) (Table 96.). . . . . . . . . . . . 132

A/D Analog Specification (Table 97.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

Input to Output Disable / Enable (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CPLD Combinatorial Timing (5V Devices) (Table 98.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

CPLD Combinatorial Timing (3V Devices) (Table 99.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Synchronous Clock Mode Timing – PLD (Figure 69.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

CPLD Macrocell Synchronous Clock Mode Timing (5V Devices) (Table 100.). . . . . . . . . . . . . . . 134

CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) (Table 101.). . . . . . . . . . . . . . . 135

Asynchronous RESET / Preset (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

Asynchronous Clock Mode Timing (product term clock) (Figure 71.) . . . . . . . . . . . . . . . . . . . . . . 136

CPLD Macrocell Asynchronous Clock Mode Timin g (5V Devices) (Table 102.). . . . . . . . . . . . . . 136

CPLD Macrocell Asynchronous Clock Mode Timin g (3V Devices) (Table 103.). . . . . . . . . . . . . . 137

= 5.0V (Turbo Mode Off) (Table 84.). . 120

CC

9/152

UPSD3212C, UPSD3212CV

Input Macrocell Timing (product term clock) (Figure 72.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Input Macrocell Timing (5V Devices) (Table 104.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Input Macrocell Timing (3V Devices) (Table 105.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Program, WRITE and Erase Times (5V Devices) (Table 106.). . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Program, WRITE and Erase Times (3V Devices) (Table 107.). . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Peripheral I/O READ Timing (Figure 73.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

Port A Peripheral Data Mode READ Timing (5V Devices) (Table 108.) . . . . . . . . . . . . . . . . . . . . 140

Port A Peripheral Data Mode READ Timing (3V Devices) (Table 109.) . . . . . . . . . . . . . . . . . . . . 140

Peripheral I/O WRITE Timing (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

Port A Peripheral Data Mode WRITE Timing (5V Devices) (Table 110.) . . . . . . . . . . . . . . . . . . . 141

Port A Peripheral Data Mode WRITE Timing (3V Devices) (Table 111.) . . . . . . . . . . . . . . . . . . . 141

Reset (RESET) Timing (5V Devices) (Table 112.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Reset (RESET) Timing (3V Devices) (Table 113.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

V

STBYON

V

STBYON

ISC Timing (Figure 76.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

ISC Timing (5V Devices) (Table 116.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

ISC Timing (3V Devices) (Table 117.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

MCU Module AC Measurement I/O Waveform (Figure 77.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

PSD MODULE AC Float I/O Waveform (Figure 78.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

External Clock Cycle (Figure 79.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Recommended Oscillator Circuits (Figure 80.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

PSD MODULE AC Measurement I/O Waveform (Figure 81.). . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

PSD MODULEAC Measurem ent Load Circuit (Figure 82.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Capacitance (Table 118.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 5

Definitions Timing (5V Devices) (Table 114.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

Timing (3V Devices) (Table 115.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

10/152

SUMMARY DESCRIPTION

■ Dual bank Flash memories

– Concurrent operation, read from memory

while erasing and writing the other. In-Appli­cation Programming (IAP) for remote updates

– Large 64KByte main Flash memory for appli-

cation code, operating systems, or bit maps
for graphic user interfaces

– Large 16KByte secondary Flash m emory di-

vided in small sectors. Eliminate external EE­PROM with software EEPROM emulation

– Secondary Flash memory is large enough for

sophisticated communicat ion protoc ol du ring
IAP while continuing critical system tasks

■ Large SRAM with battery back-up option

– 2KByte SRAM for RTOS, high-level languag-

es, communication buffers, and stacks

■ Programmable Decode PLD for flexible address

mapping of all memories
– Place individual Flash an d SRAM sectors on

any address boundary

– Built-in page regist er breaks restrictive 8032

limit of 64KByte address space

– Special register swaps Flash memory seg-

ments between 8032 “program” space and
“data” space for efficient In-Application Pro­gramming

■ High-speed clock standard 8032 core (12-cycle)

– 40MHz operation at 5V, 24MHz at 3.3V
– 2 UARTs with independent baud rat e, three

16-bit Timer/Counters and two External Inter­rupts

2

■ I

C interface for peripheral connections

– Capable of master or slave operation

■ 5 Pulse Width Modulator (PWM) channels

– Four 8-bi t PWM un its
– One 8-bit PWM unit with prog ramm abl e peri-

od

UPSD3212C, UPSD3212CV

■ 4-channel, 8-bit Analog-to-Digital Converter

(ADC) with analog supply voltage (V

■ Six I/O ports with up to 46 I/O pins

2

– Multifunction I/O: GPI O, I

C, PWM, PLD I/O,

supervisor, and JTAG

– Eliminates need for external latches and logic

■ 3000 gate PLD with 16 macrocells

– Create glue logic, state machines, delays,

etc.
– Eliminate external PALs, PLDs, and 74HCxx
– Simple PSDsoft Express software... Free

■ Supervisor functions

– Generates reset upon low voltage or watch-

dog time-out. Eliminate external supervisor

device
– RESET

■ In-System Programming (ISP) via JTAG

Input pin; Reset output via PLD

– Program entire chip in 10 - 25 seconds with

no involvement of 8032
– Allows efficient manu facturing, easy product

testing, and Just-In-Time inventory
– Eliminate sockets and pre-programmed parts

TM

– Program with FlashLINK

■ Content Security

cable and any PC

– Programmable Security Bit blocks access of

device programmers and readers

■ Zero-Power Technology

– Memories and PLD automatically reach

standby current between input changes

■ Packages

– 52-pin TQFP
– 80-pin TQFP: allows access to 8032 address/

data/control signals for connecting to external

peripherals

REF

)

11/152

UPSD3212C, UPSD3212CV

Table 1. uPSD321X Devices Product Matrix

Main

Part No.

Flash

uPSD3212C-40T6 512K 128K 16K 16 37 5 3 2 1 4 5V 40 52

uPSD3212CV-24T6 512K 128K 16K 16 37 5 3 2 1 4 3V 24 52

uPSD3212C-40U6 512K 128K 16K 16 46 5 3 2 1 4 5V 40 80

uPSD3212CV-24U6 512K 128K 16K 16 46 5 3 2 1 4 3V 24 80

Figure 3. TQ FP 52 Connection s

(bit)

Sec.

Flash

SRAM

(bit)

PB0
52515049484746454443424140

(bit)

PB1

PB2

Macro

-Cells

PB3

PB4

Pins

PB5

I/O

VREF

GND

PWM

Ch.

RESET

PB6

Timer

/ Ctr

PB7

P1.7/ADC3

UART

Ch.

P1.6/ADC2

ADC

2

C

I

Ch.

V

CC

MHz Pins

PD1

1

PC7

2

PC6

3

PC5

4

See note

Note: 1. Pull-up resis tor requ i r ed on pin 5 (2kΩ for 3V devices, 7.5kΩ for 5V dev i ces).

2. NC = Not Connected.

(1)

PC4

NC

V

CC

GND

PC3
PC2
PC1
PC0

5
6
7
8
9
10
11
12
13

14151617181920212223242526

GND

P4.2

P4.1

P4.0

P3.1 / TXD

P4.7 / PWM4

P4.6 / PWM3

P4.5 / PWM2

P4.4 / PWM1

P4.3 / PWM0

P3.0 / RXD

P3.2 / EXINT0

P3.3 / EXINT1

39 P1.5 / ADC1
38 P1.4 / ADC0
37 P1.3 / TXD1
36 P1.2 / RXD1
35 P1.1 / T2X
34 P1.0 / T2
33 V

CC

32 XTAL2
31 XTAL1
30 P3.7 / SCL1
29 P3.6 / SDA1
28 P3.5 / T1
27 P3.4 / T0

AI07423

12/152

Figure 4. TQ FP 80 Connection s

PB0

P3.2 / EXINT0

80797877767574737271706968676665646362

PB1

P3.1 / TXD

PB2

P3.0 / RXD

PB3

PB4

PB5NCVREF

GND

RESET

PB6

UPSD3212C, UPSD3212CV

PB7

RD, CNTL1

P1.7 / ADC3

PSEN, CNTL2

WR, CNTL0

P1.6 / ADC2

61

PD2

P3.3 /EXINT1

PD1

PD0, ALE

PC7
PC6
PC5

See note

P4.7 / PWM4
P4.6 / PWM3

(1)

PC4

NC
NC

V

CC

GND

PC3
PC2
PC1

NC

PC0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21222324252627282930313233343536373839

40

60 P1.5 / ADC1
59 P1.4 / ADC0
58 P1.3 / TXD1
57 P2.3, A11
56 P1.2 / RXD1
55 P2.2, A10
54 P1.1 / T2X
53 P2.1, A9
52 P1.0 / T2
51 P2.0, A8
50 V

CC

49 XTAL2
48 XTAL1
47 P0.7, AD7
46 P3.7 / SCL1
45 P0.6, AD6
44 P3.6 / SDA1
43 P0.5, AD5
42 P3.5 / T1
41 P0.4, AD4

PA7

PA6

PA5

PA4

PA3

GND

P4.5 / PWM2

P4.4 / PWM1

P4.3 / PWM0

Note: 1. Pull-up resis tor requ i r ed on pin 8 (2kΩ for 3V devices, 7.5kΩ for 5V dev i ces).

2. NC = Not Connected.

P4.2

P4.1

PA2

P4.0

PA1

PA0

AD0, P0.0

AD1, P0.1

AD2, P0.2

AD3, P0.3

P3.4 / T0

AI07424

13/152

UPSD3212C, UPSD3212CV

Table 2. 80-Pin Package Pin Description

Port Pin

P0.0 AD0 36 I/O

P0.1 AD1 37 I/O Multiplexed Address/Data bus A0/D0
P0.2 AD2 38 I/O Multiplexed Address/Data bus A2/D2
P0.3 AD3 39 I/O Multiplexed Address/Data bus A3/D3
P0.4 AD4 41 I/O Multiplexed Address/Data bus A4/D4
P0.5 AD5 43 I/O Multiplexed Address/Data bus A5/D5
P0.6 AD6 45 I/O Multiplexed Address/Data bus A6/D6
P0.7 AD7 47 I/O Multiplexed Address/Data bus A7/D7
P1.0 T2 52 I/O General I/O port pin Timer 2 Count input
P1.1 T2EX 54 I/O General I/O port pin Timer 2 Trigger input
P1.2 RxD2 56 I/O General I/O port pin 2nd UART Receive
P1.3 TxD2 58 I/O General I/O port pin 2nd UART Transmit
P1.4 ADC0 59 I/O General I/O port pin ADC Channel 0 input
P1.5 ADC1 60 I/O General I/O port pin ADC Channel 1 input
P1.6 ADC2 61 I/O General I/O port pin ADC Channel 2 input
P1.7 ADC3 64 I/O General I/O port pin ADC Channel 3 input

Signal

Name

Pin No. In/Out

Basic Alternate

External Bus
Multiplexed Address/Data bus A1/D1

Function

P2.0 A8 51 O External Bus, Address A8
P2.1 A9 53 O External Bus, Address A9
P2.2 A10 55 O External Bus, Address A10
P2.3 A11 57 O External Bus, Address A11
P3.0 RxD1 75 I/O General I/O port pin UART Receive
P3.1 TxD1 77 I/O General I/O port pin UART Transmit

P3.2 INTO 79 I/O General I/O port pin

P3.3 INT1 2 I/O General I/O port pin

P3.4 T0 40 I/O General I/O port pin Counter 0 input
P3.5 T1 42 I/O General I/O port pin Counter 1 input

P3.6 SDA1 44 I/O General I/O port pin
P3.7 SCL1 46 I/O General I/O port pin

P4.0 33 I/O General I/O port pin
P4.1 31 I/O General I/O port pin
P4.2 30 I/O General I/O port pin

P4.3 PWM0 27 I/O General I/O port pin

Interrupt 0 input / Timer 0 gate
control

Interrupt 1 input / Timer 1 gate
control

2

I

C Bus serial data I/O

2

I

C Bus clock I/O

8-bit Pulse Width Modulation
output 0

14/152

UPSD3212C, UPSD3212CV

Port Pin

P4.4 PWM1 25 I/O General I/O port pin

P4.5 PWM2 23 I/O General I/O port pin

P4.6 PWM3 19 I/O General I/O port pin

P4.7 PWM4 18 I/O General I/O port pin

Signal

Name

PUP 8 I/O

AVREF 70 O Reference Voltage input for ADC

RD_ 65 O READ signal, external bus

WR_ 62 O WRITE signal, external bus

PSEN_ 63 O PSEN

ALE 4 O Address Latch signal, external bus

RESET_ 68 I Active low RESET

XTAL1 48 I Oscillator input pin for system clock
XTAL2 49 O Oscillator output pin for system clock

Pin No. In/Out

Pull-up resistor required (2kΩ for 3V
devices, 7.5kΩ for 5V devices)

signal, external bus

Function

Basic Alternate

8-bit Pulse Width Modulation
output 1

8-bit Pulse Width Modulation
output 2

8-bit Pulse Width Modulation
output 3

Programmable 8-bit Pulse Width
modulation output 4

input

PA0 35 I/O General I/O port pin
PA1 34 I/O General I/O port pin
PA2 32 I/O General I/O port pin
PA3 28 I/O General I/O port pin
PA4 26 I/O General I/O port pin
PA5 24 I/O General I/O port pin
PA6 22 I/O General I/O port pin

PA7 21 I/O General I/O port pin
PB0 80 I/O General I/O port pin
PB1 78 I/O General I/O port pin
PB2 76 I/O General I/O port pin
PB3 74 I/O General I/O port pin
PB4 73 I/O General I/O port pin
PB5 72 I/O General I/O port pin
PB6 67 I/O General I/O port pin
PB7 66 I/O General I/O port pin

1. PLD Macro-cell outputs

2. PLD inputs

3. Latched Address Out (A0-A7)

4. Peripheral I/O Mode

1. PLD Macro-cell outputs

2. PLD inputs

3. Latched Address Out (A0-A7)

15/152

UPSD3212C, UPSD3212CV

Port Pin

PC0 TMS 20 I JTAG pin
PC1 TCK 16 I JTAG pin
PC2
PC3 TSTAT 14 I/O General I/O port pin
PC4 TERR 9 I/O General I/O port pin
PC5 TDI 7 I JTAG pin
PC6 TDO 6 O JTAG pin
PC7 5 I/O General I/O port pin

PD1 CLKIN 3 I/O General I/O port pin

PD2 CSI 1 I/O General I/O port pin

Vcc 12

Vcc 50
GND 13
GND 29
GND 69

NC 10

Signal

Name

V

STBY

Pin No. In/Out

15 I/O General I/O port pin

Function

Basic Alternate

1. PLD Macro-cell outputs

2. PLD inputs

3. SRA M stand by voltage input

4. SRAM battery-on indicator

5. JTAG pins are dedicated pins

1. PLD I/O

2. Clock input to PLD and APD

1. PLD I/O

2. Chip select to PSD Module

(V

STBY

(PC4)

)

NC 11
NC 17
NC 71

52 PIN PACKAGE I/O PORT

The 52-pin package members of the uPSD321X
Devices have the same port pins as those of the
80-pin package except:

■ Port 0 (P0.0-P0.7, external address/data bus

AD0-AD7)

■ Port 2 (P2.0-P2.3, external address bus A8-

A11)

■ Port A (PA0-PA7)

■ Port D (PD2)

■ Bus control signal (RD,WR,PSEN,ALE)

Pin 5 requires a pull-up resistor (2kΩ for 3V de­vices, 7.5kΩ for 5V devices) for all devices.

16/152

ARCHITECTURE OVERVIEW
Memory Organization

The uPSD321X Devices’s standard 8032 Core
has separate 64KB address spac es for Program
memory and Data Memory. Program memory is
where the 8032 executes in structions from. Data
memory is used to hold data variables. Flash
memory can be mapped in either program or data
space. The Flash memory consists of two flash
memory blocks: the main Flash (512Kbit) and the
Secondary Flash (128Kbit). Except during flash
memory programming or update, Flash memory
can only be read, not written to. A Page Register
is used to access memory beyond t he 64K bytes

Figure 5. Memory Map and Address Space

MAIN
FLASH

UPSD3212C, UPSD3212CV

address space. Refer to the PSD Module for de­tails on mapping of the Flash memory.

The 8032 core h as t wo ty pes of data m em ory (in­ternal and external) that can be read and written.
The internal SRAM cons ists of 256 byte s, and in­cludes the stack area.

The SFR (Special Function Registers) occupies
the upper 128 bytes of the internal SRAM, the reg­isters can be accessed by Direct addressing only.
Another 2K bytes resides in the PSD Modul e that
can be mapped to any address space defined by
the user.

EXT. RAM

SECONDARY
FLASH

16KB

Flash Memory Space

64KB

INT. RAM

FF

Indirect

Addressing

7F

Indirect
Direct

Addressing

0

Internal RAM Space
(256 Bytes)

SFR

Direct

Addressing

or

2KB

External RAM Space

(MOVX)

AI07425

17/152

UPSD3212C, UPSD3212CV

Registers

The 8032 has several registers; these are the Pro­gram Counter (PC), Accumulator (A), B Register
(B), the Stack Pointer (SP), the Program Status
Word (PSW), General purpose registers (R0 to
R7), and DPTR (Data Pointer register).

Accumulator. The Ac cumulator is the 8-bit gen­eral purpose register, used for data operation such
as transfer, temporary saving, and conditional
tests. The Accumulator can be used as a 16-bit
register with B Register as shown in Figure 6.

B Register. The B Register is the 8-bit general
purpose register, used f or an arithmetic operation
such as multiply, division with the Accumulator
(see Figure 7).

Stack Pointer. The Stack Pointer Register is 8
bits wide. It is incremented before data is stored
during PUSH and CALL executions. While the
stack may reside anywhere in on-chip RAM, the
Stack Po inter is initi alize d to 07h af ter reset. Th is
causes the stack to begin at location 08h (see Fig­ure 8).

Program Counter. The Program Counter is a 16­bit wide which consists of two 8-bit registers, PCH
and PCL. This counter indicates the address of the
next instruction to be executed. In RESET
the program counter has reset routine address
(PCH:00h, PCL:00h).

Program Status Word. The Program Status
Word (PSW) contains several bits that reflect the
current state of the CPU and select Internal RAM
(00h to 1Fh: Bank0 to Bank3). The PSW is de­scribed in Figure 9, page 19. It contains the Carry
Flag, the Auxiliary Carry Flag, the Half Carry (for
BCD operation), the general purpose flag, the
Register Bank Select Flags, the Overflow Flag,
and Parity Flag.

[Carry Flag, CY]. This flag stores any carry or not
borrow from the ALU of CPU after an arithmetic
operation and is also changed by the Shift Instruc­tion or Rotate Instruction.

[Auxiliary Carry Flag, AC]. After operation, this is
set when there is a carry from Bit 3 of ALU or there
is no borrow from Bit 4 of ALU.

[Register Bank Select Flags, RS0, RS1]. This flags
select one of four bank(00~07H:bank0,
08~0Fh:bank1, 10~17h: bank2, 17~1Fh:bank3) in
Internal RAM.

[Overflow Flag, OV]. This flag is set to '1' when an
overflow occurs as the result of an arithmetic oper­ation involving signs. An overflow occurs when the
result of an addition or subtraction exceeds +127
(7Fh) or -128 (80h). The CLRV instruction clears
the overflow flag. There is no set instruction. When

state,

the BIT instruction is executed, Bit 6 of memory is
copied to this flag.

[Parity Flag, P]. This flag reflects on number of Ac­cumulator’s “1.” If the number of Accumulator’s 1
is odd, P=0. otherwise, P=1. The sum of adding
Accumulator’s 1 to P is always even.

R0~R7. General purpose 8-bit registers that are
locked in the lower portion of internal data area.

Data Pointer Register. Data Pointer Register is
16-bit wide which consists of two-8bit registers,
DPH and DPL. This register is used as a data
pointer for the data transmission with external data
memory in the PSD Module.

Figure 6. 8032 MCU Registers

Accumulator
B Register

Stack Pointer
Program Counter
Program Status Word

General Purpose
Register (Bank0-3)
Data Pointer Register

AI06636

PCH

DPTR(DPH)

A
B

SP

PCL

PSW

R0-R7

DPTR(DPL)

Figure 7. Configuration of BA 16-bit Registers

B

AB

A

Two 8-bit Registers can be used as a "BA" 16-bit Registers

AI06637

Figure 8. Stack Pointer

Stack Area (30h-FFh)

Bit 15 Bit 0Bit 8 Bit 7

Hardware Fixed

SP (Stack Pointer) could be in 00h-FFh

SP00h

00h-FFh

AI06638

18/152

Figure 9. PSW (Program Status Word) Registe r

UPSD3212C, UPSD3212CV

MSB

CY

PSW

Carry Flag

Auxillary Carry Flag

General Purpose Flag

AC FO RS1 RS0 OV P

Register Bank Select Flags

(to select Bank0-3)

Program Memory

The program memory consists of two Flash mem­ory: 64KByte Main Flash and 16KByte of Second­ary Flash. The Flash mem ory can be mapped to
any address space as define d by the user in the
PSDsoft Tool. It can also be mapped to Data
memory space during Flash memory update or
programming.

After reset, the CPU begins execution from loca­tion 0000h. As shown in Figure 10, each interrupt
is assigned a fixed location in Program Memory.
The interrupt causes the CPU to jump to t hat loca­tion, where it commences execution of the service
routine. External Interrupt 0, for example, is as­signed to location 0003h. If External Interrupt 0 is
going to be used, its service routine must begin at
location 0003h. If the interrupt is not going to be
used, its service location is available as gen eral
purpose Program Memory.

The interrupt service locations are spaced at 8­byte intervals: 0003h for External Interrupt 0,
000Bh for Timer 0, 0013 h for E xternal I nterrupt 1,
001Bh for Timer 1 and so forth. If an interrupt ser­vice routine is short enough (as is often the c ase
in control applications), it can reside entirely within
that 8-byte interval (see Figure 10). Longer service
routines can use a jump instruction to s kip over
subsequent interrupt locat ions, if other interrupts
are in use.

Data memory

The internal data memory is divided into four phys­ically separate d blocks: 256 bytes of internal RAM,
128 bytes of Special Function Registers (SFRs)
areas and 2K bytes (XRAM-PSD) in the PSD Mod­ule.

LSB

Reset Value 00h

Parity Flag
Bit not assigned

Overflow Flag

AI06639

RAM

Four register banks, each 8 registers wide, occupy
locations 0 through 31 in the lower RAM area.
Only one of these banks may be enabled at a time.
The next 16 bytes, locations 32 through 47, con­tain 128 directly addressable bit locations. The
stack depth is only limited by the available internal
RAM space of 256 bytes.

XRAM-PSD

The 2K bytes of XRAM-P SD resides in the PSD
Module and can be mapped to any address space
through the DPLD (Decoding PLD) as defined by
the user in PSDsoft Development tool. The XRAM­PSD has a battery backup feature that allow the
data to be retained in t he event of a power lost.
The battery is connected t o the Port C PC2 pin.
This pin must be configured in PSDSoft to be bat­tery back-up.

Figure 10. Inte rru pt Lo c atio n of P rog ra m Memory

008Bh

•

•

•

•

0013h
000Bh

0003h
0000hReset

8 Bytes

AI06640

Interrupt
Location

•

•

•

•

•

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UPSD3212C, UPSD3212CV

SFR

The SFRs can only be addressed directly in the
address range from 80h to FFh. Table 15, page 32
gives an overview of the Speci al Function Regis­ters. Sixteen address in the SFRs space are both­byte and bit-addressable. The bit-addressable
SFRs are those whose address ends in 0h and 8h.
The bit addresses in this area are 80h to FFh.

Table 3. RAM Address

Byte Address
(in Hexadecimal)

↓↓

FFh 255

30h 48

Byte Address

(in Decimal)

Addressing Modes

The addressing modes in uPSD321 X Devices in­struction set are as follows

■ Direct addressing

■ Indirect addressing

■ Register addressing

■ Register-specific addressing

■ Immediate constants addressing

■ Indexed addressing

(1) Direct addressing. I n a direct addressing t he
operand is specified by an 8-bit address field in the
instruction. Only internal Data RAM and SFRs
(80~FFH RAM) can be directly addressed.

Example:

msb Bit Address (Hex) lsb
2Fh 7F 7E 7D 7C 7B 7A 79 78 47
2Eh 77 76 75 74 73 72 71 70 46
2Dh 6F 6E 6D 6C 6B 6A 69 68 45
2Ch 67 66 65 64 63 62 61 60 44
2Bh 5F 5E 5D 5C 5B 5A 59 58 43

mov A, 3EH ;A <----- RAM[3E]

Figure 11. Direct Addressing

Program Memory

3Eh

04

A

2Ah 57 56 55 54 53 52 51 50 42

29h 4F 4E 4D 4C 4B 4A 49 48 41
28h 47 46 45 44 43 42 41 40 40
27h 3F 3E 3D 3C 3B 3A 39 38 39
26h 37 36 35 34 33 32 31 30 38
25h 2F 2E 2D 2C 2B 2A 29 28 37
24h 27 26 25 24 23 22 21 20 36
23h 1F 1E 1D 1C 1B 1A 19 18 35
22h 17 16 15 14 13 12 11 10 34
21h 0F 0E 0D 0C 0B 0A 09 08 33
20h 07 06 05 04 03 02 01 00 32

1Fh

Register Bank 3

18h 24
17h

Register Bank 2

10h 16

0Fh

Register Bank 1

08h 8
07h

Register Bank 0

00h 0

31

23

15

AI06641

(2) Indirect addressing. In indirect addressing
the instruction specifies a register which contains
the address of the operand. Both internal and ex­ternal RAM can be indirectly addressed. The ad­dress register for 8-bit addresses can be R0 or R1
of the selected register bank, or the Stack Pointer.
The address register for 16-bit addresses can only
be the 16-bit “data pointer” register, DPTR.

Example:

mov @R1, #40 H ;[R1] <-----40H

Figure 12. Indirect Addressing

Program Memory

55h

7

R1

40h

55

AI06642

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UPSD3212C, UPSD3212CV

(3) Register addressing. The register banks,

containing registers R0 through R7, can be ac­cessed by certain instructions which carry a 3-bit
register specification within the opc ode of the in­struction. Instructions that access the registers
this way are code efficient, since t his mode elimi­nates an address byte. When the instruction is ex­ecuted, one of four banks is selected at execution
time by the two bank select bits in the PSW.

Example:

mov PSW, #0001000B ; select Bank0
mov A, #30H
mov R1, A

(4) Register-specific addressing. Some in­structions are specific to a certain register. For ex­ample, some instructions always operate on the
Accumulator, or Data Pointer, etc., so no address
byte is needed to point it. The opcode it self does
that.

(5) Immediate constants addressing. The val­ue of a constant can follow the opcode in Program
memory.

Example:

mov A, #10H.

(6) Indexed addressing. Only Program memory
can be accessed with indexed addressing, a nd it
can only be read. This addressing mode is intend­ed for reading look-up tables in Program memory.
A 16-bit base register (either DPTR or PC) points
to the base of the table, and the Accumulator is set
up with the table entry number. The address of the
table entry in Program memory is formed by add­ing the Accumulator data to the bas e p ointer (see
Figure 13).

Example:

movc A, @A+DPTR

Figure 13. Indexed Addressing

Arithmetic Instructions

The arithmetic instructions is listed in Table 4,
page 22. The table indicates the addressing
modes that can be used with each ins truction to
access the <byte> operand. For example, the
ADD A, <byte> instruction can be written as:

ADD a, 7FH (direct addressing)
ADD A, @R0 (indirect addressing)
ADD a, R7 (register addressing)
ADD A, #127 (immediate constant)

Note: Any byte in the internal Data Memory space
can be incremented without going through the Ac­cumulator.

One of the INC instructions operates on the 16-bit
Data Pointer. The Data Pointer is used to generate
16-bit addresses for external memory, so being
able to increment it in one 16-bit operations is

a useful feature.
The MUL A B instruc tion mul tiplies the Accum ula-

tor by the data in the B register and puts the 16-bit
product into the concatenated B and Accumulator
registers.

The DIV AB instruction divides the Accumulator by
the data in the B register and leaves the 8-bit quo­tient in the Accumulator, and the 8-bit remainder in
the B regi s ter.

In shift operations, dividing a num ber by 2n s hifts
its “n” bits to the right. Using DIV AB t o perform the
division completes the shift in 4?s and leaves the
B register holding the b its that were shifted out.
The DAA instruction is for BCD arithmetic opera­tions. In BCD arithmetic, ADD and ADDC instruc­tions should always be followed by a DAA
operation, to ensure that the result is also in BCD.

Note: DAA will not convert a binary number to
BCD. The DAA operation produces a meaningful
result only as the second step in the addition of
two BCD bytes.

ACC DPTR

3Ah 1E73h

Program Memory

3Eh

AI06643

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UPSD3212C, UPSD3212CV

Table 4. Arithmetic Instructions

Mnemonic Operation

ADD A,<byte> A = A + <byte> X X X X

ADDC A,<byte> A = A + <byte> + C X X X X
SUBB A,<byte> A = A – <byte> – C X X X X

INC A = A + 1 Accumulator only

INC <byte> <byte> = <byte> + 1 X X X

INC DPTR DPTR = DPTR + 1 Data Pointer only

DEC A = A – 1 Accumulator only

DEC <byte> <byte> = <byte> – 1 X X X

MUL AB B:A = B x A Accumulator and B only

DIV AB

DA A Decimal Adjust Accumulator only

A = Int[ A / B ]

B = Mod[ A / B ]

Dir. Ind. Reg. Imm

Logical Instructions

Table 5, page 23 shows list of uPSD321X Devices
logical instructions. The instructions that perform
Boolean operations (AND, OR, Exclusive OR,
NOT) on bytes perform the operation on a bit-by­bit basis. That is, if the Accumulator contains
00110101B and byte contains 01010011B, then:

ANL A, <byte>
will leave the Accumulat or holding 00010001B.
The addressing modes that can be used to access

the <byte> operand are listed in Table 5.
The ANL A, <byte> instruction may take any of the

forms:

ANL A,7FH(direct addressing)

ANL A, @R1 (indirect addressing)

ANL A,R6 (register addressing)

ANL A,#53H (immediate constant)
Note: Boolean operations can be performed on

any byte in the internal Data Mem ory space with­out going through the Accumulator. The XRL
<byte>, #data instruction, for example, offers a
quick and easy way to invert port bits, as in

If the operation is in response to an interrupt, not
using the Accumulator saves the time and effort to
push it onto the stack in the service routine.

The Rotate instructions (RL A , RLC A, etc.) shift
the Accumulator 1 bit to the left or right. For a left
rotation, the MSB rolls into the LSB position. For a
right rotation, the LSB rolls into the MSB position.

The SWAP A instruction interchanges the high
and low nibbles within the Accumulator. This is a
useful operation in BCD manipulations. For exam­ple, if the Accumulator contains a b inary number
which is known to be less than 100, it can be quick­ly converted to BCD by the following code:

MOVE B,#10
DIV AB
SWAP A
ADD A,B

Dividing the number by 10 leaves the tens digit in
the low nibble of the Acc umulator, and the ones
digit in the B register. The SWAP and ADD instruc­tions move the tens digit to the high nibble of the
Accumulator, and the ones digit to the low nibble.

XRL P1, #0FFH.

Addressing Modes

Accumulator and B only

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UPSD3212C, UPSD3212CV

Table 5. Logical Instructions

Mnemonic Operation

Dir. Ind. Reg. Imm

ANL A,<byte> A = A .AND. <byte> X X X X
ANL <byte>,A A = <byte> .AND. A X

ANL <byte>,#data A = <byte> .AND. #data X

ORL A,<byte> A = A .OR. <byte> X X X X
ORL <byte>,A A = <byte> .OR. A X

ORL <byte>,#data A = <byte> .OR. #data X

XRL A,<byte> A = A .XOR. <byte> X X X X
XRL <byte>,A A = <byte> .XOR. A X

XRL <byte>,#data A = <byte> .XOR. #data X

CRL A A = 00h Accumulator only
CPL A A = .NOT. A Accumulator only

RL A Rotate A Left 1 bit Accumulator only

RLC A Rotate A Left through Carry Accumulator only

RR A Rotate A Right 1 bit Accumulator only

Addressing Modes

RRC A Rotate A Right through Carry Accumulator only

SWAP A Swap Nibbles in A Accumulator only

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UPSD3212C, UPSD3212CV

Data Transfers
Internal RAM. Table 6 shows the menu of in-

structions that are available for moving data
around within the internal memory spaces, and the
addressing modes that can be used with each
one. The MOV <dest>, <src> instruction allows
data to be transferred between any two internal
RAM or SFR locations without going through t he
Accumulator. Remember, the Uppe r 128 b ytes of
data RAM can be access ed only by indirect ad­dressing, and SFR space only by di rect address­ing.

Note: In uPSD321X Devices, the stack resides in
on-chip RAM, and grows upwards . The PUSH in­struction first increments the St ack Pointer (SP),
then copies the byte into the stack. PUSH and
POP use only direct addressing to identify the byte
being saved or restored, but the stack itself is ac­cessed by indirect addressing us ing the S P regis­ter. This means the stack can go into the Upper
128 bytes of RAM, if they are implemented, but not
into SFR space.

The Data Transfer instructions include a 16-bit
MOV that can be used to initialize the Data Pointer
(DPTR) for look-up tables in Program Memory.

The XCH A, <byte> instruction causes the Accu­mulator and ad-dressed byte to exchange data.
The XCHD A, @Ri instruction is similar, but only
the low nibbles are involved in the exchange. To
see how XCH and XCHD can be used to facilitate
data manipulations, cons ider first the problem of
shifting and 8-digit BCD number two digits to the
right. Table 8 shows how this can be done using
XCH instructions. To aid in understanding how the
code works, the contents of the regist ers that are
holding the BCD number and t he content of the
Accumulator are shown alongside each instruction
to indicate their status after the instruction has
been executed.

After the routine has been executed, the Accumu­lator contains the two digits that were shifted out
on the right. Doing the routine with direct MOVs
uses 14 code bytes. The same operation with
XCHs uses only 9 bytes and executes almost
twice as fast. To right-shift by an odd number of
digits, a one-digit must be executed. Table 9
shows a sample of code that will right-shift a BCD
number one digit, using the XCHD instruction.
Again, the contents of the registers holding the
number and of the accumulator are shown along­side each instruction.

Table 6. Data Transfer Instructions that Access Internal Data Memory Space

Mnemonic Operation

Dir. Ind. Reg. Imm

MOV A,<src> A = <src> XXXX

MOV <dest>,A <dest> = A X X X

MOV <dest>,<src> <dest> = <src> XXXX

MOV DPTR,#data16 DPTR = 16-bit immediate constant X

PUSH <src> INC SP; MOV “@SP”,<src> X
POP <dest> MOV <dest>,”@SP”; DEC SP X

XCH A,<byte> Exchange contents of A and <byte> X X X

XCHD A,@Ri Exchange low nibbles of A and @Ri X

Addressing Modes

24/152

UPSD3212C, UPSD3212CV

First, pointers R1 and R0 are set up to point to the
two bytes containing the last four BCD digits. Then

Table 7. Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes)

a loop is executed which leaves the last byte, loca­tion 2EH, holding the l ast two dig its of the shi fted
number. The pointers are decremented, and the
loop is repeated for location 2DH. The CJNE in­struction (Compare and Jump if Not equal) is a
loop control that will be described later. The l oop

MOV A,2Eh 00 12 34 56 78 78
MOV 2Eh,2 Dh 00 12 34 56 56 78
MOV 2Dh,2 Ch 00 12 34 34 56 78

executed from LOOP to CJNE for R1 = 2EH, 2DH,
2CH, and 2BH. At that point the digit that was orig­inally shifted out on the right has propagated to lo­cation 2AH. Since that location should be left with

MOV 2Ch,2 Bh 00 12 12 34 56 78
MOV 2Bh,# 0 00 00 12 34 56 78

0s, the lost digit is moved to the Accumulator.

Table 8. Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes)

CLR A 00 12 34 56 78 00
XCH A,2Bh 00 0 0 34 56 78 12
XCH A,2Ch 00 00 12 56 78 34
XCH A,2Dh 00 00 12 34 78 56
XCH A,2Eh 00 0 0 12 34 56 78

Table 9. Shifting a BCD Number One Digit to the Right

2A 2B 2C 2D 2E ACC

MOV R1,#2Eh 00 12 34 56 78 xx
MOV R0,#2Dh 00 12 34 56 78 xx

2A 2B 2C 2D 2E ACC

2A 2B 2C 2D 2E ACC

; loop for R1 = 2Eh

LOOP: MOV A,@R1 00 12 34 56 78 78

XCHD A,@R0 00 12 34 58 78 76
SWAP A 00 12 34 58 78 67
MOV @R1,A 0012345867 67
DEC R1 00 12 34 58 67 67
DEC R0 00 12 34 58 67 67
CNJE R1,#2Ah,LOOP 00 12 34 58 67 67

; loop for R1 = 2Dh 00 12 38 45 67 45
; loop for R1 = 2Ch 00 18 23 45 67 23
; loop for R1 = 2Bh 08 01 23 45 67 01

CLR A 0801234567 00
XCH A,2Ah 00 01 23 45 67 08

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UPSD3212C, UPSD3212CV

External RAM. Table 10 shows a l ist of t he Data

Transfer instructions that access external Data
Memory. Only indirect addressing can be used.
The choice is whether t o use a one-byte address,
@Ri, where Ri can be either R0 or R1 of the s e­lected register bank, or a two-byte
address, @DTPR.

Note: In all external Data RAM accesses, the Ac­cumulator is always either the destination or
source of the data.

Lookup Tables. Ta ble 1 1 shows t he tw o instruc­tions that are available for reading lookup tables in
Program Memory. Since these instructions access
only Program Memory, the lookup tables can only
be read, not updated.

The mnemonic is MOVC for “move constant.” The
first MOVC instruction in Table 11 can accommo­date a table of up to 256 entries numbered 0
through 255. The number of th e desired entry is
loaded into the Accumulator, and the Data Pointer
is set up to point to the beginning of the table.
Then:

MOVC A, @A+DPTR
copies the desired table entry into the Accumula-

tor.

The other MOVC instruction works the same way,
except the Program Counter (PC) is used as the
table base, and the table is accessed through a
subroutine. First the num ber of the desired en-try
is loaded into the Accumulator, and the subroutine
is called:

MOV A , ENTRY NUMBER
CALL TABLE

The subroutine “TABLE” would look like this:

TABLE: MOVC A , @A+PC
RET

The table itself immediately follows the RET (re­turn) instruction is Program Memory. This type of
table can have up to 255 entries, numbered 1
through 255. Number 0 cannot b e used, because
at the time the MOVC instruction is execute d, the
PC contains the address of the RET instruction.
An entry numbered 0 would be the RET opcode it­self.

Table 10. Data Transfer Instruction that Access External Data Memory Space

Address Width Mnemonic Operation

8 bits MOVX A,@Ri READ external RAM @Ri

8 bits MOVX @Ri,A WRITE external RAM @Ri
16 bits MOVX A,@DPTR READ external RAM @DPTR
16 bits MOVX @DPTR,a WRITE external RAM @DPTR

Table 11. Lookup Table READ Instruction

Mnemonic Operation

MOVC A,@A+DPTR READ program memory at (A+DPTR)

MOVC A,@A+PC READ program memory at (A+PC)

26/152

Boolean Instructions

The uPSD323X Devices contain a complete Bool­ean (single-bit) processor. One page o f the inter­nal RAM contains 128 address able bits, and the
SFR space can support up to 128 addressable bits
as well. All of the port lines are bit-addressable,
and each one can be treated as a separate single­bit port. The instructions that access these bits are
not just conditional branches, but a complete
menu of move, set, clear, complement, OR and
AND instructions. These kinds of bit operations
are not easily obtained in other architectures with
any amount of byte-oriented software.

The instruction set for the Boolean processor is
shown in Table 12. All bit s acc esse s are by di rect
addressing.

Bit addresses 00h through 7Fh are in the Lower
128, and bit addresses 80h through FFh are in
SFR space.

Note how easily an internal flag can be moved to
a port pin:

MOV C,FLAG
MOV P1.0,C

In this example, FLAG is the name of any addres­sable bit in the Lower 128 or SFR space. An I/O
line (the LSB of Port 1, in this case) is set or
cleared depending on whether the Flag Bit is '1' or
'0.'

The Carry Bit in the PSW is used as the single-bit
Accumulator of the Boolean processor. Bit instruc­tions th at re fer to th e Ca rry B it as C as se mbl e a s
Carry-specific instructions (CLR C, etc.). The Car­ry Bit also has a direct address, since it resides in
the PSW register, which is bit-addressable.

Note: The Boolean instruction set includes ANL
and ORL operations, but not the XRL (Exclusive
OR) operation. An XRL operation is simple to im­plement in software. Suppose, for example, it is re­quired to form the Exclusive OR of two bits:

C = bit 1 .XRL. bit2

The software to do that could be as follows:

MOV C , bit1
JNB bit2, OVER
CPL C
OVER: (continue)

First, Bit 1 is moved to the Carry. If bit2 = 0, then
C now contains the correct result. That i s, Bit 1
.XRL. bit2 = bit1 if bit2 = 0. On the o ther hand, if
bit2 = 1, C now contains the complement of the
correct result. It need only be inverted (CPL C) to
complete the operation.

This code uses the JNB instruction, one of a series
of bit-test instructions which execute a jump if the

UPSD3212C, UPSD3212CV

addressed bit is set (JC, JB, JBC) or if the ad­dressed bit is not set (JNC, JNB). In the above
case, Bit 2 is being tested, and if bit2 = 0, the CPL
C instruction is jumped over.

JBC executes the jump if the addressed bit is set,
and also clears the bit. Thus a flag can be tested
and cleared in one operation. All the PSW bits are
directly addressable, so the Parity Bit, or the gen­eral-purpose flags, for example, are also available
to the bit-test instructions.

Relative Offset

The destination address for thes e jumps is speci­fied to the assembler by a label or by an actual ad­dress in Program memory. How-ever, the
destination address assembl es to a relative of fset
byte. This is a signed (two’s complement) offset
byte which is added to the PC in two’s complement
arithmetic if the jump is executed.

The range of the jump is therefore -128 to +127
Program Memory bytes relative to the first byte fol­lowing the instruction.

Table 12. Boolean Instructions

Mnemonic Operation

ANL C,bit C = A .AND. bit

ANL C,/bit C = C .AND. .NOT. bit

ORL C,bit C = A .OR. bit
ORL C,/bit C = C .OR. .NOT. bit
MOV C,bit C = bit
MOV bit,C bit = C

CLR C C = 0

CLR bit bit = 0

SETB C C = 1

SETB bit bit = 1

CPL C C = .NOT. C

CPL bit bit = .NOT. bit

JC rel Jump if C =1

JNC rel Jump if C = 0

JB bit,rel Jump if bit =1
JNB bit,rel Jump if bit = 0
JBC bit,rel Jump if bit = 1; CLR bit

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UPSD3212C, UPSD3212CV

Jump Instructions

Table 13 shows the list of unconditional jump in­structions. The table lists a single “JMP add” in­struction, but in fact there a re th ree S JMP, LJMP,
and AJMP, which differ in the format of the desti­nation address. JMP is a generic mnemonic which
can be used if the programmer does not care
which way the jump is en-coded.

The SJMP instruction encodes the destination ad­dress as a relative offset, as described above. The
instruction is 2 bytes long, consisting of the op­code and the relative offset byte. The jump dis­tance is limited to a range of -128 to +127 bytes
relative to the instruction following the SJMP.

The LJMP instruction encodes the destination ad­dress as a 16-bit constant. The instruction is 3
bytes long, consistin g of the op code and two ad­dress bytes. The des tination address can be any­where in the 64K Program Memory space.

The AJMP instruction encodes the destination ad­dress as an 11-bit constant. The instruction is 2
bytes long, consisting of the opcode, which itself
contains 3 of the 11 address bits, followed by an­other byte containing the low 8 bits of the destina­tion address. When the instruction is executed,
these 11 bits are simply substituted for the low 11
bits in the PC. The high 5 bits stay the same.
Hence the destination has to be within the same
2K block as the instruction following the AJMP.

In all cases the programmer specifies the destina­tion address to the assembler in the same way: as
a label or as a 16-bit constant. The assembler will
put the destination address into the correct format
for the given instruction. If the format required by
the instruction will not support t he distance t o the
specified destination address, a “Destination out
of range” message is written into the List file.

The JMP @A+DPTR instruction supports case
jumps. The destination address is computed at ex­ecution time as the sum of the 16-bit DPTR regis­ter and the Accumulator. Typically. DPTR is set up
with the address of a jump table. In a 5-way
branch, for ex-ample, an integer 0 through 4 is
loaded into the Accum ulator. The code t o be exe­cuted mi ght be as follows:

MOV DPTR, # J U MP TABLE
MOV A,INDEX_ NU MBER
RL A
JMP @A+DPTR

The RL A instruction converts the index number (0
through 4) to an even number on the range 0
through 8, because each entry in the jump table is
2 bytes long:

JUMP TABLE:
AJMP CASE 0
AJMP CASE 1
AJMP CASE 2
AJMP CASE 3
AJMP CASE 4

Table 13 shows a single “CALL a ddr” instruction,
but there are two of them, LCALL and ACALL,
which differ in the format in which the subroutine
address is given to the CPU. CALL is a generic
mnemonic which can b e used if the progra mmer
does not care which way the address is encoded.

The LCALL instruction uses the 16-bit address for­mat, and the subroutine can be anywh ere in the
64K Program Memory space. The ACALL instruc­tion uses the 11-bit format, and the subroutine
must be in the same 2K block as the instruction fol­lowing the ACALL.

In any case, the programmer specifies the subrou­tine address to the assembler in the same way: as
a label or as a 16-bit constant. The assembler will
put the address into the correct format for the giv­en instructions.

Subroutines should end with a RET instruction,
which returns execution to the instruction following
the CALL.

RETI is used to return from an interrupt service
routine. The only difference between RET and
RETI is that RET I tells the interrupt control system
that the interrupt in progress is done. If there is no
interrupt in progress at the time RETI is executed,
then the RETI is functionally identical to RET.

Table 13. Unconditional Jump Instructions

Mnemonic Operation

JMP addr Jump to addr

JMP @A+DPTR Jump to A+DPTR

CALL addr Call Subroutine at addr

RET Return from subroutine

RETI Return from Interrupt

28/152

NOP No operation

UPSD3212C, UPSD3212CV

Table 14 shows the list of conditional jumps avail­able to the uPSD321X Devices user. All of these
jumps specify the destination address by the rela­tive offset method, and so are limited to a jump dis­tance of -128 to +127 bytes from the instruction
following the conditional jump instruction. Impor­tant to note, however, the user specifies to the as­sembler the actual destination address the sam e
way as the other jumps: as a label or a 16-bit con­stant.

There is no Zero Bit in the PSW. The JZ and JNZ
instructions test the Accumulator data for that con­dition.

The DJNZ instruction (Decrement and Jump if Not
Zero) is for loop control. To execute a loop N
times, load a counter byte with N and terminate the
loop with a DJNZ to the b eginning of t he loop, as
shown below for N = 10:

MOV COUNTER,#10
LOOP: (begin loop)

•

•

•

(end loop)
DJNZ COUNTER, LOOP
(continue)

The CJNE instruction (Compare and Jump if Not
Equal) can also be used f or loo p cont rol a s in Ta­ble 9. Two bytes are specified in the operand field
of the instruction. The jump is executed only if the
two bytes are not equal. In the example of Table 9
Shifting a BCD Numb er One Digits to the Right,
the two bytes were data in R1 and the constant
2Ah. The initial data in R1 was 2Eh.

Every time the loop was executed, R1 was decre­mented, and the looping was to continue until the
R1 data reached 2Ah.

Another application of this instruction is in “greater
than, less than” comparisons. The two bytes in the
operand field are taken as unsigned integers. If the
first is less than the second, then the Carry Bit is
set (1). If the first is greater than or equal to the
second, then the Carry Bit is cleared.

Machine Cycles

A machine cycle consists of a sequence of six
states, numbered S1 through S6. Each state time
lasts for t wo oscillator peri ods. Thus, a ma chine
cycle takes 12 oscillator periods or 1µs if the oscil­lator frequency is 12MHz. Refer to Figure 14, page

30.
Each state is divided into a Phase 1 half and a

Phase 2 half. State Sequence i n uPSD321X De­vices shows that retrieve/execute sequences in
states and phases for various kinds of instructions.

Normally two program retrievals are generated
during each machine cycle, even if the instruction

not

being executed does

require it. If the instruc­tion being executed does not need more code
bytes, the CPU simply ig nores the e xtra retrieval,
and the Program Counter is not incremented.

Execution of a one-cycle instruction (Figure 14,
page 30) begins during State 1 of the machine cy­cle, when the opcode is latched into the Instruction
Register. A second retrieve occurs during S4 of
the same machine cycle. Execution is complete at
the end of State 6 of this machine cycle.

The MOVX instructions take two machine cycles
to execute. No program retrieval is generated dur­ing the second cycle of a MOVX instruction. This
is the only time program retrievals are skipped.
The retrieve/execute sequence for MOVX instruc­tion is shown in Figure 14, page 30 (d).

Table 14. Conditional Jump Instructions

Addressing Modes

Mnemonic Operation

Dir. Ind. Reg. Imm

JZ rel Jump if A = 0 Accumulator only

JNZ rel Jump if A ≠ 0 Accumulator only

DJNZ <byte>,rel Decrement and jump if not zero X X

CJNE A,<byte>,rel Jump if A ≠ <byte> X X

CJNE <byte>,#data,rel Jump if <byte> ≠ #data X X

29/152

UPSD3212C, UPSD3212CV

Figure 14. State Sequence in uPSD321X Devices

Osc.

(XTAL2)

a. 1-Byte, 1-Cycle Instruction, e.g. INC A

b. 2-Byte, 1-Cycle Instruction, e.g. ADD A, adrs

c. 1-Byte, 2-Cycle Instruction, e.g. INC DPTR

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1 p1p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2 p2

Read next

Read opcode

S1 S2 S3 S4 S5 S6

Read opcode

S1 S2 S3 S4 S5 S6

Read opcode

S1 S2 S3 S4 S5 S6

Read opcode
(MOVX)

opcode and
discard

Read 2nd
Byte

Read next
opcode and
discard

Read next
opcode and
discard

Read next
opcode

Read next
opcode

Read next
opcode and
discard

S1 S2 S3 S4 S5 S6

No Fetch

No ALE

Read next
opcode and
discard

No Fetch

Read next
opcode

Read next
opcode

S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6

d. 1-Byte, 2-Cycle MOVX Instruction

Addr Data

Access External Memory

AI06822

30/152

UPSD3200 HARDWARE DESCRIPTION

The uPSD321X Devices has a m odular architec­ture with two main functional modules: the MCU
Module and the PSD Module. The MCU Module
consists of a standard 8032 core, peripheral s and
other system supporting functions. The PSD Mod­ule provides configurable Program and Data mem­ories to the 8032 CPU core. In addition, it has its
own set of I/O ports and a PLD with 16 macrocells
for general logic implementation. Ports A,B,C, and
D are general purpose programmable I/O ports

Figure 15. uPSD321X Devices Function al Mod ules

UPSD3212C, UPSD3212CV

that have a port architecture which is different from
Ports 0-4 in the MCU Module.

The PSD Module communicates with the CPU
Core through the internal address, data bus (A0­A15, D0-D7) and control signals (RD_, WR_,
PSEN_ , AL E, RESET_ ). The use r defin es the De ­coding PLD in the PSDsoft Development Tool and
can map the resources in the PSD Mo dule to any
program or data address space.

Port 3, UART,

Intr, Timers,I2C

8032 Core

2 UARTs

Interrupt

MCU MODULE

PSD MODULE

Page Register

Decode PLD

Port 1, Timers and

2nd UART and ADC

Port 1Port 3

I2C

3 Timer /

Counters

256 Byte SRAM

Channel

ADC

512Kb

Main Flash

CPLD - 16 MACROCELLSJTAG ISP

4

8032 Internal Bus

128Kb

Secondary

Flash

PSD Internal Bus

Port 4 PWM

PWM

5

Channels

A0-A15

RD,PSEN

WR,ALE

16Kb

SRAM

D0-D7

Bus

Interface

VCC, GND,

Reset Logic
LVD & WDT

XTAL

Reset

Port 0, 2
Ext. Bus

Port C,

JTAG, PLD I/O

and GPIO

Port A & B, PLD

I/O and GPIO

Port D
GPIO

Dedicated

Pins

AI07426

31/152

UPSD3212C, UPSD3212CV

MCU MODULE DISCRIPTION

This section provides a detail description of the
MCU Module system functions and Peripherals,
including:

■ Special Function Registers

■ Timers/Counter

■ Interrupts

■ PWM

■ Supervisory Function (LVD and Watchdog)

■ USART

■ Power Saving Modes

2

■ I

C Bus

■ On-chip Oscillator

■ ADC

■ I/O Ports

Table 15. SFR Memory Map

F8 FF
F0
E8 EF
E0
D8 S2CON S2STA S2DAT S2A DR DF
D0

C8
C0
B8
B0
A8
A0

(1)

B

ACC

PSW

T2CON

(1)

P4

(1)

IP

(1)

P3

(1)

IE

(1)

P2

(1)

(1)

(1)

T2MOD RCAP 2L RCAP2H TL2 TH2 CF

PSCL0L PSCL 0H PSCL1L PSCL1H IPA B7

PWM4P PWM4W

PWMCON PWM0 P WM1 PWM2 PWM3 WDRST IEA A7

Special Function Registers

A map of the on-chip memory area called the Spe­cial Function Register (SFR) space is shown in Ta­ble 15.

Note: In the SFRs not all of the addresses are oc­cupied. Unoccupied addresses are not implement­ed on the chip. READ accesses to these
addresses will in general re turn random da ta, and
WRITE accesses will have no effect. User soft­ware should write '0s' t o t hese unimplemented lo­cations.

WDKEY AF

F7

E7

D7

C7
BF

98 SC ON SBUF SCON2 SBUF2 9F
90

88
80

Note: 1. Register can be bit addressing

P1

TCON

P0

(1)

(1)

P1SFS P3SFS P4SFS ASCL A DAT AC ON 97

(1)

TMOD TL0 TL1 TH0 TH1 8F

SP DPL DPH PCON 87

32/152

UPSD3212C, UPSD3212CV

Table 16. List of all SFR

SFR

Reg Name

Addr

80 P0 FF Port 0
81 SP 07 Stack Ptr
82 DPL 00 Data Ptr Low
83 DPH 00 Data Ptr High
87 PCON SMOD SMOD1 LVREN ADSFINT RCLK1 TCLK1 PD IDLE 00 Power Ctrl

76543210

Bit Register Name

Reset
Value

Comments

88 TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00

89 TMOD Gate C/T M1 M0 Gate C/T M1 M0 00

8A TL0 00 Timer 0 Low
8B TL1 00 Timer 1 Low
8C TH0 00 Timer 0 High
8D TH1 00 Timer 1 High
90 P1 FF Port 1

91 P1SFS P1S7 P1S6 P1S5 P1S4 00

93 P3SFS P3S7 P3S6 00

94 P4SFS P4S7 P4S6 P4S5 P4S4 P4S3 P4S2 P4S1 P4S0 00

95 ASCL 00

96 ADAT AD AT7 ADAT6 ADAT5 ADAT4 ADAT3 AD AT2 ADAT1 A DAT0 00

97 ACON ADEN ADS1 ADS0 ADST ADSF 00

Timer / Cntr

Control

Timer / Cntr

Mode Control

Port 1 Select

Register

Port 3 Select

Register

Port 4 Select

Register

8-bit

Prescaler for

ADC clock

ADC Data

Register

ADC Control

Register

98 SCON SM0 SM1 SM2 REN TB8 RB8 TI RI 00

99 SBUF 00 Serial Buffer

9A SCON2 SM0 SM1 SM2 REN TB8 RB8 TI RI 00

9B SBUF2 00

A0 P2 FF Port 2

A1 PWMCON PWML PWMP PWME CFG4 CFG3 CFG2 CFG1 CFG0 00

A2 PWM0 00

Serial Control

Register

2nd UART

Ctrl Register

2nd UART

Serial Buffer

PWM Control

Polarity

PWM0

Output Duty

Cycle

33/152

UPSD3212C, UPSD3212CV

SFR

Reg Name

Addr

A3 PWM1 00

A4 PWM2 00

A5 PWM3 00

A6 WDRST 00

A7 IEA ES2

A8 IE EA - ET2 ES ET1 EX1 ET0 EX0 00

A9

AA PWM4P 00

AB PWM4W 00

AE WDKEY 00

B0 P3 FF Port 3

76543210

Bit Register Name

EI

Reset

Comments

Value

PWM1

Output Duty

Cycle

PWM2

Output Duty

Cycle

PWM3

Output Duty

Cycle

Watch Dog

Reset

2

C

00

Enable (2nd)

PWM 4 Pulse

Watch Dog

Key Register

Interrupt

Interrupt

Enable

PWM 4

Period

Wid th

B1 PSCL0L 00

B2 PSCL0H 00

B3 PSCL1L 00

B4 PSCL1H 00

B7 IPA PS2 PI2C 00

B8 IP PT2 PS PT1 PX1 PT0 PX0 00

C0 P4 FF New Port 4

C8 T2CON TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00

C9 T2MOD DCEN 00 Timer 2 Mode

CA RCAP2L 00

CB RCAP2H 00

Prescaler 0

Low (8-bit)

Prescaler 0
High (8-bit)

Prescaler 1

Low (8-bit)

Prescaler 1
High (8-bit)

Interrupt

Priority (2nd)

Interrupt

Priority

Timer 2
Control

Timer 2

Reload low

Timer 2

Reload High

34/152

UPSD3212C, UPSD3212CV

SFR

Reg Name

Addr

76543210

CC TL2 00

CD TH2 00

D0 PSW CY AC FO RS1 RS0 OV P 00

Bit Register Name

Reset
Value

Comments

Timer 2 Low

byte

Timer 2 High

byte

Program

Status Word

D1

2

C (S2)

D2 S2SETUP 00

I

Setup
D4
D5
D6
D7
D8
D9

DA
DB

2

I

DC S2CON CR2 EN1 STA STO ADDR AA CR1 CR0 00

DD S2STA GC Stop Intr TX-Md Bbusy Blost ACK_R SLV 00

DE S2DAT 00

DF S2ADR 00

C Bus

Control Reg

2

C Bus

I

Status

Data Hold

Register

2

C address

I
E0 ACC 00 Accumulator
F0 B 00 B Register

35/152

UPSD3212C, UPSD3212CV

Table 17. PSD Module Register Address Offset

CSIOP

Addr

Offset

Register Name

00 Data In (Port A) Reads Port pins as input

02 Control (Port A)

04 Data Out (Port A) Latched data for output to Port pins, I/O Output Mode 00
06 Direction (Port A) Configures Port pin as input or output. Bit = 0 selects input 00

08 Drive (Port A)

Input Macrocell

0A

0C

01 Data In (Port B)
03 Control (Port B) 00
05 Data Out (Port B) 00
07 Direction (Port B) 00
09 Drive (Port B) 00

(Port A)

Enable Out

(Port A)

76543210

Configure pin between I/O or Address Out Mode. Bit = 0 selects I/

Configures Port pin between CMOS, Open Drain or Slew rate. Bit

Reads latched value on Input Macrocells

Reads the status of the output enable control to the Port pin driver.

Bit = 0 indicates pin is in input mode.

Bit Register Name

O

= 0 selects CMOS

Reset

Value

00

00

Comments

0B

0D

1A

1B

Input Macrocell

(Port B)

Enable Out

(Port B)
10 Data In (Port C)
12 Data Out (Port C) 00
14 Direction (Port C) 00
16 Drive (Port C) 00

Input Macrocell

18

11 Data In (Port D) * * * * * *

13 Data Out (Port D) * * * * * * 00

15 Direction (Port D) * * * * * * 00

17 Drive (Port D) * * * * * * 00

(Port C)

Enable Out

(Port C)

Enable Out

(Port D)

***** *

Only Bit 1 and

2 are used

Only Bit 1 and

2 are used

Only Bit 1 and

2 are used

Only Bit 1 and

2 are used

Only Bit 1 and

2 are used

20

36/152

Output

Macrocells AB

UPSD3212C, UPSD3212CV

CSIOP

Addr

Offset

Note: (Re gi st er address = cs io p address + address offs et ; where csiop address is def i ned by user in P SD soft)

Register Name

21

22

23

C0

C2

B0 PMMR0 * *

B4 PMMR2 *

E0 Page 00 Page Register

E2 VM

* indicates bit is not used and need to s et to '0.'

Output

Macrocells BC

Mask Macrocells

AB

Mask Macrocells

BC

Primary Flash

Protection

Secondary Flash

Protection

76543210

Security

_Bit

Periph-

mode

*****

**

Bit Register Name

PLD

Mcells

PLD

array

Ale

clk

PLD

array-

clk

PLD
array
Cntl2

FL_
data

Sec3_

Prot

PLD

Turbo

PLD
array
Cntl1

Boot_

data

Sec2_

Prot

*

PLD
array
Cntl0

FL_

code

Reset

Value

Sec1_

Sec1_

APD

enable

Boot_

code

Sec0_

Prot

Prot

Prot

Sec0_

Prot

*00

**00

SR_

code

Comments

Bit = 1 sector

is protected

Security Bit =

1 device is

secured

Control PLD

power

consumption

Blocking

inputs to PLD

array

Configure

8032 Program

and Data

Space

37/152

UPSD3212C, UPSD3212CV

INTERRUPT SYSTEM

There are interrupt requests from 10 sources as
follows (see Figure 16, page 39).

■ INT0 External Interrupt

■ 2nd USART Interrupt

■ Timer 0 Interrupt

2

■ I

C Interrupt

■ INT1 External Interrupt (or ADC Interrupt)

■ Timer 1 Interrupt

■ USART Interrupt

■ Timer 2 Interrupt

Externa l In t0

– The INT0 can be either level-active or transition-

active depending on Bit IT0 in registe r TCON.
The flag that ac tuall y gen erate s t his interrupt is
Bit IE0 in TCON.

– When an external interrupt is generated, the

corresponding request flag is cleared by the
hardware when the service routine is v ectored
to only if the interrupt was transition activated.

– If the interrupt was level activated then the inter-

rupt request flag remains set until the requested
interrupt is actually generated. Then it has to de­activate the request before the interrupt service
routine is completed, or else another interrupt
will be generated.

Timer 0 and 1 Interrupts

– Timer 0 and Timer 1 Interrupts are generated by

TF0 and TF1 which are set by an overflow of
their respective Timer/Counter registers (except
for Timer 0 in Mode 3).

– These flags are cleared by the internal hard-

ware when the interrupt is serviced.

Timer 2 Interrupt

– Timer 2 Inte rrupt is generated by TF 2 which is

set by an overflow of Timer 2. This flag has to be
cleared by the software - not by hardware.

– It is also generated by the T2EX signal (Timer 2

External Interrupt P1.1) which is controlled by
EXEN2 and EXF2 Bits in the T2CON register.

2

C Interrupt

I

– The interrupt of the I

2

C is generated by Bit INTR

in the register S2STA.

– This flag is cleared by hardware.

Externa l In t1

– The INT1 can be either level active or transition

active depending on Bit IT1 in registe r TCON.
The flag that ac tuall y ge nerate s t his interrupt is
Bit IE1 in TCON.

– When an external interrupt is generated, the

corresponding request flag is cleared by the
hardware when the service routine is v ectored
to only if the interrupt was transition activated.

– If the interrupt was level activated then the inter-

rupt request flag remains set until the requested
interrupt is actually generated. Then it has to de­activate the request before the interrupt service
routine is completed, or else another interrupt
will be generated.

– The ADC can take over the External INT1 to

generate an interrupt on conversion being com­pleted

38/152

Figure 16. Inte rru pt S yst em

UPSD3212C, UPSD3212CV

Interrupt
Sources

INT0

USART

Timer

0

I2C

INT1

Timer

1

2nd

USART

Timer

2

IE /

IP / IPA Priority

High

Low

Interrupt Polling

Global
Enable

AI07427

39/152

UPSD3212C, UPSD3212CV

USART Inte rru pt

– The USART Interrupt is gene rated by RI (Re-

ceive Interrupt) OR TI (Transmit Interrupt).

– When the USART Interrupt is generated, the

corresponding request flag mus t be cleared by
the software. The interrupt service routine will
have to check the various USART regist ers to
determine the source and clear the correspond­ing flag.

– Both USART’s are identical, except for the addi-

tional interrupt controls in the Bit 4 of the addi­tional interrupt control registers (A7H, B7H).

Interrupt Priority Structure

Each interrupt source can be assigned one of two
priority levels. Interrupt priority levels are defined
by the interrupt priority special function register IP
and IPA.

0 = low priority
1 = high priority

Table 18. Priority Levels

Source Priority with Level

Int0 0 (highest)

2nd USART 1

Timer 0 2

A low priority interrupt may be interrupted by a
high priority interrupt level interrupt. A high priority
interrupt routine cannot be interrupted by any oth­er interrupt source. If two interrupts of different pri­ority occur simultaneously, the high priority level
request is serviced. If requests of the same priority
are received simultaneously, an internal polling
sequence determines which request is serviced.
Thus, within each priority level, there is a second
priority structure determined by the polling se­quence.

Interrupts Enable Structure

Each interrupt source can be individually enab led
or disabled by setting or clearing a bit in the inter­rupt enable special function register IE and IEA. All
interrupt source can also b e globally disabled by
the clearing Bit EA in IE (see Table 19). Please
see Tables 20, 21, 22, and 23 for individual bit de­scriptions.

I²C 3

Int1 4

reserved 5

Timer 1 6

reserved 7

1st USART 8

Timer 2+EXF2 9 (lowest)

Table 19. SFR Register

SFR

Addr

Reg

Name

A7 IEA — — — ES2 — —

A8 IE EA — ET2 ES ET1 EX1 ET0 EX0 00

B7 IPA — — — PS2 — —

B8 IP — — PT2 PS PT1 PX1 PT0 PX0 00

76543210

Bit Register Name

EI

PI

2

C

2

C

—00

—00

Reset
Value

Comments

Interrupt

Enable (2nd)

Interrupt

Enable

Interrupt

Priority (2nd)

Interrupt

Priority

40/152

Table 20. Description of the IE Bits.

Bit Symbol Function

Disable all interrupts:

7EA

6 — Reserved
5 ET2 Enable Timer 2 Interrupt
4 ES Enable USART Interru pt
3 ET1 Enable Timer 1 Interrupt
2 EX1 Enable External Interrupt (Int1)
1 ET0 Enable Timer 0 Interrupt
0 EX0 Enable External Interrupt (Int0)

0: no interrupt with be acknowledged
1: each interrupt source is individually enabled or disabled by setting or clearing its
enable bit

Table 21. Description of the IEA Bits

Bit Symbol Function

7 — Not used
6 — Not used
5 — Not used

UPSD3212C, UPSD3212CV

4 ES2 Enable 2nd USART Interrupt
3 — Not used
2 — Not used
1 EI2C Enable I²C Interrupt
0 — Not used

Table 22. Description of the IP Bits

Bit Symbol Function

7 — Reserved
6 — Reserved
5 PT2 Timer 2 Interrupt priority level
4 PS USART Interrupt priority level
3 PT1 Timer 1 Interrupt priority level
2 PX1 External Interrupt (Int1) priority level
1 PT0 Timer 0 Interrupt priority level
0 PX0 External Interrupt (Int0) priority level

41/152

UPSD3212C, UPSD3212CV

Table 23. Description of the IPA Bits

Bit Symbol Function

7 — Not used
6 — Not used
5 — Not used
4 PS2 2nd USART Interrupt priority level
3 — Not used
2 — Not used
1 PI2C I²C Interrupt priority level
0 — Not used

How Interrupts are Handled

The interrupt flags are sampled at S5P2 of every
machine cycle. The sa mples a re pol l e d dur i ng fol­lowing machine cycle. If one of the flags was in a
set condition at S5P2 of the preceding cycle, the
polling cycle will find it and the interrupt system will
generate an LCALL to the appropriate service rou­tine, provided this H/W generated LCALL is not
blocked by any of the following conditions:

– An interrupt of equal priority or higher priority

level is already in progress.

– The current machine cycle is not the final cycle

in the execution of the instruction in progress.

– The instruction in progress is RETI or any ac-

cess to the interrupt priority or interrupt enable
registers.

The polling cycl e is repeated with each machin e
cycle, and the values polled are the values that
were present at S5P2 of the previous machine cy­cle.

Note: If an interrupt flag is active but being re­sponded to for one of the above mentioned condi­tions, if the flag is still inactive wh en the blocking
condition is removed, the d enied interrupt wil l not
be serviced. In other words, the fact that the inter­rupt flag was once active but not serviced is not re­membered. Every polling cycle is new.

The processor acknowledges an interrupt request
by executing a hardware generated LCALL to the
appropriate service routine. The hardware gener­ated LCALL pushes the content s of the Program
Counter on to the stack (but it does n ot save the

PSW) and reloads the PC with an address that de­pends on the source of the interrupt being vec­tored to as shown in Table 24.

Execution proceeds from that location until the
RETI instruction is encountered. The RETI instruc­tion informs the processor that the interrupt routine
is no longer in progress, then pops the top two
bytes from the stack and reloads the Program
Counter. Execution of the interrupted program
continues from where it left off.

Note: A simple RET instruction wo uld also return
execution to the interrupted program, but it would
have left the interrupt control system thinking an
interrupt w as still in p rogre ss, mak in g futur e inter­rupts impossible.

Table 24. Vector Addresses

Source Vector Address

Int0 0003h

2nd USART 004Bh

Timer 0 000Bh

I²C 0043h

Int1 0013h

Timer 1 001Bh

1st USART 0023h

Timer 2+EXF2 00 2Bh

42/152

POWER-SAVING MODE

Two software selectable modes of reduced power
consumption are implemented (see Table 25).

Idle M o de

The following Functions are Switched Off.
– CPU ( Halted)
The following Function Rem ain Active During Id le

Mode.
– External Interrupts
– Timer 0, Timer 1, Timer 2
–PWM Units
– USART
–8-bit ADC

2

C Interface

–I
Note: Interrupt or RESET

terminates the Idle

Mode.

Power-Down Mode

– System Clock Halted
– LVD Logic Remains Active
– SRAM contents remains unchanged
– The SFRs retain their value until a RESET

is as-

serted

Note: The only way to exit Power-down Mode is a
RESET

.

Power Control Register

The Idle and Power-down Modes are activated by
software via the PCON register (see Tables 26
and Table 27, page 44).

UPSD3212C, UPSD3212CV

Idle M o de

The instruction that sets PCON.0 is the last in­struction executed in the normal operating mode
before Idle Mode is activated. Once in the Idle
Mode, the CPU status is preserved in its entirety:
Stack pointer, Program counter, Program status
word, Accumulator, RAM and All other registers
maintain their data during Idle Mode.

There are three ways to terminate the Idle Mode.
– Activation of any enabled interrupt will cause

PCON.0 to be cl eared by hardware terminating
Idle mode. The interrupt is serviced, and follow­ing return from interrupt instruction RETI, the
next instruction to be execut ed will be the one
which follows the instruction that wrote a logic '1'
to PCON.0.

– External hardware res et: the hardware reset is

required to be active for two machine cycle to
complete the RESET operation.

– Internal reset: the microcontroller restarts after

3 machine cycles in all cases.

Power-Down Mode

The instruction that sets PCON.1 is the las t exe­cuted prior to going into the Power-down Mode.
Once in Power-down Mode, the oscillator is
stopped. The contents of the on-chip RAM and the
Special Function Register are preserved.

The Power-down Mode can be terminated by an
extern al R ESET.

Table 25. Power- S av i ng Mode Power Co nsu m pt i on

Mode Addr/Data Ports1,3,4 PWM

Idle Maintain Data Maintain Data Active Active

Power-down Maintain Data Maintain Data Disable Disable

2

C

I

Table 26. Pin S ta t us D uri ng Idle and Po wer- d own Mode

SFR

Addr

Reg

Name

87 PCON SMOD SMOD1 LVREN ADSFINT RCLK1 TCLK1 PD IDLE 00 Power Ctrl

76543210

Bit Register Name

Reset
Value

Comments

43/152

UPSD3212C, UPSD3212CV

Table 27. Description of the PCON Bits

Bit Symbol Function

7 SMOD Double Baud Data Rate Bit UART
6 SMOD1 Double Baud Data Rate Bit 2nd UART
5 LVREN LVR Disable Bit (active High)
4 ADSFINT Enable ADC Interrupt

3
2

1 PD Activate Power-down Mode (High enable)
0 IDL Activate Idle Mode (High enable)

Note: 1. See the T2CON register for details of the flag description

I/O PORTS (MCU MODULE)

The MCU Module has five ports: Port0, Port1,
Port2, Port3 and Port 4. (Refer to the PSD Module
section on I/O ports A,B,C and D). P orts P0 and
P2 are dedicated for the external address and data
bus and is not available in the 52-pin package de­vices.

Port1 - Port3 are the same as in the st andard 8032
micro-controllers, with the exception of the addi-

RCLK1
TCLK1

(1)

Received Clock Flag (UART 2)

(1)

Transmit Clock Flag (UART 2)

tional special peripheral functions (see Table 28 ).
All ports are bi-directional. Pins of which the alter­native function is not used may be used as normal
bi-directional I/O.

The use of Port1- Port4 pins as alternative func­tions are carried out automatically by the
uPSD321X Devices provi ded t he a ssocia ted S FR
Bit is set HIGH.

Table 28. I/O Port Functions

Port Name Main Function Alternate

Port 1 GPIO

Port 3 GPIO

Port 4 GPIO PWM - Bits 3..7

Timer 2 - Bits 0,1

2nd UART - Bits 2,3

ADC - Bits 4..7

UART - Bits 0,1

Interrupt - Bits 2,3

Timers - Bits 4,5

2

C - Bits 6,7

I

44/152

UPSD3212C, UPSD3212CV

The following SFR registers (Tabl es 29, 30, and

31) are used to control the mapping of alternate
functions onto the I/O port bits. Port 1 alternate
functions are controlled using the P1SFS register,
except for Timer 2 and the 2nd UART which are
enabled by their configuration registers. P1.0 to
P1.3 are default to GPIO after reset.

Port 3 pins 6 and 7 have been modified from the
standard 8032. These pins that were used for
READ and WRITE control signals are now GPIO

or I2C bus pins. The READ and W RITE pins are
assigned to dedicated pins.

Port 3 (I

2

C) and Port 4 alternate functions are con­trolled using the P3SFS and P4SFS Special Func­tion Selection registers. A fter a res et, t he I/O pins
default to GPIO. The alternate function is enabled
if the corresponding bit in the PXSFS register is
set to '1.' Other Port 3 alternative functions (UART,
Interrupt, and Timer/Counter) are enabled by their
configuration register and do not require setting of
the bits in R3SFS.

Table 29. P1SFS (91H)

76543210

0=Port 1.7

1=ACH3

0=Port 1.6

1=ACH2

0=Port 1.5

1=ACH1

0=Port 1.4

1=ACH0

Bits Reserved Bits Reserved

Table 30. P3SFS (93H)

76543210

0 = Port 3.7

1 = SCL

2

C unit

from I

0 = Port 3.6

1 = SDA

2

C unit

from I

Bits are reserved.

Table 31. P4SFS (94H)

76543210

0=Port 4.7

1=PWM 4

0=Port 4.6
1=PWM 3

0=Port 4.5

1=PWM 2

0=Port 4.4

1=PWM 1

0=Port 4.3

1=PWM 0

0=Port 4.2

0=Port 4.1 0=Port 4.0

45/152

UPSD3212C, UPSD3212CV

PORT Type and Descripti on

Figure 17. PORT Type and Description (Part 1)

Symbol Circuit Description

RESET I

WR, RD,ALE,
PSEN

XTAL1,

XTAL2

In /

Out

O

I

NFC

xon

• Schmitt input with internal pull-up
CMOS compatible interface
NFC : 400ns

Output only

On-chip oscillator
On-chip feedback resistor
Stop in the power down mode

External clock input available
CMOS compatible interface

46/152

O

PORT0 I/O

Bidirectional I/O port
Schmitt input

Address Output ( Push-Pull )
CMOS compatible interface

AI07438

Figure 18. PORT Type and Description (Part 2)

UPSD3212C, UPSD3212CV

Symbol Circuit Function

PORT1 <3:0>,

PORT3,

PORT4<7:3,1:0>

PORT2

PORT1 < 7:4 > I/O

PORT4.2

In/

Out

I/O

I/O

Bidirectional I/O port with
internal pull-ups
Schmitt input
CMOS compatible interface

Bidirectional I/O port with
internal pull-ups
Schmitt input

CMOS compatible interface
Analog input option

an_enb

Bidirectional I/O port with internal

pull-ups

Schmitt input.
TTL compatible interface

OSCILLATOR

The oscillator c ircuit of the uP SD321X D evic es is
a single stage inverting amplifier in a Pierce oscil­lator configuration (see Figure 19). The circuitry
between XTAL1 and XTAL2 is basically an invert­er biased to the t ransfer point. Either a c rystal or
ceramic resonator can be used as the feedback el-

Figure 19. Oscillator

XTAL1 XTAL2

8 to 40 MHz

AI07428

ement to complete the o scillator circuit. Both are
operated in parallel resonance.

XTAL1 is the high gain amplifier input, and XTAL2
is the output. To drive the uPSD321X Devices ex­ternally, XTAL1 is driven from an external source
and XTAL2 left open-circuit.

XTAL1 XTAL2

External Clock

AI06620

47/152

UPSD3212C, UPSD3212CV

SUPERVISORY

There are four ways to invoke a reset and initialize
the uPSD321X Devices.

■ Via the external RESET pin

■ Via the internal LVR Block.

■ Via Watch Dog timer

The RESET
Each RESET

signal active. The CPU responds by executing an
internal reset and puts the internal registers in a
defined state. This internal reset is also routed as
an active low reset input to the PSD Module.

External Reset

The RESET
for noise reduction. A RESET
holding the RESET
power up while the oscillator is r unning. Refer to
AC spec on other RESET

mechanism is illustrated in Figure 20.

source will cause an internal reset

pin is connected to a Sc hmitt trigger

is accomplished by

pin LOW for at least 1ms at

timing requirements.

Low V

Voltage Reset

DD

An internal reset is generated by the LVR circuit
when the V
ter V

DD

the RESET

drops below the reset t hreshold. Af-

DD

reaching back up to the re set threshold,

signal will remain asserted for 10 ms
before it is released. On initial power-up the LV R
is enabled (default). After power-up the LVR can
be disabled via the LVREN Bit in the PCON Reg­ister.

Note: The LVR logic is still function al in both the
Idle and Power-down Modes.

The reset threshold:

■ 5V operation: 4V +/- 0.25V

■ 3.3V operation: 2.5V +/-0.2V

This logic supports approximately 0.1V of hystere­sis and 1µs noise-cancelling delay.

Watchdog Timer Overflow

The Watchdog Timer generates an internal reset
when its 22-bit counter overflows. See Watchdog
Timer section for details.

Figure 20. RESET

Reset

WDT

LVR

Configuration

10ms

Timer

Noise

Cancel

S

Q

R

10ms at 40Mhz
50ms at 8Mhz

CPU

Clock

Sync

CPU

&

PERI.

PSD_RST

“Active Low

AI07429

48/152

UPSD3212C, UPSD3212CV

WATCHD OG TI M E R

The hardware Watchdog Timer (WDT) resets the
uPSD321X Devices when it overflows. The WDT
is intended as a recovery method in situations
where the CPU may be subject ed to a software
upset. To pr event a syste m reset the ti mer must be
reloaded in time by the application software. If the
processor suffers a hardware/software malfunc­tion, the s oft wa re wi ll f ai l to r el oad th e ti me r. T hi s
failure will result in a reset upon overflow thus pre­venting the processor running out of control.

In the Idle Mode the watchdog timer and reset cir­cuitry remain active. The WDT consists of a 22-bit
counter, the Watchdog Timer RESET

(WDRST)

SFR and Watchdog Key Register (WDKEY).
Since the WDT is automatica lly enab led whi le the

processor is running. the user only needs to be
concerned with servicing it.

The 22-bit counter overflows when it reaches
4194304 (3FFFFFH). The WDT increments once
every machine cycle.

Table 32. Watchdog Timer Key Register (WDKEY: 0AEH)

76543210

This means the user must reset the WDT at least
every 4194304 machine cycles (1.258 seconds at
40MHz). To reset the WDT the user must write a
value between 00-7EH to the WDRST register.
The value that is written to the WDRST is loaded
to the 7MSB of the 22-bit c ounter. T his allows t he
user to pre-loaded the counter to an initial value to
generate a flexible Watchdog time out period.
Writing a “00” to WDRST clears the counter.

The watchdog timer is controlled by the watchdog
key register, WDKEY. Only pattern 01010101
(=55H), disables the watchdog timer. The rest of
pattern combinations will keep the watchdog timer
enabled. This securit y key w ill preve nt the watch­dog timer from being terminated abnormally when
the function of the watchdog timer is needed.

In Idle Mode, the oscillator continues to run. To
prevent the WDT from resetting the processor
while in Idle, the user should always set up a timer
that will periodically exit Idle, service the WDT, and
re-enter Idle Mode.

WDKEY7 WDKEY6 WDK EY5 WDKEY4 WDKEY3 WDKEY2 WDKEY1 WDKEY0

Table 33. Description of the WDKEY Bits

Bit Symbol Function

7 to 0

WDKEY7 to

WDKEY0

Enable or disable Watchdog Timer.
01010101 (=55h): disable watchdog timer. Others: enable watchdog timer

49/152

UPSD3212C, UPSD3212CV

Watchdog reset pulse width depends on the clock
frequency. The reset period is Tf

Figure 21. RESET

Pulse Width

x 12 x 222.

OSC

Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz)

Reset period

(1.258 second at 40Mhz)

(about 6.291 seconds at 8Mhz)

The RESET

pulse width is Tf

x 12 x 215.

OSC

AI06823

Table 34. Watchdog Timer Clear Register (WDRST: 0A6H)

76543210

Reserved WDR ST6 WDRST5 WDRST4 W DRS T3 WDRST2 WDRS T1 WDRST0

Table 35. Description of the WDRST Bits

Bit Symbol Function

7 — Reserved

6 to 0

Note: The Watchdog Ti m er (WDT) is enabled at po wer-up or reset and mu st be served or disabled.

WDRST6 to

WDRST0

To reset Watchdog Timer, write any value beteen 00h and 7Eh to this register.
This value is loaded to the 7 most significant bits of the 22-bit counter.
For example: MOV WDRST,#1EH

50/152

UPSD3212C, UPSD3212CV

TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2)

The uPSD321X Devices has three 16-bit Timer/
Counter registers: Timer 0, Timer 1 and Timer 2.
All of them can be c onfigured t o op erate either as
timers or event counters and are compa tible with
standard 8032 architecture.

In the “Timer” function, the register is incremented
every machine cycle. Thus, one can think of it as
counting machine cycles. Since a machine cycle
consists of 6 CPU clock periods, the count rate is
1/6 of the CPU clock frequency or 1/12 of Oscilla­tor Frequency (f

OSC

).

In the “Counter” function, the register is increment­ed in response to a 1-to-0 transition at its corre­sponding external input pin, T0 or T1. In this
function, the external input is sampled during
S5P2 of every machine c ycle. When the sam ples
show a high in one cycle and a low in the next cy­cle, the count is incremented. The new count value
appears in the register during S3P1 of the cycle

Table 36. Control Register (TCON)

76543210

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

following the one in which the t ransition was de­tected. Since it takes 2 machine cycles (24 f
clock periods) to recognize a 1-to-0 transition, the
maximum count rate is 1/24 of the f

. There are

OSC

no restrictions o n the duty cycle of the external in­put signal, but to ensure that a given level is sam­pled at least once before it changes , it should be
held for at least one full cycle. In addi tion to the
“Timer” or “Counter” selection, Tim er 0 and Timer
1 have four operating modes from which to select.

Timer 0 and Tim er 1

The “Timer” or “Counter” function is selected by
control bits C/T in the Special Function Register
TMOD. These Timer/Counters have four ope rat­ing modes, which are selected by bit-pairs (M1,
M0) in TMOD. Modes 0, 1, and 2 are the same for
Timers/ Counters. Mode 3 is different. The four op­erating modes are de-scribed in the following text.

OSC

Table 37. Description of the TCON Bits

Bit Symbol Function

7TF1

6 TR1 Timer 1 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off

5TF0

4 TR0 Timer 0 Run Control Bit. Set/cleared by software to turn Timer/Counter on or off

3IE1

2IT1

1IE0

0IT0

Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow. Cleared by
hardware when processor vectors to interrupt routine

Timer 0 Overflow Flag. Set by hardier on Timer/Counter overflow. Cleared by hardware
when processor vectors to interrupt routine

Interrupt 1 Edge Flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed

Interrupt 1 Type Control Bit. Set/cleared by software to specify falling-edge/low-level
triggered external interrupt

Interrupt 0 Edge Flag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed

Interrupt 0 Type Control Bit. Set/cleared by software to specify falling-edge/low-level
triggered external interrupt

51/152

UPSD3212C, UPSD3212CV

Table 38. TMOD Register (TMOD)

76543210

Gate C/ T

M1 M0 Gate C/T M1 M0

Table 39. Description of the TMOD Bits

Bit Symbol Timer Function

7Gate

6C/T

5 M1 (M1,M0)=(0,0): 13-bit Timer/Counter, TH1, with TL1 as 5-bit prescaler

4M0

3Gate

2C/T

1 M1 (M1,M0)=(0,0): 13-bit Timer/Counter, TH0, with TL0 as 5-bit prescaler

0M0

Timer 1

Timer 0

Gating control when set. Timer/Counter 1 is enabled only while INT1 pin is High and
TR1 control pin is set. When cleared, Timer 1 is enabled whenever TR1 control bit is set

Timer or Counter selector, cleared for timer operation (input from internal system clock);
set for counter operation (input from T1 input pin)

(M1,M0)=(0,1): 16-bit Timer/Counter. TH1 and TL1 are cascaded. There is no prescaler.
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH1 holds a value which is to be
reloaded into TL1 each time it overflows
(M1,M0)=(1,1): Timer/Counter 1 stopped

Gating control when set. Timer/Counter 0 is enabled only while INT0 pin is High and
TR0 control pin is set. When cleared, Timer 0 is enabled whenever TR0 control bit is set

Timer or Counter selector, cleared for timer operation (input from internal system clock);
set for counter operation (input from T0 input pin)

(M1,M0)=(0,1): 16-bit Timer/Counter. TH0 and TL0 are cascaded. There is no prescaler.
(M1,M0)=(1,0): 8-bit auto-reload Timer/Counter. TH0 holds a value which is to be
reloaded into TL0 each time it overflows
(M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard TImer 0 control
bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits

52/152

UPSD3212C, UPSD3212CV

Mode 0. Putting either Timer into Mode 0 makes

it look like an 8048 Timer, which is an 8-bit Counter
with a divide-by-32 prescaler. Figure 22 shows the
Mode 0 operation as it applies to Timer 1.

In this mode, the Timer register is configured as a
13-bit register. As the count rolls over from all '1s'
to all '0s,' it sets the Timer Interrupt Flag TF1. The
counted input is enabled to the Timer when TR1 =
1 and either GATE = 0 or /INT1 = 1. (Setting GATE
= 1 allows the Timer to be controlled by external in­put /INT1, to facilitate pulse width measurements).
TR1 is a control bit in the Special Function Regis-

Figure 22. Tim er/Counte r Mode 0: 13 -bit Co unter

f

OSC

T1 pin

TR1

÷ 12

C/T = 0
C/T = 1

Control

ter TCON (TCON Control Register). GATE is in
TMOD.

The 13-bit register consists of all 8 bits of TH1 and
the lower 5 bits of TL1. The upper 3 bits of TL1 are
indeterminate and shou ld be ignored. S etting the
run flag does not clear the registers.

Mode 0 operation is the same for the Timer 0 as
for Timer 1. Substitute TR0, TF0, and /INT0 for the
corresponding Timer 1 signals in Figure 22. There
are two different GATE Bits, one for T imer 1 and
one for Timer 0.

Mode 1. Mode 1 is the same as Mode 0, except
that the Timer register is being run with all 16 bits.

TL1

(5 bits)

TH1

(8 bits)

TF1 Interrupt

Gate

INT1 pin

AI06622

53/152

UPSD3212C, UPSD3212CV

Mode 2. Mode 2 configures the Timer register as

an 8-bit Counter (TL1) with a utomatic reload, as
shown in Figure 23. Overflow from TL1 not only
sets TF1, but also reloads TL1 with the contents of
TH1, which is preset by software. The reload
leaves TH1 unchanged. Mode 2 operatio n is the
same for Timer/Counter 0.

Timer 2

Like Timer 0 and 1, Timer 2 can operate as either
an event timer or as an event counter. This is se­lected by Bit C/T2 in the special function register
T2CON (see Table 40). It has three operating
modes: Capture, Auto-reload, and Baud Rate
Generator (see Table 41, page 55), which are se­lected by bits in the T2CON as shown in Table 42,
page 55. In the Capture Mode there are two op­tions which are selected by Bit EXEN2 in T2CON.
if EXEN2 = 0, then Timer 2 is a 16-bit timer or
counter which upon overflowing sets Bit TF2 , the
Timer 2 overflow bit, which can be used to gener­ate an interrupt. If EXEN2 = 1, then Timer 2 still
does the above, but with the added feature that a

Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload

1-to-0 transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and
TH2, to be captured into registers RCAP2L and
RCAP2H, respectively. In addition, the transition
at T2EX causes Bit EXF2 in T2CON to be set, and
EXF2 like TF2 can generate an interrupt. The Cap­ture Mode is illustrated in Figure 24, page 56.

In the Auto-reload Mode, there are again two op­tions, wh i c h ar e selected b y b i t EXEN2 in T2CON.
If EXEN2 = 0, then when Timer 2 rolls over it not
only sets TF2 but a lso causes the T imer 2 regis­ters to be reloaded with the 16-bit value in regis­ters RCAP2L and RCAP2 H, which are preset by
software. If EXEN2 = 1, then Timer 2 still does the
above, but with the added feature that a 1-to-0
transition at external input T2E X will also trigger
the 16-bit reload and set EXF2. The Auto-reload
Mode is illustrated in Standard Serial Interface
(UART) Figure 25, page 5 6. The Ba ud Rat e G en­eration Mode is selected by (RCLK, RCLK1) = 1
and/or (TCLK, TCLK1) = 1. It will be described in
conjunction with the serial port.

Gate

INT1 pin

f

OSC

T1 pin

TR1

÷ 12

C/T = 0
C/T = 1

Control

TL1

(8 bits)

TH1

(8 bits)

TF1 Interrupt

AI06623

Table 40. Timer/Counter 2 Control Register (T2CON)

76543210

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T

2 CP/RL2

54/152

Table 41. Timer/Counter 2 Operating Modes

T2CON

Mode

RxCLK

or

TxCLK

CP/

RL

2

T2MOD

TR2 Internal

DECN

0 0 1 0 0 x reload upon overflow

T2CON

EXEN

P1.1

T2EX

UPSD3212C, UPSD3212CV

Input Clock

Remarks

External

(P1.0/T2)

16-bit

Auto-

reload

0010 1↓

0 0 1 1 x 0 Down counting

reload trigger (falling
edge)

f

OSC

/12

0 0 1 1 x 1 Up count ing

16-bit

011x 0x

Capture

011x 1↓

1x1x 0x

Baud Rate

Generator

1x1x 1↓

16-bit Timer/Counter
(only up counting)

Capture (TH1,TL2) →
(RCAP2H,RC A P2L)

No Overflow Interrupt
Request (TF2)

Extra External Interrupt
(Timer 2)

f

f

OSC

OSC

/12

/12

Off x x 0 x x x Timer 2 stops — —

Note: ↓ = fal l i ng edge

Table 42. Description of the T2CON Bits

Bit Symbol Function

7TF2

6EXF2

5

RCLK

Timer 2 Overflow Flag. Set by a Timer 2 overflow, and must be cleared by software. TF2
will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1

Timer 2 External Flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will
cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared by
software

Receive Clock Flag (UART 1). When set, causes the serial port to use Timer 2 overflow

(1)

pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the receive clock

MAX

f

OSC

MAX

f

OSC

MAX

f

OSC

/24

/24

/24

Transmit Clock Flag (UART 1). When set, causes the serial port to use Timer 2 overflow

(1)

4

TCLK

pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the transmit clock

Timer 2 External Enable Flag. When set, allows a capture or reload to occur as a result

3 EXEN2

of a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2=0 causes Time 2 to ignore events at T2EX

2 TR2 Start/stop control for Timer 2. A logic 1 starts the timer

1C/T

Timer or Counter Select for Timer 2. Cleared for timer operation (input from internal

2

system clock, t

); set for external event counter operation (negative edge triggered)

CPU

Capture/Reload Flag. When set, capture will occur on negative transition of T2EX if
EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or

0 CP/RL

2

negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,
TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow

Note: 1. The RCLK1 and TCLK1 B i ts i n th e PCON Regi ster control UART 2, and have the s am e function as RCLK and TCLK .

55/152

UPSD3212C, UPSD3212CV

Figure 24. Timer 2 in Capture Mode

f

OSC

T2 pin

T2EX pin

÷ 12

Transition

Detector

C/T2 = 0
C/T2 = 1

TR2

EXEN2

Control

Capture

Control

Figure 25. Timer 2 in Auto-Reload Mode

TL2

(8 bits)

RCAP2L

TH2

(8 bits)

RCAP2H

TF2

Timer 2
Interrupt

EXP2

AI06625

f

OSC

T2 pin

T2EX pin

÷ 12

Transition

Detector

C/T2 = 0

C/T2 = 1

TR2

EXEN2

Control

Reload

Control

TL2

(8 bits)

RCAP2L

TH2

(8 bits)

RCAP2H

TF2

Timer 2
Interrupt

EXP2

AI06626

56/152

UPSD3212C, UPSD3212CV

Mode 3. Timer 1 in Mode 3 simply holds its count.

The effect is the same as setting TR1 = 0.
Timer 0 in Mode 3 establishes TL0 and TH0 as two

separate counters. The logic for Mode 3 on Timer
0 is shown in Figure 26. TL0 uses the Timer 0 con­trol Bits: C/T, GATE, TR0, INT0, an d TF0. TH0 is
locked into a timer function (counting machine cy­cles) and takes over the use of TR1 and TF1 from

Mode 3 is provided f or applications requiring an
extra 8-bit timer on the counter. With Timer 0 in
Mode 3, an uPSD321X Devices can look like it has
three Timer/Counters. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out
of and into its own Mode 3, or can still be used by
the serial port as a baud rate generator, or in fact,
in any application not requiring an interrupt.

Timer 1. Thus, TH0 now controls the “Timer 1“ In­terrupt.

Figure 26. Timer/Counter Mode 3: Two 8-bit Counters

Gate

INT0 pin

f

OSC

T0 pin

TR0

÷ 12

C/T = 0
C/T = 1

Control

TL0

(8 bits)

TF0 Interrupt

f

OSC

÷ 12

TR1

Control

TH1

(8 bits)

TF1 Interrupt

AI06624

57/152

UPSD3212C, UPSD3212CV

STANDARD SERIAL INTERFACE (UART)

The uPSD321X Devices provides two standard
8032 UART serial ports. The first port is connected
to pin P3.0 (RX) and P3.1 (TX). The second port is
connected to pin P1.2 (RX) and P1.3(TX). The op­eration of the two serial ports are the same and are
controlled by the SCON and SCON2 registers.

The serial port is full duplex, meaning it can trans­mit and receive simultaneously. I t is also receive­buffered, meaning it can commence reception of a
second byte before a previously received byte has
been read from the register. (However, if the first
byte still has not been read by the time reception
of the second byte is complete, one of the bytes
will be lost.) The serial por t receive and transmit
registers are both accessed at Special Function
Register SBUF (or SBUF2 for the second serial
port). Writing to SBUF load s the t rans mit registe r,
and reading SBUF accesses a physically separate
receive register.

The serial port can operate in 4 modes:
Mode 0. Serial data enters and exits through

RxD. TxD outputs the shift clock. 8 bits are trans­mitted/received (LSB first). The b aud rate is f ixed
at 1/12 the f

Mode 1. 10 bits are transmitted (through TxD) or
received (through RxD): a start B it (0), 8 data bits
(LSB first), and a Stop Bit (1). On receive, t he Stop
Bit goes into RB8 in Special Function Register
SCON. The baud rate is variable.

Mode 2. 11 bits are transmitted (through TxD) or
received (through RxD): start Bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a
Stop Bit (1). On T rans m it, the 9th data bit (TB8 in
SCON) can be assigned the value of '0' or '1.' Or,
for example, the Parity Bit (P, in the PSW) could
be moved into TB8. O n receive, the 9th data bit
goes into RB8 in Special Function Register SCON,
while the Stop Bit is ignored. The baud rate is pro­grammable to either 1/32 or 1/64 the oscillator fre­quency.

OSC

.

Mode 3. 11 bits are transmitted (through TxD) or
received (through RxD): a Start Bit (0), 8 data bits
(LSB first), a programmable 9th data bit, and a
Stop Bit (1). In fac t, Mode 3 is the same as M ode
2 in all respects except baud rate. Th e baud rate
in Mode 3 is variable.

In all four modes, transmission is init iated by any
instruction that uses SBUF as a d es tination regis­ter. Reception is initiated in Mode 0 by the condi­tion RI = 0 and REN = 1. Reception is initiated in
the other modes by the incoming start bit if REN =

1.

Multiprocessor Communicati ons

Modes 2 and 3 have a s pecia l prov ision for m ulti­processor communications. In these modes, 9
data bits are received. The 9th one goes into RB8.
Then comes a Stop Bit. The port can be pro­grammed such that when the Stop Bit is received,
the serial port interrupt will be activated only if RB8
= 1. This feature is enabled by setting Bit SM2 in
SCON. A way to use this feature in mul ti-proces­sor systems is as follows:

When the master processor wants to transmit a
block of data to one of several slaves, it first sends
out an address byte which identifies the target
slave. An address byte differs from a data by te in
that the 9th bit is '1' in an ad dres s by te and 0 in a
data byte. With SM2 = 1, no s lave wi ll be interrupt­ed by a data byte. An ad-dress byte, however, will
interrupt all slaves, so that each s lave can e xam­ine the received byte and see if it is being ad­dressed. The addressed slave will clear its SM2
Bit and prepare to receive the d ata bytes that wi ll
be coming. The slaves that weren’t being ad­dressed leave their SM2s set and go on about
their business, ignoring the coming data bytes.

SM2 has no ef fect in Mode 0, and in Mode 1 can
be used to check the validity of the Stop B it. In a
Mode 1 reception, if SM2 = 1, the Receive In ter­rupt w ill not be ac t iv a te d un less a va lid S top Bit is
received.

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Serial Port Control Register

The serial port control and status register is the
Special Function Register SCON (SCON2 f or the
second port), shown in Figure 27. This register
(see Tables 43 and 44) contains not only the mode

Figure 27. Serial Port Mode 0, Block Diagram

Internal Bus

Write

to

SBUF

DS

CL

Q

SBUF

Zero Detector

UPSD3212C, UPSD3212CV

selection bits, but also the 9th data bit for transmit
and receive (TB8 and RB8), and the Serial Port In­terrupt Bits (TI and RI).

RxD
P3.0 Alt
Output
Function

Shift

Send

Receive

Shift

Shift

Shift

Clock

RxD
P3.0 Alt
Input
Function

TxD
P3.1 Alt
Output
Function

AI06824

S6

REN

R1

Serial

Port

Interrupt

Start
Tx Clock

Rx Clock

Start

Load

SBUF

Read

SBUF

Tx Control

T

R

Rx Control

7 6 5 4 3 2 1 0

Input Shift Register

SBUF

Internal Bus

Table 43. Serial Port Control Register (SCON)

76543210

SM0 SM1 SM2 REN TB8 RB8 TI RI

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UPSD3212C, UPSD3212CV

Table 44. Description of the SCON Bits

Bit Symbol Function

7 SM0 (SM1,SM0)=(0,0): Shift Register. Baud rate = f

(SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable

6SM1

(SM1,SM0)=(0,1): 8-bit UART. Baud rate = f
(SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable

OSC

Enables the multiprocessor communication features in Mode 2 and 3. In Mode 2 or 3, if

5SM2

SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8) is '0.' In Mode
1, if SM2=1, RI will not be activated if a valid Stop Bit was not received. In Mode 0, SM2
should be '0'

4REN

3TB8

2RB8

Enables serial reception. Set by software to enable reception. Clear by software to
disable reception

The 8th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as
desired

In Modes 2 and 3, this bit contains the 8th data bit that was received. In Mode 1, if
SM2=0, RB8 is the Snap Bit that was received. In Mode 0, RB8 is not used

Transmit Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or at

1TI

the beginning of the Stop Bit in the other modes, in any serial transmission. Must be
cleared by software

Receive Interrupt Flag. Set by hardware at the end of the 8th bit time in Mode 0, or

0RI

halfway through the Stop Bit in the other modes, in any serial reception (except for
SM2). Must be cleared by software

OSC

/64 or f

/12

OSC

/32

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UPSD3212C, UPSD3212CV

Baud Rates. The baud rate in Mode 0 is fixed:

Mode 0 Baud Rate = f

OSC

/ 12

The baud rate in Mode 2 depends on the value of
Bit SMOD = 0 (which is the value on res et), the
baud rate is 1/64 the oscillator frequency. If SMOD
= 1, the baud rate is 1/32 the oscillator frequency.

SMOD

Mode 2 Baud Rate = (2

/ 64) x f

OSC

In the uPSD321X Devices, the baud rates in
Modes 1 and 3 are determined by the Timer 1
overflow rate.

Using Timer 1 to Generate Baud Ra te s. When
Timer 1 is used as the baud rate generator, the
baud rates in Modes 1 and 3 a re determined by
the Timer 1 overflow rate and the value of SMOD
as follows (see Table 45, page 62):

Mode 1,3 Baud Rate =

SMOD

(2

/ 32) x (Timer 1 overflow rate)

The Timer 1 Interrupt should be disabled in this
application. The Timer itself can be c onf igured for
either “timer” or “counter” operation, and in any of
its 3 running modes. In the m ost typical applica­tions, it is configured for “timer” operation, in the
Auto-reload Mode (high nibble of TMOD = 0010B).
In that case the baud rate is given by the formula:

Mode 1,3 Baud Rate =

SMOD

(2

/ 32) x (f

/ (12 x [256 – (TH1)]))

OSC

One can achieve very low baud rates with Timer 1
by leaving the Timer 1 Interrupt enabled, and con­figuring the Timer to run as a 16-bit t imer (high nib­ble of TMOD = 0001B), and using the Timer 1
Interrupt to do a 16-bit software reload. Figure 22
lists various commonly used baud rates and how
they can be obtained from Timer 1.

Using Timer/Counter 2 to Generate Baud
Rates. In the uPSD321X Devices, Timer 2 select-

ed as the baud rate generator by setting TCLK
and/or RCLK (see Figure 22, page 53 Timer/
Counter 2 Control Register (T2CON)).

Note: The baud rate for transmit and receive c an
be simultaneously different. S etting RCLK and/or
TCLK puts Timer into its Baud Rate Generator
Mode.

The RCLK and TCLK Bits in the T2CON register
configure UART 1. The RCLK1 and TCLK1 Bits in
the PCON register configure UART 2.

The Baud Rate Generator Mode is similar to the
Auto-reload Mode, in that a roll over in TH2 causes
the Timer 2 registers to be reloaded with the 16-bit
value in registers RCAP2H and RCAP2L, which
are preset by software.

Now, the baud rates in Modes 1 and 3 are deter­mined at Timer 2’s overflow rate as follows:

Mode 1,3 Baud Rate = Timer 2 Overflow Rate / 16
The timer can be configured for either “timer” or

“counter” operation. In the most typical applica­tions, it is configured for “timer” operation (C/T2 =

0). “Timer” operation is a little different for Timer 2
when it’s being used as a baud rate generator.
Normally, as a timer it would increment every ma­chine cycle (thus at the 1/6 the CPU clock frequen­cy). In the case, the baud rate is given by the
formula:

Mode 1,3 Baud Rate = f

/ (32 x [65536 -

OSC

(RCAP2H, RCAP2L)]
where (RCAP2H, RCAP2L) is the content of

RC2H and RC2L taken as a 16-bit unsigned inte­ger.

Timer 2 also be used as the Baud Rate Generating
Mode. This mode is valid only if RCLK + TCLK = 1
in T2CON or in PCON.

Note: A roll-over in TH2 does not set TF2, and will
not generate an interrupt. Therefore, the Timer in­terrupt does not have to be disabled when Timer 2
is in the Baud Rate Generator Mode.

Note: If EXEN2 is set, a 1-to-0 transition in T2EX
will set EXF2 but will not cause a reload from
(RCAP2H, RCAP2L) to (TH2, TL2). Thus when
Timer 2 is in use as a baud rate gene rator, T2EX
can be used as an extra external interrupt, if de­sired.

It should be noted that when Timer 2 is running
(TR2 = 1) in “timer” function in the Baud Rate Gen­erator Mode, one should not try to READ or
WRITE TH2 or TL2. Un der these conditions the
timer is being incremented every state time, and
the results of a READ or WRITE may not be accu­rate. The RC registers may be read, but should not
be written to, because a WRITE might overlap a
reload and cause WRITE and/or reload errors.
Turn the timer off (clear TR2) before accessing the
Timer 2 or RC registers, in this case.

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UPSD3212C, UPSD3212CV

Table 45. Timer 1-Generated Commonly Used Baud Rates

Baud Rate

Mode 0 Max: 1MHz 12MHz X X X X

Mode 2 Max: 375K 12MHz 1 X X X

Modes 1, 3: 62.5K 12MHz 1 0 2 FFh

19.2K 11.059MHz 1 0 2 FDh

9.6K 11.059MHz 0 0 2 FDh

4.8K 11.059MHz 0 0 2 FAh

2.4K 11.059MHz 0 0 2 F4h

1.2K 11.059MHz 0 0 2 E8h

137.5 11.059MHz 0 0 2 1Dh
110 6MHz 0 0 2 72h
110 12MHz 0 0 1 FEEBh

f

OSC

SMOD Timer 1

C/T Mode Reload Value

More Abo ut Mode 0. Serial data enters and exits

through RxD. TxD outputs the shift clock. 8 bits are
transmitted/received: 8 data bits (LSB first). The
baud rate is fixed at 1/12 the f

OSC

.

Figure 27, page 59 shows a simplified functional
diagram of the serial port in Mode 0, and associat­ed timing.

Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal at S6P2 also loads a '1' into the
9th position of the tra nsmit shift register and t ells
the TX Control block to commence a transmission.
The internal timing is such that one f ull machine
cycle will e lapse bet ween “WR ITE to SBUF ” and
activation of SEND.

SEND enables the output of the shift register to the
alternate out-put function line of RxD and also en­able SHIFT CLOCK to the alternate output func­tion line o f TxD. SHI FT CLOC K is low during S3,
S4, and S5 of every m achine c ycle, a nd hig h dur­ing S6, S1, and S2. At S6P2 of every machine cy­cle in which SEND is active, the contents of t he
transmit shift are shifted to the right one position.

As data bits shift out to the right, zeros come in
from the left. When the MS B o f the da ta b yte is at
the output position of the shift register, then the '1'
that was initially loaded into the 9th position, is just

to the left of the MSB, and all positions to the left
of that contain zeros. This condition flags the TX
Control block to do one last shift and then dea cti­vate SEND and set T1. Both of these actions occur
at S1P1. Both of these actions occur at S1P1 of
the 10th machine cycle after “WRITE to SBUF.”

Reception is initiated by the condition REN = 1 and
R1 = 0. At S6P2 of the next machi ne cycle, the RX
Control unit writes the bits 11111110 to the receive
shift register, and in the next clock phase activates
RECEIVE.

RECEIVE enables SHIFT CLOCK to the alternate
output function line of TxD. SHIFT CLOCK makes
transitions at S3P1 and S6P1 of every machine
cycle in which RECEIVE is active, the co ntents of
the receive shift register are shifted to the left one
position. The value that comes in from t he right is
the value that was sampled at the RxD pin at S5P2
of the same machine cycle.

As data bits come in from the right, '1s' shift out to
the left. When the '0' that was initially loaded into
the right-most position arrives at the left-most po­sition in the shift register, it flags the RX Control
block to do one last shift and load SBUF. At S1P1
of the 10th machine cycle after the WRITE to
SCON that cleared RI, RECEIVE is cleared as RI
is set.

62/152

Figure 28. Serial Port Mode 0, Waveform s

UPSD3212C, UPSD3212CV

Write to SBUF

Send

Shift

RxD (Data Out)

TxD (Shift Clock)

T

Write to SCON

RI

Receive

Shift

RxD (Data In)

TxD (Shift Clock)

S6P2

D0 D1 D2 D3 D4 D5 D6 D7

S3P1 S6P1

Clear RI

D0 D1 D2 D3 D4 D5 D6 D7

More Abo ut Mode 1. Ten bits are transmitted
(through TxD), or received (through RxD): a start
Bit (0), 8 data bits (LSB first). and a Stop Bit (1). On
receive, the Stop Bit goes into RB8 in SCON. In
the uPSD321X Devices the baud rate is deter­mined by the Timer 1 or Timer 2 overflow rate.

Figure 29, page 64 shows a simplified functional
diagram of the serial port in Mode 1, and associat­ed timings for transmit receive.

Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal also loads a '1' into the 9th bit po­sition of the transmit shift register and flags the TX
Control unit that a transmission is requested.
Transmission actually comm ences at S1P1 of the
machine cycle following the next rollover in the di­vide-by-16 counter. (Thus, the bit times are syn­chronized to the divide-by-16 counter, not to the
“WRITE to SBUF” signal.)

The transmission begins wi th activation of SEND
which puts the start bit at TxD. One bit time l ater,
DATA is activated, which enables the output bit of
the transmit shift register to TxD. The first shift
pulse occurs one bit time after that.

As data bits shift out to the right, zeros are clocked
in from the left (see Figure 30, page 64). When the
MSB of the data byte is at the output position of the
shift regis ter, then the '1' tha t was initiall y loaded
into the 9th position is just to the left of the MSB,
and all positions to the left of that contain zeros.
This condition flags the TX Control unit t o do one
last shift and then deactivate SEND and set TI.
This occurs at the 10th divide-by-16 rollover after
“WRITE to SBUF.”

Reception is initiated by a detected 1-to-0 transi­tion at RxD. For this purpose RxD is sampled at a

Transmit

Receive

AI06825

rate of 16 times what ev er ba ud rat e has been es­tablished. When a transition is detected, the di­vide-by-16 counter is immediately reset, and 1FFH
is written into the input shift register. Resetting the
divide-by-16 counter aligns its roll-overs with the
boundaries of the incoming bit times.

The 16 states of the counter divide each bit time
into 16ths. At the 7 th, 8th, an d 9th counter sta tes
of each bit time, the bit detector samples the value
of RxD. The value accepted is the value that was
seen in at least 2 of the 3 samples. This is done for
noise rejection. If the value accepted during the
first bit time is not '0,' the receive circuits are reset
and the unit goes back to looking for an-other 1-to­0 transition. This is to provide rejection of false
start bits. If the start bit proves valid, it is shifted
into the input shift register, and reception of the re­set of the rest of the frame will proceed.

As data bits come in from the right, '1s' shift out to
the left. When the start bit arrives at the left-most
position in the shift register (which in Mode 1 is a
9-bit register), it flags the RX Control block to do
one last shift, load SBUF and RB8, and set RI. The
signal to load SBUF and RB8, and to set RI, will be
generated if, and only if, the following conditions
are met at the time the final shift pulse is generat­ed:

1. R1 = 0, and

2. Either SM2 = 0, or the received Stop Bit = 1.
If either of these two conditions is not m et, the re-

ceived frame is irretrievably lost. If both conditions
are met, the Stop Bit goes into RB8, the 8 data bits
go into SBUF, and RI is activated. At this time,
whether the above condi tions are met or not, the
unit goes back to looking f or a 1-to-0 t ransition in
RxD.

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UPSD3212C, UPSD3212CV

Figure 29. Serial Port Mode 1, Block Diagram

SMOD

TCLK

RCLK

Timer1

Overflow

÷2

01

Timer2

Overflow

01

0

1

Write

to

SBUF

RxD

Sample

1-to-0

Transition

Detector

÷16

Serial

Port

Interrupt

Rx Detector

TB8

DS

CL

Q

Start

Tx Clock

÷16

Rx Clock

Start

Load

SBUF

Internal Bus

SBUF

Zero Detector

Tx Control

TI

RI

Rx Control

1FFh

Input Shift Register

Shift

Send

Load SBUF

TxD

Data

Shift

Shift

Figure 30. Serial Port Mode 1, Waveform s

Tx Clock

Write to SBUF

Send

Data

Shift

TxD

T1

Rx Clock

RxD

Bit Detector

Sample Times

Shift

RI

S1P1

Start Bit

÷16 Reset

Start Bit

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

Read

SBUF

SBUF

Internal Bus

Stop Bit

Stop Bit

AI06826

Transmit

Receive

AI06843

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UPSD3212C, UPSD3212CV

More About Modes 2 and 3. Eleven bits are

transmitted (through TxD), or received (through
RxD): a Start Bit (0), 8 data bits (LSB first), a pro­grammable 9th data bit, and a Stop Bit (1). On
transmit, the 9th data b it (TB8) can be assigned
the value of '0' or '1.' On receive, the data bit goes
into RB8 in SCON. The baud rate is programma­ble to either 1/16 or 1/32 the CPU clock frequency
in Mode 2. Mode 3 may have a variable baud rate
generated from Timer 1.

Figure 31, page 66 a nd Figure 33, p age 67 show
a functional diagram of the s erial port in Modes 2
and 3. The receive portion is exactly the same as
in Mode 1. The transmit portion di ffers from M ode
1 only in the 9th bit of the transmit shift register.

Transmission is initiated by any instruction that
uses SBUF as a destination register. The “WRITE
to SBUF” signal also loads TB8 into the 9th bit po­sition of the transmit shift register and flags the TX
Control unit that a transmission is requested.
Transmission commences at S1P1 of the machine
cycle following the next roll-over i n the divide-by­16 counter. (Thus, the bit t imes are s ynchronized
to the divide-by-16 counter, not to the “WRITE to
SBUF” signal.)

The transmission begins with activation of S END,
which puts the start bit at TxD. One bit time l ater,
DATA is activated, which enables the output bit of
the transmit shift register to TxD. The first shift
pulse occurs one bit time after that (see Figure 32,
page 66 and Figure 34, page 67). The first shift
clocks a '1' (the Stop Bit) into the 9th bit position of
the shift register. There-after, only zeros are
clocked in. Thus, as data bits shift out to the right,
zeros are clocked in from the l eft. When TB8 is at
the out-put position of the shift register, then the
Stop Bit is just to the left of TB8, and all positions
to the left of that contain zeros. This condition flags
the TX Control unit to do one last shift and then de-

activate SEND and set TI. This occurs at the 11th
divide-by 16 rollover after “WRITE to SUBF.”

Reception is initiated by a detected 1-to-0 transi­tion at RxD. For this purpose RxD is sampled at a
rate of 16 times what ev er ba ud rat e has been es­tablished. When a transition is detected, the di­vide-by-16 counter is immediately reset, and 1FFH
is written to the input shift register.

At the 7th, 8th, and 9th counter sta tes of each bit
time, the bit detector sam ples the value of R -D.
The value accepted is the value that was seen in
at least 2 of the 3 samples. If the value accepted
during the first bit time is not '0,' the receive circuits
are reset and the unit goes back to looking for an­other 1-to-0 transition. If the Start Bit proves valid,
it is shifted into the input shi ft regi ster, and recep­tion of the rest of the frame will proceed.

As data bits come in from the right, '1s' shift out to
the left. When the Start Bit arrives at the l eft-m ost
position in the shift register (which in Modes 2 and
3 is a 9-bit register), it flags the RX Control block
to do one last shift, load SBUF and RB8, and set
RI.

The signal to load SBUF a nd RB8, a nd to set RI,
will be generated if, and only if, the following con­ditions are met at th e time the final shift pul se is
generated:

1. RI = 0, and

2. Either SM2 = 0, or the received 9th data bit = 1
If either of these conditions is not met, the received

frame is irretrievably lost, and RI is not set. If both
conditions are met, the recei ve d 9t h data bit goes
into RB8, and the first 8 data bits go into SBUF.
One bit time later, whether the above conditions
were met or not, the unit goes bac k to looking for
a 1-to-0 transition at the RxD input.

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UPSD3212C, UPSD3212CV

Figure 31. Serial Port Mode 2, Block Diagram

Phase2 Clock

1/2*f

OSC

÷2

SMOD

01

Write

to

SBUF

RxD

Sample

1-to-0

Transition

Detector

÷16

Serial

Port

Interrupt

Rx Detector

TB8

DS

CL

Q

Start

Tx Clock

÷16

Rx Clock

Start

Load

SBUF

Internal Bus

SBUF

Zero Detector

Tx Control

TI

RI

Rx Control

1FFh

Input Shift Register

Shift

Send

Load SBUF

TxD

Data

Shift

Shift

Figure 32. Serial Port Mode 2, Waveform s

Tx Clock

Write to SBUF

Send

Data

Shift

TxD

Stop Bit

Generator

Rx Clock

RxD

Bit Detector

Sample Times

Shift

TI

RI

S1P1

Start Bit

÷16 Reset

Start Bit

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

Read

SBUF

SBUF

Internal Bus

TB8

RB8

Stop Bit

Stop Bit

AI06844

Transmit

Receive

AI06845

66/152

Figure 33. Serial Port Mode 3, Block Diagram

UPSD3212C, UPSD3212CV

SMOD

TCLK

RCLK

Timer1

Overflow

÷2

01

Timer2

Overflow

01

0

1

Write

to

SBUF

RxD

Sample

1-to-0

Transition

Detector

÷16

Serial

Port

Interrupt

Rx Detector

TB8

DS

CL

Q

Start

Tx Clock

÷16

Rx Clock

Start

Load

SBUF

Internal Bus

SBUF

Zero Detector

Tx Control

TI

RI

Rx Control

1FFh

Input Shift Register

Shift

Send

Load SBUF

TxD

Data

Shift

Shift

Figure 34. Serial Port Mode 3, Waveform s

Tx Clock

Write to SBUF

Send

Data

Shift

TxD

Stop Bit

Generator

Rx Clock

RxD

Bit Detector

Sample Times

Shift

TI

RI

S1P1

Start Bit

÷16 Reset

Start Bit

D0 D1 D2 D3 D4 D5 D6 D7

D0 D1 D2 D3 D4 D5 D6 D7

Read

SBUF

SBUF

Internal Bus

TB8

RB8

Stop Bit

Stop Bit

AI06846

Transmit

Receive

AI06847

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UPSD3212C, UPSD3212CV

ANALOG-TO-DIGITAL CONVERTOR (ADC)

The analog to digital (A/D ) converter allows con­version of an analog input to a corresponding 8-bit
digital value. The A/D module has f our analog in­puts, which are multiplexed into one sample and
hold. The output of the sample and hold is the in­put into the converter, which generates the result
via successive approximation. The analog supply
voltage is connected to AVREF of ladder resis­tance of A/D module.

The A/D module has two regi sters which are the
control register ACON and A/D result register
ADAT. The register ACON, shown in Table 46 and
Table 47, page 69, controls the operation of the A/
D converter module. To use analog inputs, I/O is
selected by P1SFS register. Also an 8-bit prescal­er ASCL divides the main system clock input down
to approximately 6MHz clock that is required for
the ADC logic. Appropriate values need to be load­ed into the prescal er based upon the mai n MCU
clock frequency prior to use.

The processing of conversion starts when the
Start Bit ADST is set to '1.' After one cycle, it is
cleared by hardware. The register AD AT cont ains
the results of the A/D conversion. When conver­sion is completed, the result is loaded into the
ADAT the A/D Conversion Status Bit ADSF is set
to '1.'

The block diagram of the A/D module is shown in
Figure 35. The A/D Status Bit ADSF is set auto-

matically when A/D conversion is completed,
cleared when A/D conversion is in process.

The ASCL should be loaded with a value that re­sults in a clock rate of approximately 6MHz for the
ADC using the following formula (see Table 48,
page 69):

ADC clock input = (f

/ 2) / (Prescaler register

OSC

value +1)
Where f

is the MCU clock input frequency

OSC

The conversion time f or the ADC can be c alcula t­ed as follows:

ADC Conversion Time = 8 clock * 8bits * (ADC
Clock) ~= 10.67usec (at 6MHz)

ADC Interrupt

The ADSF Bit in the ACON register is set to '1'
when the A/D conversion is complete. The status
bit can be driven by the MCU, or it can be config­ured to generate a falling e dge i nterrupt when t he
conversion is complete.

The ADSF Interrupt is enabled by setting the ADS­FINT Bit in the PCON register. Once the bit is set,
the external INT1 Interrupt is disabled and the
ADSF Interrupt takes over as INT1. INT1 must be
configured as if it is an edge interrupt input. The
INP1 pin (p3.3) is available for gene ral I/O func­tions, or Timer1 gate control.

Figure 35. A/D Block Diagram

AVREF

ACH0
ACH1
ACH2

ACH3

ACON

Input

MUX

S/H

Ladder

Resistor

Decode

INTERNAL BUS

Successive

Approximation

Circuit

Conversion

Complete

Interrupt

ADAT

AI06627

68/152

UPSD3212C, UPSD3212CV

Table 46. ADC SFR Memory Map

SFR

Addr

Reg

Name

95 ASCL 00

76543210

Bit Register Name

Reset
Value

Comments

8-bit

Prescaler for

ADC clock

96 ADAT ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2 ADAT1 ADAT0 00

97 ACON ADEN ADS1 ADS0 ADST ADSF 00

Table 47. Description of the ACON Bits

Bit Symbol Function

7 to 6 — Reserved

5

4 — Reserved

3 to 2

1

0

ADEN ADC Enable Bit: 0 : ADC shut off and consumes no operating current

1 : enable ADC

ADS1, ADS0 Analog channel select

0, 0 Channel0 (ACH0)
0, 1 Channel1 (ACH1)
1, 0 Channel2 (ACH2)
1, 1 Channel3 (ACH3)

ADST ADC Start Bit: 0 : force to zero

1 : start an ADC; after one cycle, bit is cleared to '0'

ADSF ADC Status Bit: 0 : A/D conversion is in process

1 : A/D conversion is completed, not in process

ADC Data

Register

ADC Control

Register

Table 48. ADC Clock Input

MCU Clock Frequency Prescaler Register Value ADC Clock

40MHz 2 6.7MHz
36MHz 2 6MHz
24MHz 1 6MHz
12MHz 0 6MHz

69/152

UPSD3212C, UPSD3212CV

PULSE WIDTH MODULATION (PWM)

The PWM block has the following features:

■ Four-channel, 8-bit PWM unit with 16-bit

prescaler

■ One-channel, 8-bit unit with programmable

frequency and pulse width

■ PWM Output with programmable polarity

4-channel PWM Unit (PWM 0-3)

The 8-bit counter of a PWM counts modul e 256
(i.e., from 0 to 255, inclusive). The valu e held in
the 8-bit counter is compared to the contents of the
Special Function Register (PWM 0-3) of the corre­sponding PWM. T he pola rity of t he P WM o utputs
is programmable and selected by the PWML Bit in
PWMCON register. Provided the contents of a
PWM 0-3 register is greater than the counter val­ue, the corresponding PWM output is set HIGH
(with PWML = 0). When the contents of this regis­ter is less than or equal to the counter value, the
corresponding PWM output is set LOW (with
PWML = 0). The pulse-width-ratio is therefore de-

fined by the contents of the corresponding Special
Function Register (PWM 0-3) o f a PWM . By l oad­ing the corresponding Special Function Register
(PWM 0-3) with either 00H or FFH, the P WM ou t­put can be ret ained at a c onstant HIGH o r LOW
level respectively (with PWML = 0).

For each PWM unit, there is a 16-bit Prescaler that
are used to divide the main syste m clock to form
the input clock for the correspondi ng PWM unit.
This prescaler is used to define the desired repeti­tion rate for the PWM unit. SFR registers B1h ­B2h are used to hold the 16-bit divisor values.

The repetition frequency of the PWM output is giv­en by:

fPWM

= (f

8

/ prescaler0) / (2 x 256)

OSC

And the input clock frequency to the PWM
counters is = f

/ 2 / (prescaler data value + 1)

OSC

See the I/O PORTS (MCU Module), page 44 for
more information on how to configure the Port 4
pin as PWM output.

70/152

Figure 36. Four-Channel 8-bit PWM Block Diagram

DATA BUS

UPSD3212C, UPSD3212CV

f

OSC

CPU rd/wr

/2

8

CPU rd/wr

8

16-bit Prescaler

Register

(B2h,B1h)

16

16-bit Prescaler

Counter

8-bit PWM0-PWM3

8-bit PWM0-PWM3

Comparators Registers

8-bit PWM0-PWM3

clock

8

Data Registers

8

x 4

8

x 4

Comparators

8

8-bit Counter

Overflow

x 4

load

4

PWMCON bit7 (PWML)

Port4.3
Port4.4
Port4.5
Port4.6

load

PWMCON bit5 (PWME)

AI06647

71/152

UPSD3212C, UPSD3212CV

Table 49. PWM SFR Memory Map

SFR

Reg Name

Addr

A1 PWMCON PWML PWMP PWME CFG4 CFG3 CFG2 CFG1 CFG0 00

76543210

Bit Register Name

Reset

Value

Comments

PWM

Control

Polarity

A2 PWM0 00

A3 PWM1 00

A4 PWM2 00

A5 PWM3 00

AA PWM4P 00

AB PWM4W 00

B1 PSCL0L 00

B2 PSCL 0H 00

B3 PSCL 1L 00

B4 PSCL 1H 00

PWM0
Output

Duty Cycle

PWM1
Output

Duty Cycle

PWM2
Output

Duty Cycle

PWM3
Output

Duty Cycle

PWM 4

Period

PWM 4

Pulse
Width

Prescaler 0

Low (8-bit)

Prescaler 0
High (8-bit)

Prescaler 1

Low (8-bit)

Prescaler 1
High (8-bit)

PWMCON Register Bit Definition:
– PWML = PWM 0-3 polarity control
– PWMP = PWM 4 polarity control
– PWME = PWM enable (0 = disabled , 1= enabled)
– CFG3..CFG0 = PW M 0-3 Output (0 = Open Drain; 1 = Push-Pull)
– CFG4 = PWM 4 Output (0 = Open Drain; 1 = Push-Pull)

72/152

Programm able Period 8-bi t PWM

The PWM 4 chan nel can be program med to pro­vide a PWM output with variable pulse wi dth and
period. The PWM 4 has a 16-bi t Prescaler, an 8­bit Counter, a Pulse Width Register, a nd a Pe riod

PWM pulse width time, while the Period Regi ster
defines the period of the P WM . The input clock t o
the Prescaler is f
signed to Port 4.7.

Register. The Pulse Width Register defines the

Figure 37. Programmable PWM 4 Channel Block Diagram

DATA BUS

8

8

UPSD3212C, UPSD3212CV

/2. The PWM 4 channel is as-

OSC

8

f

OSC

CPU RD/WR

/ 2

PWMCON

Bit 5 (PWME)

8

16-bit Prescaler

Register

(B4h, B3h)

16

16-bit Prescaler

Counter

Load

CPU RD/WR

8-bit PWM4P

Register

(Period)

8

8-bit PWM4
Comparator

Register

8

8-bit PWM4
Comparator

88

PWM4
Control

Match

8-bit Counter

Clock

8-bit PWM4W

8-bit PWM4
Comparator

8-bit PWM4
Comparator

Reset

Register

(Width)

8

Load

Register

8

PWMCON

Bit 6 (PWMP)

Port 4.7

AI07091

73/152

UPSD3212C, UPSD3212CV

PWM 4 Channel Operation

The 16-bit Prescaler1 divides the input clock

/2) to the desired frequency, the resulting

(f

OSC

clock runs the 8-bit Counter of the PWM 4 chan­nel. The input clock frequency to the PWM 4
Counter is:

f PWM 4 = (f

/2)/(Prescaler1 data value +1)

OSC

When the Prescaler1 Register (B4h, B3h) is set to
data value '0,' the maximum input clock frequency
to the PWM 4 Counter is f

/2 and can be as high

OSC

as 20MHz.
The PWM 4 Counter is a free-running, 8-bit

counter. The output of the counter is com pared t o
the Compare Registers, which are loaded with
data from the Pulse Width Register (PWM4W,
ABh) and the Period Register (PWM4P, AAh). The
Pulse Width Register defines the pulse duration or
the Pulse Width, while the Period Register defines
the period of the PWM. When the PWM 4 channel
is enabled, the register val ues are l oaded into the
Comparator Registers and are compared to the

Figure 38. PW M 4 Wi th P r og ra mm a b le P ul s e W i dth a n d Fre q ue n c y

Counter output. When the content of the counter is
equal to or greater than the value in the Pulse
Width Register, it sets t he PWM 4 output to low
(with PWMP Bit = 0). When the Period Register
equals to the PWM4 Counter, the Counter is
cleared, and the PWM 4 channel output is set to
logic 'high' level (beginning of the next PWM
pulse).

The Period Register cannot have a value of “00”
and its content should always be greater than the
Pulse Width Register.

The Prescaler1 Register, Pulse Width Register,
and Period Register can be modified while the
PWM 4 channel is active. The values of these reg­isters are automatically loaded into the Prescaler
Counter and Comparator Registers when the cur­rent PWM 4 period ends.

The PWMCON Register (Bits 5 and 6) controls the
enable/disable and polarity of the PWM 4 channel.

PWM4

Defined by Pulse

Width Register

Defined by Period Register

Switch Level

RESET
Counter

AI07090

74/152

UPSD3212C, UPSD3212CV

I2C INTERFACE

2

The serial port supports the twin line I

C-bus, con­sisting of a data line (SDA1), and a clock line
(SCL1) as shown in Figure 39. Dep ending on the
configuration, the SD A1 and SCL1 l ines may re­quire pull-up resistors.

These lines also function as I/O port lines if the I

2

bus is not enabled.
The system is unique because data transport,

clock generation, address recognition, and bus
control arbitration are all controlled by hardware.

2

C serial I/O has complete a uto nom y in byte

The I
handling and operates in 4 modes.

■ Master transmitter

2

Figure 39. Block Diagram of the I

SDA1

C Bus Serial I/O

70

70

Arbitration and Sync. Logic

■ Master receiver

■ Slave transmitter

■ Slave receiver

These functions are controlled by the S FRs (see

C

Tables 50, 51, and Table 52, page 76):
– S2CON: the control of byte handling and the op-

eration of 4 mode.

– S2STA: the content s of its register ma y a lso be

used as a vector to various service routines.
– S2DAT: data shift register.
– S2ADR: slave address register. Slave address

recognition is performed by On-Chip H/W.

Slave Address

Shift Register

Internal Bus

SCL1

Bus Clock Generator

70

Control Register

70

Status Register

AI07430

75/152

UPSD3212C, UPSD3212CV

Table 50. Serial Control Register (S2CON)

76543210

CR2 ENII STA STO ADDR AA CR1 CR0

Table 51. Description of the S2CON Bits

Bit Symbol Function

7CR2

6ENII

5STA

This bit along with Bits CR1and CR0 determines the serial clock frequency when SIO is
in the Master Mode.

Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high
impedance state.

2

START Flag. When this bit is set, the SIO H/W checks the status of the I

C-bus and
generates a START condition if the bus free. If the bus is busy, the SIO will generate a
repeated START condition when this bit is set.

STOP Flag. With this bit set while in Master Mode a STOP condition is generated.

2

4STO

Flag.

When a STOP condition is detected on the I

C bus, the I2C hardware clears the STO

Note: This bit have to be set before 1 cycle interrupt period of STOP. That is, if this bit is
set, STOP condition in Master Mode is generated after 1 cycle interrupt period.

3 ADDR This bit is set when address byte was received. Must be cleared by software.

Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:

• Own slave address is received

2AA

• A data byte is received while the device is programmed to be a Master Receiver

• A data byte is received while the device is a selected Slave Receiver. When this bit is
reset, no acknowledge is returned.
SIO release SDA line as high during the acknowledge clock pulse.

1CR1
0CR0

These two bits along with the CR2 Bit determine the serial clock frequency when SIO is
in the Master Mode.

Table 52. Selection of the Serial Clock Frequency SCL in Master Mode

Divisor

CR2 CR1 CR0

f

OSC

12MHz 24MHz 36MHz 40MHz

0 0 0 16 375 750 X X
0 0 1 24 250 500 750 833
0 1 0 30 200 400 600 666
0 1 1 60 100 200 300 333

Bit Rate (kHz) at f

OSC

1 0 0 120 50 100 150 166
1 0 1 240 25 50 75 83
1 1 0 480 12.5 25 37.5 41
1 1 1 960 6.25 12.5 18.75 20

76/152

UPSD3212C, UPSD3212CV

Serial Status Register (S2STA)

S2STA is a “Read-only” register. The contents of
this register may be used as a vector to a service
routine. This optimized the respons e time of the
software and consequently that of the I
status codes for all possible modes of the I

2

C bus. The

2

C bus

interface are given Table 54.
This flag is set, and an interrupt is generated, after

any of the following events occur:

1. Own slave address has been received during
AA = 1: ack_int

2. The general call address has been received
while GC(S2ADR.0) = 1 and AA = 1:

Table 53. Serial Status Register (S2STA)

76543210

GC STOP INTR TX_MODE BBUSY BLOST /ACK_REP SLV

Table 54. Description of the S2STA Bits

Bit Symbol Function

7 GC General Call Flag
6 STOP Stop Flag. This bit is set when a STOP condition is received

5

4 TX_MODE

3 BBUSY

2 BLOST

1 /ACK_REP

0SLV

Note: 1. Interrupt Flag Bit (I NTR, S2ST A Bit 5) is cleared by Hardware as reading S2STA register.

2

2. I

C Interrupt Flag (INTR) can occur in below case.

INTR

(1,2)

Interrupt Flag. This bit is set when an I²C Interrupt condition is requested
Transmission Mode Flag.

This bit is set when the I²C is a transmitter; otherwise this bit is reset
Bus Busy Flag.

This bit is set when the bus is being used by another master; otherwise, this bit is reset
Bus Lost Flag.

This bit is set when the master loses the bus contention; otherwise this bit is reset
Acknowledge Response Flag.

This bit is set when the receiver transmits the not acknowledge signal
This bit is reset when the receiver transmits the acknowledge signal

Slave Mode Flag.
This bit is set when the I²C plays role in the Slave Mode; otherwise this bit is reset

3. A data byte has been received or transmitted in
Master Mode (even if arbitration is lost): ack_int

4. A data byte has been received or transmitted as
selected slave: ack_int

5. A stop condi tion is received as selected slave
receiver or transmitter: stop_int

Data Shift Register (S2DAT)

S2DAT contains the serial data to b e transmitted
or data which has just been received. The M SB
(Bit 7) is transmitted or rec eived f irst; that is, data
shifted from right to left.

Table 55. Data Shift Register (S2DAT)

76543210

S2DAT7 S2DAT6 S2DAT5 S2DAT4 S2DAT3 S2DAT2 S2DAT1 S2DAT0

77/152

UPSD3212C, UPSD3212CV

Address Register (S2ADR)

2

This 8-bit register may be loaded with the 7-bit
slave address to which the controller will respond
when programmed as a slave receive/transmitter.

The Start/Stop Hold Time Detection and Sys tem

C unit to specify the start/stop detection time

the I
to work with the large range of MCU frequency val­ues supported. For example, with a system clock
of 40MHz.

Clock registers (Tables 57 and 58) are included in

Table 56. Address Register (S2ADR)

76543210

SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 —

Note: SLA6 to S LA 0: Own slave address.

Table 57. Start /Stop Hold Time Detection Register (S2SETUP)

Address Register Name Res et Value Note

SFR D2h S2SETUP 00h

To control the start/stop hold time detection for the multi-master
I²C module in Slave Mode

Table 58. System Cock of 40MHz

S1SETUP,

S2SETUP Register

Value

00h 1EA 50ns

Number of Sample

Clock (f

OSC

50ns)

/2 – >

Required Start/

Stop Hold Time

Note

When Bit 7 (enable bit) = 0, the number of

sample clock is 1EA (ignore Bit 6 to Bit 0)
80h 1EA 50ns
81h 2EA 100ns
82h 3EA 150ns

... ... ...

8Bh 12EA 600ns Fast Mode I²C Start/Stop hold time specification

... ... ...

FFh 128EA 6000ns

Table 59. System Clock Setup Examp les

S1SETUP,

System Clock

40MHz (f

30MHz (f

20MHz (f

8MHz (f

/2 – > 50ns)

OSC

/2 – > 66.6ns)

OSC

/2 – > 100ns)

OSC

/2 – > 250ns)

OSC

S2SETUP Register

Value

8Bh 12 EA 600ns
89h 9 EA 600ns
86h 6 EA 600ns
83h 3 EA 750ns

Number of Sample

Clock

Required Start/Stop Hold Time

78/152

PSD MODULE

■ The PSD Module provides configurable

Program and Data memories to the 8032 CPU
core (MCU). In addition, it has its own set of I/O
ports and a PLD with 16 macrocells for general
logic implementation.

■ Ports A,B,C, and D are general purpose

programmable I/O ports that have a port
architecture which is different from the I/O ports
in the MCU Module.

■ The PSD Module communicates with the MCU

Module through the internal address, data bus
(A0-A15, D0-D7) and control signals (RD
PSEN

, ALE, RESET). The user defines the

, WR,

Decoding PLD in the PSDsoft Development
Tool and can map the resources in the PSD
Module to any program or data address space.
Figure 40 shows the functional blocks in the
PSD Module.

Functional Overvie w

■ 512Kbit Flash mem ory. This is the main Flash

memory. It is divided into 4 sectors (16KBytes
each) that can be accessed with user-specified
addresses.

■ Secondary 128Kbit Flash boot memory. It is

divided into 2 sectors (8KBytes each) that can
be accessed with user-specified addresses.
This secondary m emo ry brings th e abilit y to
execute code and update the main Flash

concurrently.

■ 16Kbit SRAM. The SRAM’s contents can be

protected from a power failure by connecting an
external battery.

■ CPLD with 16 Output Micro Cells (OMCs) and

up to 20 Input Micro Cells (IMCs). The CPLD
may be used to efficiently implement a variety of
logic functions for internal and external control.

UPSD3212C, UPSD3212CV

Examples include state machines, loadable
shift registers, and loadable counters.

■ Decode PLD (DPLD) that decodes address for

selection of memory blocks in the PSD Module.

■ Configurable I/O ports (Port A,B,C and D) that

can be used for the following functions:
– MCU I/Os

–PLD I/Os
– Latched MCU address output
– Special function I/Os.
– I/O ports may be configured as open drain

outputs.

■ Built-in JTAG compliant serial port allows full-

chip, In-System Programmability (ISP). With it,
you can program a blank device or reprogram a
device in the factory or the field.

■ Internal page register that can be used to

expand the 8032 MCU Module address space
by a factor of 256.

■ Internal programmable Power Management

Unit (PMU) that supports a low-power mode
called Power-down Mode. The PMU can
automatically detect a lack of the 8032 CPU
core activity and put the PSD Mod ule into
Power-down Mode.

■ Erase/WRITE cycles:

– Flash memory - 100,000 minimum
– PLD - 1,000 minimum
– Data Retention: 15 year minimum (for Main

Flash memory, Boot , PLD a nd Configurat ion
bits)

79/152

UPSD3212C, UPSD3212CV

Figure 40. PSD MODULE Block Diagram

)

PC2

(

VSTDBY

PA0 – PA7

PB0 – PB7

PC0 – PC7

PD1 – PD2

ADDRESS/DATA/CONTROL BUS

POWER

8 SECTORS

FLASH MEMORY

512KBIT PRIMARY

EMBEDDED

ALGORITHM

PAGE

REGISTER

8

UNIT

MANGMT

2 SECTORS

(BOOT OR DATA)

128KBIT SECONDARY

NON-VOLATILE MEMORY

SECTOR

SELECTS

SECTOR

SELECTS

)

DPLD

(
PLD

FLASH DECODE

73

A

PORT

PORT

PROG.

BACKUP SRAM

16KBIT BATTERY

RUNTIME CONTROL

AND I/O REGISTERS

SRAM SELECT

PERIP I/O MODE SELECTS

CSIOP

B

PORT

PORT

PROG.

PORT A ,B & C

PORT A ,B & C

2 EXT CS TO PORT D

(CPLD)

FLASH ISP CPLD

73

20 INPUT MACROCELLS

16 OUTPUT MACROCELLS

CLKIN

C

PORT

PORT

PROG.

MACROCELL FEEDBACK OR PORT INPUT

CLKIN

PORT

PORT

PROG.

JTAG

SERIAL

& FLASH MEMORY

PLD, CONFIGURATION

D

CHANNEL

LOADER

80/152

8032 Bus

PLD

BUS

INPUT

WR_, RD_,

PSEN_, ALE,

RESET_,

A0-A15

BUS

Interface

BUS

Interface

D0 – D7

GLOBAL

SECURITY

CONFIG. &

CLKIN

(PD1)

AI07431

UPSD3212C, UPSD3212CV

In-Syst em Prog r a mmi ng ( ISP)

Using the JTAG signals on Port C, the entire PSD
MODULE device can be prog rammed or erased
without the use of the MCU. The primary Flash
memory can also be programmed in-system by
the MCU executing the programming algorithms
out of the secondary memory, or SRAM. The sec­ondary memory can be programmed the same

Tabl e 60. Methods of Program m ing Different Functional B l ocks of the PSD MODULE

Functional Block JTAG Programming Device Programmer IAP

Primary Flash Memory Yes Yes Yes
Secondary Flash Memory Yes Yes Yes
PLD Array (DPLD and CPLD) Yes Yes No
PSD MODULE Configuration Yes Yes No

way by executing out of t he pri mary F lash m em o­ry. The PLD or other PSD MODULE Configuration
blocks can be program med throu gh the JTAG p ort
or a device programmer. Table 60 indicates which
programming methods can program different func­tional blocks of th e PSD MODULE.

81/152

UPSD3212C, UPSD3212CV

DEVELOPMENT SYST EM

The uPSD3200 is supported by PSDsof t, a Win­dows-based software development tool (Win­dows-95, Windows-98, Windows-NT). A PSD
MODULE design is quickly and easily produced in
a point and click environment. The designer does
not need to enter Hardware Description Language
(HDL) equations, unless desired, to define PSD
MODULE pin functions and memory map informa­tion. The general design flow is shown in Figure

41. PSDsoft is available from our web site (t he ad-

Figure 41. PSDsoft Express Development Tool

Choose µPSD

Define µPSD Pin and

Node Functions

Point and click definition of

PSD pin functions, internal nodes,

and MCU system memory map

dress is given on the back page of this data sheet)
or other distribution channels.

PSDsoft directly supports a low cost device pro­grammer from ST: FlashLINK (JTAG). The pro­grammer may be purchased through your local
distributor/representative. The uP SD3200 is also
supported by third party device programmers. See
our web site for the current list.

Define General Purpose

Logic in CPLD

Point and click definition of combin­atorial and registered logic in CPLD.

Access HDL is available if needed

Merge MCU Firmware with

PSD Module Configuration

A composite object file is created

containing MCU firmware and

PSD configuration

*.OBJ FILE

PSD Programmer

FlashLINK (JTAG)

MCU FIRMWARE

HEX OR S-RECORD

FORMAT

*.OBJ FILE

AVAILABLE

FOR 3rd PARTY

PROGRAMMERS

C Code Generation

GENERATE C CODE

SPECIFIC TO PSD

FUNCTIONS

USER'S CHOICE OF

8032

COMPILER/LINKER

AI07432

82/152

UPSD3212C, UPSD3212CV

PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET

Table 61 shows the offset addresses to the PSD
MODULE registers relative to the CSIOP base ad­dress. The CSIOP space is the 256 bytes of ad­dress that is allocated by the user to the internal

Table 61. Register Address Offset

Register Name Port A Port B Port C Port D

Data In 00 01 10 11 Reads Port pin as input, MCU I/O Input Mode
Control 02 03 Selects mode between MCU I/O or Address Out

PSD MODULE registers. Table 61 provides brief
descriptions of the registers in CSIOP space. The
following section gives a more detailed descrip­tion.

Other

1

Description

Data Out 04 05 12 13

Direction 06 07 14 15 Configures Port pin as input or output

Drive Select 08 09 16 17

Input Macrocell 0A 0B 18 Reads Input Macrocells

Enable Out 0C 0D 1A 1B

Output Macrocells
AB

Output Macrocells
BC

Mask Macrocells AB 22 22 Blocks writing to the Output Macrocells AB
Mask Macrocells BC 23 23 Blocks writing to the Output Macrocells BC
Primary Flash

Protection
Secondary Flash

memory Protection
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register

20 20

21 21

C0 Read-only – Primary Flash Sector Protection

C2

Stores data for output to Port pins, MCU I/O
Output Mode

Configures Port pins as either CMOS or Open
Drain on some pins, while selecting high slew rate
on other pins.

Reads the status of the output enable to the I/O
Port driver

READ – reads output of macrocells AB
WRITE – loads macrocell flip-flops

READ – reads output of macrocells BC
WRITE – loads macrocell flip-flops

Read-only – PSD MODULE Security and
Secondary Flash memory Sector Protection

VM E2

Note: 1. Other registers that are not part of the I/O ports.

Places PSD MODULE memory areas in Program
and/or Data space on an individual basis.

83/152

UPSD3212C, UPSD3212CV

PSD MODULE DETAILED OPERATION

As shown in Figure 15, the PSD M ODULE con­sists of five major types of functional blocks:

■ Memory Block

■ PLD Blocks

■ I/O Ports

■ Power Management Unit (PMU)

■ JTAG Interface

The functions of ea ch block are described i n the
following sections. Many of the blocks perform
multiple functions, and are user configurable.

MEMORY BLOCKS

The PSD MODULE has the following memory
blocks:

■ Primary Flash memory

■ Secondary Flash memory

■ SRAM

The Memory Select signals for these blocks origi­nate from the Decode PLD (DPLD) an d are user­defined in PSDsoft Express.

Primary Flash Memory and Secon dary Flash memory Description

The primary Flash memory is divided into 4 sec­tors (16KBytes each). The secondary Flash mem­ory is divided into 2 sectors (8KBytes each). Each
sector of either memory block can be separately
protected from Program and Erase cycles.

Flash memory may be erased on a sector-by-sec­tor basis. Flash sector erasure may be suspended
while data is read from other sectors of the block
and then resumed after reading.

During a Program or Erase cycle in Flash memory,
the status can be output on Ready/Busy
This pin is set up using PSDsoft Express Configu­ration.

(PC3).

Memory Block Select Signals

The DPLD generates the Select signals for all the
internal memory blocks (see the section entitled
“PLDs,” page 97). Each of the eight sectors of the
primary Flash memory has a Sele ct signal (FS0­FS3) which can contain up to three product terms.
Each of the 2 sectors of the secondary Flash
memory has a Select signal (CSBOOT0­CSBOOT1) which can contain up to three product
terms. Having three product terms for each Select
signal allows a given sector to be mapped in Pro­gram or Data space.

Ready/Busy

output the Ready/Busy
ry. The output on Ready/Busy
when Flash memory is being written to,

(PC3 ). This signal can be used to

status of the Flash memo-

(PC3) is a 0 (Busy)

or

when
Flash memory is being erased. The output is a 1
(Ready) when no WRITE or Erase cycle is in
progress.

Memory Operation. The primary Flash memory
and secondary Flash memory are addressed
through the MCU Bus. The MCU can access these
memories in one of two ways:

– The MCU ca n execute a typical bus WRITE or

READ

operation

.

– The MCU can execute a specific Flash memory

instruction that consists of several WRITE and
READ operations. This involve s writing specific
data patterns to special addresses within the
Flash memory to invoke an embedded algo­rithm. These instructions are summarized in Ta­ble 62.

Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de­vice. However, Flash memory can only b e altered
using specific Erase and Program instructions. For
example, the MCU cannot write a single byte di­rectly to Flash memory as it would write a by te to
RAM. To program a byte into F lash memory, t he
MCU must execute a Program instruction, then
test the status of the Program cycle. This status
test is achieved by a RE AD operation or polling
Ready/Busy

(PC3).

84/152

Instructions

An instruction consists of a sequence o f specific
operations. Each received byte is sequentially de­coded by the PSD MODULE and not exec uted as
a standard WRITE operation. The instruction is ex­ecuted when the correct number of bytes are prop­erly received and the time between two
consecutive bytes is shorter than the time-out pe­riod. Some instructions are structured to include
READ operations after the initial WRITE opera­tions.

The instruction must be followed exactly. Any in­valid combination of instruction bytes or time-out
between two consecutive byte s while addressing
Flash memory resets the device logic into READ
Mode (Flash memory is read like a ROM device).

The Flash memory supports the instructions sum­marized in Table 62:

Flash memory:

■ Erase memory by chip or sector

■ Suspend or resume sector erase

■ Program a Byte

■ RESET to READ Mode

■ Read Sector Protection Status

UPSD3212C, UPSD3212CV

These instructions are detailed in Table 62. For ef­ficient decoding of the instructions, the first two
bytes of an instruction are the code d cycles and
are followed by an instruction byte or confirmation
byte. The coded cycles consist of writing the data
AAh to address X555h during the first cycle and
data 55h to address XAAAh during th e se cond c y­cle. Address signals A15-A12 are Don’t Care dur­ing the instruction WRITE cycles. However, the
appropriate Sector Select (FS0-FS3 or
CSBOOT0-CSBOOT1) must be selected.

The primary and secondary Flash memories have
the same instruction set. The Sector Select signals
determine which Flash memory is to receive and
execute the instruction. The primary Flash memo­ry is selected if any one of Sector Select (FS0­FS3) is High, and the secondary Flash memory is
selected if any one of Sector Select (CSBOO T0­CSBOOT1) is High.

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UPSD3212C, UPSD3212CV

Table 62. Instructions

Instruction

(5)

READ
READ Sector

Protection

(6,8,11)

Program a Flash

(11 )

Byte
Flash Sector

(7,11)

Erase
Flash Bulk

(11)

Erase
Suspend Sector

(9)

Erase
Resume Sector

(10)

Erase

(6)

RESET

Note: 1. All bus cycles are WRITE bus cycles, exce pt the ones with t he “Read” label

2. All values are in hexadecimal:
X = Don’t care. Ad dresses of the form XXXXh, in this tab l e, must be even addresses
RA = Address of the memor y location to be read
RD = Data READ from location RA during the READ cycle
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR
PA is an even address for PSD in Word P rogrammi ng M ode.
PD = Data word to be programmed at locati on PA. Data is latched on the rising edge of WRITE Str obe (WR
SA = Addres s of t he sect or to be erased or veri fied. Th e Sect or Selec t (FS0- FS3 o r CSBOOT 0-CSBO OT1) of the se ctor to b e
erased, or verified, must be Ac tive (High).

3. Sector Select (FS0-FS3 or CSBOOT0-CSBOOT1) signals are active High, and are defined in PSDsoft Express.

4. Only address Bits A 11-A0 are used i n i nstructi on decoding.

5. No Unlock or instruction cycl es are requir ed when the dev i ce is in the READ Mode

6. The RESE T I nstr uctio n is re quir ed to retu rn to the RE AD Mode afte r re adin g the S ecto r Prot ect ion St atus , or if t he Err or Fla g Bit
(DQ5) goes High.

7. Addit i onal sectors to be erased must be written at the end of the Sector Erase instructi on within 80µ s.

8. The dat a is 00h for an unp rotected sector, and 01h for a protec ted sector. In the fourth c ycle, the Sec tor Select is active, and
(A1,A0)= (1,0)

9. The system may perform READ and Program cycles in non-erasing sectors, read the Sector Protection Status when in the Suspend
Sector Eras e Mode. The S uspend Sector Erase inst ruction is val i d only during a Sector Eras e cy cle.

10. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase Mode.

11. The MCU cannot inv oke the se in stru ction s wh ile exe cuti ng cod e from the sa me Fla sh me mory as that fo r whic h the ins tru ctio n is
intended. T he MCU mus t re tri eve, for exam pl e, t he co de from th e sec ondar y Flas h me mor y wh en rea ding the Sec tor P rot ectio n
Status of th e pri m ary Flash me m ory.

FS0-FS3 or
CSBOOT0-

CSBOOT1

1

1

1

1

1

1

1

1

Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7

“Read”
RD @ RA

AAh@
X555h

AAh@
X555h

AAh@
X555h

AAh@
X555h

55h@
XAAAh

55h@
XAAAh

55h@
XAAAh

55h@
XAAAh

90h@
X555h

A0h@
X555h

80h@
X555h

80h@
X555h

Read status @
XX02h

PD@ PA

AAh@ X555h

AAh@ X555h

55h@
XAAAh

55h@
XAAAh

30h@
SA

10h@
X555h

B0h@
XXXXh

30h@
XXXXh

F0h@
XXXXh

, CNTL0)

(7)

30h
next SA

, CNTL0).

@

86/152

Power-down Instruction and Power-up Mode
Power-up Mode. The PSD MODULE internal

logic is reset upon Power-up to the READ Mode.
Sector Select (FS0-FS3 and CSBOOT0­CSBOOT1) must be held Low, and WRITE Strobe

, CNTL0) High, during Power-up for maximum

(WR
security of the data contents and to remove the
possibility of a byte being written on t he f irst edge
of WRITE Strobe (WR
initiation is locked when V

, CNTL0). Any WRITE cycl e

is below V

CC

LKO

.

READ

Under typical conditions, the MCU may read t he
primary Flash memory or the secondary Flash
memory using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use READ operations to ob tain status inform ation
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these memory blocks. The
following sections describe these READ functions.

READ Memory Contents. Primary Flash memo­ry and secondary Flash memory are placed in the
READ Mode after Power-up, chip reset, or a
Reset Flash instruction (see Table 62, page 86).
The MCU can read the memory contents of the pri­mary Flash memory or the secondary Flash mem­ory by using READ operations any time the READ
operation is not part of an instruction.

READ Memory Sector Protection Status. The
primary Flash memory Sector Protection Status is
read with an instruction composed of 4 operations:
3 specific WRITE operations and a READ opera­tion (see Table 62). During the READ operation,
address Bits A6, A1, and A0 must be '0,' '1 ,' and
'0,' respectively, while Sector Select (FS0-FS3 or
CSBOOT0-CSBOOT1) designates the Flash
memory sector whose protection has to be v eri­fied. The READ operation produces 01h if the
Flash memory sector is protected, or 00h if the
sector is not protected.

The sector protection status for all NVM blocks
(primary Flash memory or secondary Flash mem­ory) can also be read by the M CU accessing the
Flash Protection registers in PSD I/O space. See

UPSD3212C, UPSD3212CV

the section entitled “Flash Memory Sector Pro­tect,” page 92, for register definitions.

Reading the Erase/Program Status Bits. The
Flash memory provides several status bits to be
used by the MCU to confirm the c ompletion of an
Erase or Program cycle of Flash memory. These
status bits minimize the time that the MCU spends
performing these tasks and are defined in Table
63, page 88. The status bits can be read as many
times as needed.

For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algorithm. See the section entit led
“Programming Flash Memory,” page 89, for de­tails.

Data Polling Flag (DQ7). When erasing or pro­gramming in Flash memory, the Data Polling Flag
Bit (DQ7) outputs the complement of the bit being
entered for programming/writing on the DQ7 Bit.
Once the Program instruction or the WRITE oper­ation is completed, the true logic value i s read on
the Data Polling Flag Bit (DQ7) (in a READ opera­tion).

– Data Polling is effective af ter the fourth WRITE

pulse (for a Program instruction) or after the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being pro­grammed or at an address within the Flash
memory sector being erased.

– During an Era se cycl e , the Data Polling Flag Bit

(DQ7) outputs a '0.' After completion of the cy­cle, the Data Polling Flag B it (DQ7) outputs the
last bit programmed (it is a '1' after erasing).

– If the byte to be program med is in a protected

Flash memory sector, the instruction is ignored.

– If all the Flash memory sectors to be erased are

protected, the Data Polling Flag Bit (DQ7) is re­set to '0' for about 100µs, and then returns to the
previous addressed byte. No erasure is per­formed.

87/152

UPSD3212C, UPSD3212CV

Toggle Flag ( DQ6 ). The Flash memory offers an-

other way for determining when the Program cycle
is completed. During the internal WRITE operation
and when either the FS0-FS3 or CSBOOT0­CSBOOT1 is true, the Toggle Fla g Bit (DQ6) tog­gles from 0 to 1 and 1 to 0 on subsequent attempts
to read any byte of the memory.

When the internal cycle is complete, the toggling
stops and the data READ on the Data Bus D0-D7
is the addressed memory byte. The device is now
accessible for a new RE AD or WRITE operat ion.
The cycle is finished when two successive Reads
yield the same output data.

– The Toggle Flag Bit (DQ6) is effective after the

fourth WRITE pulse (for a Program instruction)
or after the sixth WRITE pulse (for an E rase in­struction).

– If the byte to be programmed b elongs to a pro-

tected Flash memory sector, the instruc tion is
ignored.

– If all the Flash memory sectors selected for era-

sure are protected, the Toggle Flag Bit (DQ6)
toggles to '0' for about 100µs and then returns to
the previous addressed byte.

Error Flag (DQ5). During a normal Program or
Erase cycle, the Error Flag Bit (DQ5) is to 0. This

bit is set to '1' when there is a failure during F lash
memory Byte Program, Sector Erase, or Bulk
Erase cycle.

In the case of Flash memory programming, the Er­ror Flag Bit (DQ5) indicates the attempt to program
a Flash memory bit from the programmed state,
'0,' to the erased state, '1,' which is not valid. The
Error Flag Bit (DQ5) may also indicate a Time-out
condition while attempting to program a byte.

In case of an error in a Flash memory Sector Erase
or Byte Progra m cycle, the Fl ash memory sector i n
which the error occurred or to which the pro­grammed byte belongs must no longer be used.
Other Flash memory sectors may still be used.
The Error Flag Bit (DQ5) is reset after a Reset
Flash instruction.

Erase Time-out Flag (DQ3). The Erase Time­out Flag Bit (DQ 3) reflects the time-out period al­lowed between two consecutive Sec tor Erase in­structions. The Erase Tim e-out Flag Bit (DQ3) is
reset to 0 after a Sector Erase cycle for a time pe­riod of 100µs + 20% unless an additional Sector
Erase instruction is decoded. After this time peri­od, or when the additional Sector Erase instruction
is decoded, the Erase Time-out Flag Bit (DQ3) is
set to '1.'

Table 63. Status Bit

Functional Block

Flash Memory

Note: 1. X = Not guaranteed value, can be read ei ther '1' or '0. '

2. DQ7-DQ0 represent the Data Bus bits, D7-D0.

3. FS0-FS 3 and CSBOO T 0-CSBOOT 1 are active High.

FS0-FS3/CSBO OT0-

CSBOOT1

V

IH

DQ7 DQ6 DQ5 DQ4 D Q3 DQ2 DQ1 DQ0

Data
Polling

Toggle
Flag

Error
Flag

Erase

X

Time­out

XXX

88/152

Programming Flash Memory

Flash memory must be erased prior to being pro­grammed. A byte of Flash memory is erased to all
'1s' (FFh), and is programmed by set ting select ed
bits to '0.' The MC U may e rase F lash memory a ll
at once or by-sector, but not byte-by-byte. Howev­er, the MCU may program Flash memory byte-by­byte.

The primary and secondary Flash memories re­quire the MCU to send an instruction to program a
byte or to erase sectors (see Table 62).

Once the MCU issues a Flash memory Program or
Erase instruction, it must check for the status bits
for completion. The embedded algorithms that are
invoked support several m eans to provide status
to the MCU. Status may be checked using an y of
three methods: Data Polling, Data Toggle, or
Ready/Busy

(PC3).

Data Polling. Polling on the D at a P olling Flag Bit
(DQ7) is a method of checking whether a Program
or Erase cycle is in progress or has completed.
Figure 42 shows the Data Polling algorithm.

When the MCU issue s a Program i nstruction, the
embedded algorithm begins. The MCU then reads
the location of the byte to be programmed in Flash
memory to check status. The Data Polling Flag Bit
(DQ7) of this location becomes the complement of
b7 of the original data byte to be programmed. The
MCU continues to poll this location, comparing the
Data Polling Flag Bit (DQ7) and monitoring the Er­ror Flag Bit (DQ5). When the Data Polling Flag Bit
(DQ7) matches b7 of the original data, and the Er­ror Flag Bit (DQ5) remains '0,' the embedded algo­rithm is complete. If the Error Flag Bit (DQ5) is '1,'
the MCU should test the Data Polling Flag Bit
(DQ7) again since the Data Polling Flag Bit (DQ7)
may have changed simultaneously with the Error
Flag Bit (DQ5) (see Figure 42).

The Error Flag Bit (DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte or if the MCU a t­tempted to program a '1' to a bit that was not
erased (not erased is logic '0').

It is suggested (as with all Flash memories) to read
the location again after the embedded program­ming algorithm has completed, to compare the

UPSD3212C, UPSD3212CV

byte that was written to the Flash memory with the
byte that was intended to be written.

When using the Data Polling method during an
Erase cycle, Figure 42 still applies. However, the
Data Polling Flag Bit (DQ7) is '0' until the Erase cy­cle is complete. A '1' on the Error Flag Bit (DQ5) in­dicates a time-out condition on the Erase cycle; a
'0' indicates no error. The MCU can read any loca­tion within the sector being erased to get the Data
Polling Flag Bit (DQ7) and the Error Flag Bit
(DQ5).

PSDsoft Express generates ANSI C code func­tions which implement these Data Polling algo­rithms.

Figure 42. Data Polling Flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

DQ7

DATA

NO

DQ5

READ DQ7

DQ7

DATA

FAIL PASS

= 1

YES

=

NO

YES

YES

=

NO

AI01369B

89/152

UPSD3212C, UPSD3212CV

Data Toggle. Checking the Toggle Flag Bit

(DQ6) is a method of determinin g whether a P ro­gram or Erase cycle is in progress or has complet­ed. Figure 43 shows the Data Toggle algorithm.

When the MCU issue s a Program i nstruction, the
embedded algorithm begins. The MCU then reads
the location of the byte to be programmed in Flash
memory to check status. The Toggle Flag Bit
(DQ6) of this location toggles each time the MCU
reads this location until the embedded algorithm is
complete. The MCU continues to read this loca­tion, checking the Toggle Flag Bit (DQ6) and mon­itoring the Error Flag Bit (DQ5). When the Toggle
Flag Bit (DQ6) stops toggling (two consecutive
reads yield the same value), and the Error Flag Bit
(DQ5) remains '0,' the embedded algorithm is
complete. If the Error Flag Bit (DQ5) is '1,' the
MCU should test the Toggle Flag Bit (DQ6) again,
since the Toggle Flag Bit (DQ6) may have
changed simultaneously with the Error Flag Bit
(DQ5) (see Figure 43).

The Error Flag Bit(DQ5) is set if either an internal
time-out occurred while the embedded algorithm
attempted to program the byte, or if the MCU at­tempted to program a '1' to a bit that was not
erased (not erased is logic '0').

It is suggested (as with all Flash memories) to read
the location again after the embedded program­ming algorithm has completed, to compare the
byte that was written to Flash memory with the
byte that was intended to be written.

When using the Data Toggle method after an
Erase cycle, Figure 43 still applies. the Toggle
Flag Bit (DQ6) toggles until the Erase cycle is
complete. A '1' on the Error Flag Bit (DQ5) i ndi­cates a time-out condition on the Erase cycle; a '0'

indicates no error. The MCU can read any location
within the sector being erased t o get the Toggle
Flag Bit (DQ6) and the Error Flag Bit (DQ5).

PSDsoft Express generates ANSI C code func­tions which implement these Data T oggling algo­rithms.

Figure 43. Data Toggle Flowchart

START

READ

DQ5 & DQ6

DQ6

=

TOGGLE

NO

DQ5

= 1

READ DQ6

DQ6

=

TOGGLE

FAIL PASS

NO

YES

YES

NO

YES

AI01370B

90/152

UPSD3212C, UPSD3212CV

Erasing Flash Memory
Flash Bulk Erase. The Flash Bulk Eras e instruc-

tion uses six WRITE operations followed by a
READ operation of the status register, as de­scribed in Table 62. If any byte of the B ulk Erase
instruction is wrong, the Bulk Erase instruction
aborts and the device is reset t o the READ F lash
memory status.

During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Fl ag
Bit (DQ7), as detailed in the section entitled “Pro­gramming Flash Memory,” page 89. The Error
Flag Bit (DQ5) returns a '1' if there has been an
Erase Failure (maximum number of Erase cycles
have been executed).

It is not necessary to program the memory with
00h because the PSD MODULE automatically
does this before erasing to 0FFh.

During execution of the Bulk Erase instruction, the
Flash memory does not accept any instructions.

Flash Sector Erase. The Sector Erase instruc­tion uses six WRITE operations, as described in
Table 62. Additional Flash Sector Erase codes
and Flash memory sector addresses can be writ­ten subsequently to erase other Flash memory
sectors in parallel, without further coded cycles, if
the additional bytes are transmitted in a shorter
time than the time-out period of about 100µ s . The
input of a new Sector Erase code restarts the time­out period.

The status of the internal timer can be monitored
through the level of the Erase Time-out Flag B it
(DQ3). If the Erase T ime-out F lag Bit (DQ3) is '0,'
the Sector Erase instruction has been received
and the time-out period is counting. If the Erase
Time-out Flag Bit (DQ3) is '1,' the time-out period
has expired and the embedded algorithm is busy
erasing the Flash memory secto r(s ). Before and
during Erase time-out, any instruction other t han
Suspend Sector Erase and Resume Sector Erase
instructions abort the cycle that is currently in
progress, and reset the device to READ Mode.

During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5), the
Toggle Flag Bit (DQ6), and the Data Polling Fl ag
Bit (DQ7), as detailed in the section entitled “Pro­gramming Flash Memory,” page 89.

During execution of the Erase cycle, the Flash
memory accepts only RESET and Suspend Sec­tor Erase instructions. Erasure of one Flash mem­ory sector may be suspended, in order to read
data from another Flash memory sector, and then
resumed.

Suspend Sector Erase. When a Sector Erase
cycle is in progress, the Suspend Sector Erase in­struction can be used to suspend the cycle by writ­ing 0B0h to any address when an appropriate
Sector Se lect (FS0 -FS3 or CSBOOT0-CSBO OT1)
is High. (See Table 62). This allows reading of
data from another Flash memory sector after the
Erase cycle has been suspended. Suspend Sec­tor Erase is accepted only during an Era se cycle
and defaults to READ Mode. A Suspend Sector
Erase instruction executed during an Erase time­out period, in addition to suspending the Erase cy­cle, terminates the time out period.

The Toggle Flag Bit (DQ6) stops toggling when the
internal logic is suspended. Th e status of this bit
must be monitored at an address wi thin the F lash
memory sector being erased. The Toggle Flag Bit
(DQ6) stops toggling between 0.1µs and 15µs af­ter the Suspend Sector Erase instruction has been
executed. The Flash memory is then automatically
set to READ Mode.

If an Suspend Se ctor Erase instruction was exe­cuted, the following rules apply:

– Attempting to read from a Flash memory se ctor

that was being erased outputs invalid data.

not

– Reading from a Flash sector that was

erased is valid.

– The Flash memory

only responds to Resume Sector Erase and
Reset F las h in s t r uc tions (READ is a n op er ation
and is allowed).

– If a Reset Flash instruction is received, data in

the Flash memory sector that was being erased
is invalid .

Resume Sector Erase. If a Suspend Sector
Erase instruction was previously executed, the
erase cycle may be resumed with this instruction.
The Resume Sector Eras e instruction consists of
writing 030h to any address w hile an appropriate
Sector Se lect (FS0 -FS3 or CSBOOT0-CSBO OT1)
is High. (See Table 62.)

cannot

be programmed, and

being

91/152

UPSD3212C, UPSD3212CV

Specific Features
Flash Memory Sector Protect. Each primary

and secondary Flash memory sector can be sepa­rately protected against Program and Erase cy­cles. Sector Protection provides additional data
security because it disables all Program or Erase
cycles. This mode can be activated through the
JTAG Port or a Device Programmer.

Sector protection can be selected for each sector
using the PSDsoft Express Configuration pro­gram. This automatically protects selected sectors
when the device is programmed through the JTAG
Port or a Device Programmer. Flash memory sec­tors can be unprotected t o allow updat ing of their
contents using the JTAG Port or a Device Pro­grammer. The MCU can read (but cannot change)
the sector protection bits.

Any attempt to program or erase a protected Flash
memory sector is ignored by the device. The Verify
operation results in a READ of the protected data.
This allows a guarantee of the retention of the Pro­tection status.

The sector protection status ca n be read by the
MCU through the Flash memory protection regis-

ters (in the CSIOP block). See Table 64 and Table

65.
Reset Flash. The Reset Flash instruction con-

sists of one WRITE cycle (see Table 62). It can
also be optionally preced ed by the standard two
WRITE decoding cycles (writing AAh to 555h and
55h to AAAh). It must be executed after:

– Reading the Flash Protection Status or Flash ID
– An Error condition has occurred (and the device

has set the Error Flag Bit (DQ5 ) to '1' during a
Flash memory Program or Erase cycle.

The Reset Flash instruction puts the Flash memo­ry back into normal READ Mode. If an Error condi­tion has occurred (and the device has set the Error
Flag Bit (DQ5) to '1' the Flash memory is put back
into normal READ Mode within a few milliseconds
of the Reset Flash instruction having been issued.
The Reset Flash instruction is ignored when it is is­sued during a Program or Bulk Erase cycle of the
Flash memory. The Reset Flash instruction aborts
any on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within a
few millis econds.

Table 64. Sector Protection/Security Bit Definition – Flash Protection Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot

Note: Bit Definitions:

Sec<i>_Prot 1 = Primary Flash memory or sec ondary Flas h m em ory Sector <i> is write -protected.
Sec<i>_Prot 0 = Primary Flash memory or secondar y Fl ash memory Sector <i> is not write-p rot ected.

Table 65. Sector Protection/Security Bit Definition – Secondary Flash Protection Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Security_Bit not used not used not used not used not used Sec1_Prot Sec0_Prot

Note: Bit Definitions:

Sec<i>_Prot 1 = Secondary Flash memory Se ct or <i> is write-protected.
Sec<i>_Prot 0 = Secondary Flash memory Sector < i > is not write-protected.
Security_Bit 0 = Security Bit in device has not been set; 1 = Security Bit in device has been set.

92/152

SRAM

The SRAM is enab led when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two prod uct terms, allow ing flexible
memory mapping.

The SRAM can be backed up usin g an external
battery. The external battery should be connected
to Voltage Standby (V

, PC2). If you have an

STBY

external battery connected to the uPS D3200, the
contents of the SRAM are retained in the event of
a power loss. The contents of the SRAM are re­tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat­tery voltage, an internal power s witchover to the
battery occurs.

PC4 can be configured as an output that indicates
when power is being drawn from the external ba t­tery. Battery-on Indicator (V

, PC4) is High

BATON

with the supply voltage falls below the battery volt­age and the battery on Voltage Standby (V

STBY

PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Standby (V

PC2) and Battery-on Indicat or (V

BATON

STBY

, PC4) are
all configured using PSDsoft Express Configura­tion.

Sector Select and SRAM Select

Sector Select (FS0-FS3, CSBOOT0-CSBOOT1)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDsoft Express. The following rules ap­ply to the equations for these signals:

1. Primary Flash memory and secondary Flash

not

memory Sector Select signals must

be larg -

er than the physical sector size.

2. Any primary F lash memory sector m ust

not

be
mapped in the same memory space as another
Flash memory sector.

not

3. A secondary Flas h memory sector must

be
mapped in the same memory space as another
secondary Flash memory sector.

4. SRAM, I/O, and Peripheral I/O spaces must

not

overlap.

may

5. A secondary Flash memo ry sector

overlap

a primary Flash memory sector. In case of over-

UPSD3212C, UPSD3212CV

lap, priority is given to the secondary Flash
memory sector.

6. SRAM, I/O, and Peripheral I/O spaces
overlap any other memory sector. Priority is giv­en to the SRAM, I/O, or Peripheral I/O.

Example. FS0 is valid when the address is in the
range of 8000h to BFFFh, CSBOOT0 is valid from
8000h to 9FFFh, and RS0 is valid from 8000 h to
87FFh. Any address in the range of RS0 always
accesses the SRAM. Any address in the range of
CSBOOT0 greater than 87FFh (and less than
9FFFh) automatically addresses secondary Flash
memory segment 0. Any address greater than
9FFFh accesses the primary Flash me mory seg­ment 0. You can see that half of the primary Flash
memory segment 0 and one-fou rth of secondary
Flash memory segment 0 cannot be accessed in
this example.

,

Note: An equation that defined FS1 to anywhere
in the range of 8000h to BFFFh would

,

Figure 44 shows the priority levels for all memory
components. Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must

not

overlap. Level one has the highest priority and

level 3 has the lowest.

Figure 44. Priority Level of Memory and I/O Components in the PSD MODULE

Highest Priority

Level 1

SRAM, I/O, or
Peripheral I/O

Level 2

Secondary

Non-Volatile Memory

Level 3

Primary Flash Memory

Lowest Priority

not

be valid.

may

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UPSD3212C, UPSD3212CV

Memory Select Co nfiguratio n in Pro gram and
Data Spaces. The MCU Core has separate ad-

dress spaces for Program memory and Data
memory. Any of the memories within the PSD
MODULE can reside in either space or both spac­es. This is controlled t hrough manipulation of the
VM Register that resides in the CSIOP space.

The VM Register is set using PSDsoft Express to
have an initial value. It can subsequently be
changed by the MCU so that memory mapping
can be changed on-the-fly.

Table 66. VM Register

Bit 7

PIO_EN

0 = disable
PIO Mode

1= enable
PIO Mode

Bit 6 Bit 5

not used not used

not used not used

Bit 4

Primary

FL_Data

0 = RD
can’t
access
Flash
memory

1 = RD
access
Flash
memory

Secondary Data

0 = R
access Secondary
Flash memory

1 = RD
Secondary Flash
memory

For example, you may wish to have SRAM and pri­mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later s wap t he p r imary and
secondary Flash memories. This is easily done
with the VM Register by using PSDsoft Express
Configuration to configure it for Boot-up and hav­ing the MCU change it when desired. Table 66 de­scribes the VM Register.

Bit 3

D can’t

access

Bit 2

Primary

FL_Code

0 = PSEN
can’t
access
Flash
memory

1 = PSEN
access
Flash
memory

Bit 1

Secondary Code

0 = PSE
access Secondary
Flash memory

1 = PSEN
Secondary Flash
memory

N can’t

access

Bit 0

SRAM_Code

0 = PSEN
can’t
access
SRAM

1 = PSEN
access
SRAM

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UPSD3212C, UPSD3212CV

Separate Space Mode. Progra m space is sepa-

rated from Data space. For example, Program Se­lect E nab le (PSEN

) is used to access the program
code from the primary Flash memory, while READ
Strobe (RD

) is used to access d ata from the sec ­ondary Flash memory, SRAM and I/O Port blocks.
This configuration requires the VM Register to be
set to 0Ch (see Figure 45).

Figure 45. Separate Space Mode

DPLD

RS0

CSBOOT0-1

FS0-FS3

PSEN

RD

Primary

Flash

Memory

CS CSCS

OE OE

Figure 46. Combined Space Mode

Combined Space Modes. The Program and

Data spaces are combined into one memory
space that allows the primary Flash memory, sec­ondary Flash memory, and SRAM to be accessed
by either Program Select Enable (PSEN) or READ
Strobe (RD

). For example, to configure the prima­ry Flash memory in Combin ed spac e, B its b2 and
b4 of the VM Register are set to '1' (see Figure 46).

Secondary

Flash

Memory

SRAM

OE

AI07433

RD

VM REG BIT 3

VM REG BIT 4

PSEN

VM REG BIT 1

VM REG BIT 2

VM REG BIT 0

DPLD

RS0

CSBOOT0-1

FS0-FS3

Primary

Flash

Memory

CS CSCS

OE OE

Secondary

RD

Flash

Memory

SRAM

OE

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UPSD3212C, UPSD3212CV

Page Regis te r

The 8-bit Page Register increases the addressing
capability of the MCU Core by a factor of up to 256.
The contents of the register can also be read by
the MCU. The outputs of the Page Register
(PGR0-PGR7) are inputs to the DPLD decoder
and can be included in the Sector Select (FS0­FS3, CSBOOT0-CSBOOT1), and SRAM Select
(RS0) equations.

Figure 47. Page Register

RESET

If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for gen eral
logic.

Figure 47 shows the Page Register. The eight flip­flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.

D0-D7

R/W

D0 Q0
D1
D2
D3
D4
D5
D6
D7

Q1
Q2
Q3
Q4
Q5
Q6
Q7

PAGE

REGISTER

PGR0
PGR1

PGR2
PGR3
PGR4
PGR5
PGR6
PGR7

DPLD

AND

CPLD

PLD

INTERNAL PSD MODULE
SELECTS
AND LOGIC

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PLDS

The PLDs bring programmable logic f unctionality
to the uPSD. After specifying the logic for the
PLDs in PSDsoft Express, the logic is pro­grammed into the device and available upon Pow­er-up.

Table 67. DPL D a nd CP LD I nputs

Number

Input Source Input Name

MCU Address Bus

MCU Control Signals

RESET RST
Power-down PDN 1
Port A Input

Macrocells
Port B Input

Macrocells
Port C Input

Macrocells
Port D Inputs

Page Register PGR7-PGR0 8
Macrocell AB

Feedback
Macrocell BC

Feedback
Flash memory

Program Status Bit

Note: 1. These inp uts are not avail able in the 52-pin package.

1

A15-A0 16

, RD, WR,

PSEN
ALE

1

PA7-PA0 8

PB7-PB0 8

PC7, PC4-PC2 4

PD2-PD1 2

MCELLAB.FB7­FB0

MCELLBC.FB7­FB0

Ready/Busy

1

of

Signals

4

8

8

UPSD3212C, UPSD3212CV

The PSD MODULE contains two PLDs: the De­code PLD (DPLD), and the Complex PLD (CPLD).
The PLDs are briefly discussed in the next few
paragraphs, and in more detail in the section enti­tled “Decode PLD (DPLD),” page 99, and the sec­tion entitled “Complex PLD (CPLD),” page 100.
Figure 48 shows the configuration of the PLDs.

The DPLD performs add ress decoding for Sel ect
signals for PSD MODULE components, such as
memory, registers, and I/O ports.

The CPLD can be used for logic functions, such as
loadable counters and shift registers, state ma­chines, and encoding and decoding logic. These
logic functions can be cons tructed us ing the Out­put Macrocells (OMC), Input Macrocells (IMC),
and the AND Array. The CPLD can also b e used
to generate External Chip Select (ECS1-ECS2)
signals.

The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
The PLD input signals consist of internal MCU sig­nals and external inputs from the I/O ports. The in­put signals are shown in Table 67.

The Turbo Bit in PSD MODULE

The PLDs can minimize power consumption by
switching off when input s remain unchanged for
an extended time of about 70ns. Resetting the
Turbo Bit to '0' (Bit 3 of PMMR0) automatically
places the PLDs into standby if no inputs are
changing. Turning the T urbo Mode off increases
propagation delays while reducing power con­sumption. See the section entitled “POWER MAN­AGEMENT,” page 11 3, on how to set the Turbo
Bit.

Additionally, five bits are available in PMM R2 to
block MCU control signals from entering the PLDs.
This reduces power consumption and can be used
only when these MCU control signals are not used
in PLD logic equations.

Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.

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UPSD3212C, UPSD3212CV

Figure 48. PLD Diagram

DATA

BUS

8

PAGE

REGISTER

73

16

PLD INPUT BUS

73

DIRECT MACROCELL INPUT TO MCU DATA BUS

DECODE PLD

OUTPUT MACROCELL FEEDBACK

CPLD

4

2
1
1
2

PT

ALLOC.

20 INPUT MACROCELL

PRIMARY FLASH MEMORY SELECTS

SECONDARY NON-VOLATILE MEMORY SELECTS

SRAM SELECT
CSIOP SELECT
PERIPHERAL SELECTS

DIRECT MACROCELL ACCESS FROM MCU DATA BUS

16 OUTPUT

MACROCELL

(PORT A,B,C)

MACROCELL

ALLOC.

I/O PORTS

MCELLAB

TO PORT A OR B

MCELLBC

TO PORT B OR C

EXTERNAL CHIP SELECTS

TO PORT D

1

8

8

2

20

INPUT MACROCELL & INPUT PORTS

2

PORT D INPUTS

Note: 1. Ports A is not availa bl e i n the 52-pin package

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Decode PLD (DPLD)

The DPLD, shown in Figure 49, is used for decod­ing the address for PSD MODULE and external
components. The DPLD can be used to generate
the following decode signals:

– 4 Sector Select (FS0-FS3) signals for the prima-

ry Flash memory (three product terms each)

– 2 Sector Select (CSBOOT0-CSBOOT1) signals

for the secondary Flash memory (three product
terms each)

Figure 49. DPLD Logic Array

UPSD3212C, UPSD3212CV

– 1 internal SRAM Select (RS0) signal (two prod-

uct terms)

– 1 internal CSIOP Select signal (selects the PSD

MODULE registers)

– 2 internal Peripheral Select signals (Peripheral

I/O Mode).

I/O PORTS (PORT A,B,C)

MCELLAB.FB [7:0] (FEEDBACKS)

MCELLBC.FB [7:0] (FEEDBACKS)

PGR0 -PGR7

2

]

A[15:0

]

PD[2:1

PDN (APD OUTPUT)

PSEN, RD, WR, ALE

2

RESET

RD_BSY

1

2

(INPUTS)

(20)

(8)

(8)

(8)

(16)

(2)

(1)

(4)

(1)

(1)

3

3

3

3

3

3

2

1

1

1

CSBOOT 0

CSBOOT 1

RS0

CSIOP

PSEL0

PSEL1

FS0

FS1

FS2

FS3

SRAM SELECT
I/O DECODER

SELECT

PERIPHERAL I/O
MODE SELECT

4 PRIMARY FLASH
MEMORY SECTOR
SELECTS

Note: 1. Port A inputs are not avail able in the 52-pin package

2. Inputs from the MCU module

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UPSD3212C, UPSD3212CV

Complex PLD (CPLD)

The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg­isters, system mailboxes, ha ndshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate External Chip Select
(ECS1-ECS2), routed to Port D.

Although External Chip Select (ECS1-ECS2) can
be produced by any Output Macrocell (OMC),
these External Chip Select (ECS1-ECS2) on Port
D do not consume any Output Macrocells (OMC).

As shown in Figure 48, the CPLD has the following
blocks:

■ 20 Input Macrocells (IMC)

■ 16 Output Macrocells (OMC)

■ Macrocell Allocat o r

■ Product Term Allocator

Figure 50. Macrocell and I/O Port

■ AND Array capable of generating up to 137

product terms

■ Four I/O Ports.

Each of the blocks are described in the sections
that fo llow.

The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected t o the PSD MODULE in ter­nal data bus and can be directly acc essed by the
MCU. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).

This feature allows efficient implementation of sys­tem logic and eliminat es the need to connec t the
data bus to the AND Array as required in most
standard PLD macrocell architectures.

PLD INPUT BUSPLD INPUT BUS

AND ARRAY

PRODUCT TERMS

FROM OTHER

MACROCELLS

CPLD MACROCELLS

PRODUCT TERM

ALLOCATOR

UP TO 10

PRODUCT TERMS

POLARITY
SELECT

PT
CLOCK

GLOBAL
CLOCK

CLOCK
SELECT

PT CLEAR

PT OUTPUT ENABLE (OE

MACROCELL FEEDBACK

I/O PORT INPUT

PT INPUT LATCH GATE/CLOCK

PT PRESET

MUX

MCU DATA IN

PR DI LD

D/T

D/T/JK FF

SELECT

CK

CL

)

MCU ADDRESS / DATA BUS

DATA
LOAD

CONTROL

MCU LOAD

MACROCELL

OUT TO

MUX

Q

COMB.

/REG

SELECT

MCU

CPLD

OUTPUT

MACROCELL

TO

I/O PORT

ALLOC.

TO OTHER I/O PORTS

I/O PORTS

LATCHED

ADDRESS OUT

DATA

D

Q

WR

CPLD OUTPUT

PDR

INPUT

Q

D

DIR

REG.

WR

INPUT MACROCELLS

ALE

MUX MUX

MUX

SELECT

Q

QD

I/O PIN

D

G

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