Datasheet UPD784021GK-BE9, UPD784021GC-3B9, UPD784020GC-3B9 Datasheet (NEC)

Page 1

DATA SHEET

MOS INTEGRATED CIRCUIT

PD784020, 784021

16/8-BIT SINGLE-CHIP MICROCOMPUTER

The mPD784021 is a product of the mPD784026 sub-series in the 78K/IV series. It contains various peripheral hardware such as RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance CPU.

PD784021 is a ROM-less product of the mPD784025 or mPD784026.

The

PD784020 differs from the mPD784021 only in its RAM size: 512 bytes are allocated for the mPD784020,

The while 2048 bytes are allocated for the

For specific functions and other detailed information, consult the following user’s manual.

This manual is required reading for design work.

PD784026 Sub-Series User’s Manual, Hardware : U10898E

78K/IV Series User’s Manual, Instruction : U10905E

PD784021.

FEATURES

• 78K/IV series

• Pin-compatible with the

• Minimum instruction execution time: 160 ns

(at 25 MHz)

• Number of I/O ports: 46

• Timer/counters: 16-bit timer/counter ¥ 3 units

16-bit timer ¥ 1 unit

• Serial interface: 3 channels

UART/IOE (3-wire serial I/O) :2 channels CSI (3-wire serial I/O, SBI) : 1 channel

APPLICATIONS

LBP, automatic-focusing camera, PPC, printer, electronic typewriter, air conditioner, electronic musical instruments, cellular telephone, etc.

PD78234 sub-series

• PWM outputs: 2

• Standby function

HALT/STOP/IDLE mode

• Clock frequency division function

• Watchdog timer : 1 channel

• A/D converter : 8-bit resolution ¥ 8 channels

• D/A converter : 8-bit resolution ¥ 2 channels

• Supply voltage : VDD = 2.7 to 5.5 V

This manual describes the

The information in this document is subject to change without notice.

Document No. U11514EJ1V0DS00 (1st edition) (Previous No. IP-3234) Date Published July 1996 P Printed in Japan

PD784021 unless otherwise specified.

The mark H shows major revised points.

1990

1996

Page 2

ORDERING INFORMATION

Part number Package Internal ROM Internal RAM

PD784020GC-3B9 80-pin plastic QFP (14 ¥ 14 mm) None 512

PD784021GC-3B9 80-pin plastic QFP (14 ¥ 14 mm) None 2048

PD784021GK-BE9 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) None 2048

78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM

: Product under mass production : Product under development

: Product under planning

Standard Products Development

PD784038Y sub-series

 Product containing for 

C bus interface circuit

an I 

PD784038 sub-series

 80-pin, 8-bit A/D, 8-bit D/A ROM: 48K/64K/96K/128K

PD784020, 784021

(bytes) (bytes)



PD784026 sub-series 80-pin, 8-bit A/D, 8-bit D/A ROM: none/48K/64K



ASSP Development



PD784216 sub-series

100-pin, 8-bit A/D, 8-bit D/A ROM: 96K/128K

PD784915 sub-series

VTR servo, 100-pin, built-in  analog amplifier  ROM: 48K/62K

PD784216Y sub-series

Product containing for 

two I

C bus interface circuits

PD784054

80-pin, 10-bit A/D ROM: 32K

PD784046 sub-series sub-set



PD784046 sub-series

80-pin, 10-bit A/D ROM: 32K/64K

PD784908 sub-series

100-pin, built-in IEBusTM  ROM: 96K/128K

PD784943 sub-series

80-pin, for CD-ROM ROM: 56K



Page 3

FUNCTIONS

PD784020, 784021

Product

Item Number of basic instructions

(mnemonics) General-purpose register Minimum instruction execution

time Internal

memory Memory space

I/O ports

Additional function

Note

pins

Real-time output ports Timer/counter

PWM outputs Serial interface

A/D converter D/A converter Watchdog timer Standby Interrupt Source

Supply voltage Package

ROM RAM

Total Input Input/output Output Pins with pull-

up resistor LED direct

drive outputs Transistor

direct drive

Software Nonmaskable Maskable

PD784020

113

8 bits ¥ 16 registers ¥ 8 banks, or 16 bits ¥ 8 registers ¥ 8 banks (memory mapping) 160 ns/320 ns/640 ns/1280 ns (at 25 MHz)

None 512 bytes 2048 bytes Program and data: 1M byte 46 8 34 4 32

4 bits ¥ 2, or 8 bits ¥ 1 Timer/counter 0: Timer register ¥ 1 Pulse output capability

(16 bits) Capture register ¥ 1 Ý Toggle output

Compare register ¥ 2 Ý PWM/PPG output

Timer/counter 1: Timer register ¥ 1 Pulse output capability (8/16 bits) Capture register ¥ 1 Ý Real-time output (4 bits ¥ 2)

Capture/compare register ¥ 1 Compare register ¥ 1

Timer/counter 2: Timer register ¥ 1 Pulse output capability (8/16 bits) Capture register ¥ 1 Ý Toggle output

Capture/compare register ¥ 1 Ý PWM/PPG output Compare register ¥ 1

Timer 3 : Timer register ¥ 1 (8/16 bits) Compare register ¥ 1

12-bit resolution ¥ 2 channels UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator)

CSI (3-wire serial I/O, SBI) : 1 channel 8-bit resolution ¥ 8 channels 8-bit resolution ¥ 2 channels 1 channel HALT/STOP/IDLE mode 23 (16 internal, 7 external (sampling clock variable input: 1)) + BRK instruction BRK instruction 1 internal, 1 external 15 internal, 6 external

Ý 4-level programmable priority Ý 3 operation statuses: vectored interrupt, macro service, context switching

VDD = 2.7 to 5.5 V 80-pin plastic QFP (14 ¥ 14 mm)

80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm): for the mPD784021 only

PD784021

Ý One-shot pulse output

Note Additional function pins are included in the I/O pins.

Page 4

PD784020, 784021

1. DIFFERENCES BETWEEN

2. MAIN DIFFERENCES BETWEEN

PD784026 SUB-SERIES ........................................................... 6

PD784026 AND

PD78234 SUB-SERIES..................... 7

3. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 8

4. SYSTEM CONFIGURATION EXAMPLE (PPC) ....................................................................... 10

5. BLOCK DIAGRAM..................................................................................................................... 1 1

6. LIST OF PIN FUNCTIONS ........................................................................................................ 12

6.1 PORT PINS...................................................................................................................................... 12

6.2 NON-PORT PINS ............................................................................................................................ 13

6.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS ................................................. 15

7. CPU ARCHITECTURE .............................................................................................................. 18

7.1 MEMORY SPACE ........................................................................................................................... 18

7.2 CPU REGISTERS............................................................................................................................ 21

7.2.1 General-Purpose Registers.......................................................................................... 21

7.2.2 Control Registers ........................................................................................................... 22

7.2.3 Special Function Registers (SFRs)............................................................................. 23

8. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 28

8.1 PORTS ............................................................................................................................................. 28

8.2 CLOCK GENERATOR .................................................................................................................... 29

8.3 REAL-TIME OUTPUT PORT .......................................................................................................... 31

8.4 TIMERS/COUNTERS ...................................................................................................................... 32

8.5 PWM OUTPUT (PWM0, PWM1)..................................................................................................... 34

8.6 A/D CONVERTER ........................................................................................................................... 35

8.7 D/A CONVERTER ........................................................................................................................... 36

8.8 SERIAL INTERFACE ...................................................................................................................... 37

8.8.1 Asynchronous Serial Interface/Three-Wire Serial I/O (UART/IOE) ......................... 38

8.8.2 Synchronous Serial Interface (CSI)............................................................................. 40

8.9 EDGE DETECTION FUNCTION..................................................................................................... 41

8.10 WATCHDOG TIMER ....................................................................................................................... 42

9. INTERRUPT FUNCTION ........................................................................................................... 43

9.1 INTERRUPT SOURCE.................................................................................................................... 43

9.2 VECTORED INTERRUPT ............................................................................................................... 45

9.3 CONTEXT SWITCHING .................................................................................................................. 4 6

9.4 MACRO SERVICE ........................................................................................................................... 46

9.5 EXAMPLES OF MACRO SERVICE APPLICATIONS .................................................................. 47

Page 5

PD784020, 784021

10. LOCAL BUS INTERFACE......................................................................................................... 49

10.1 MEMORY EXPANSION .................................................................................................................. 49

10.2 MEMORY SPACE ........................................................................................................................... 50

10.3 PROGRAMMABLE WAIT............................................................................................................... 51

10.4 PSEUDO-STATIC RAM REFRESH FUNCTION ........................................................................... 51

10.5 BUS HOLD FUNCTION .................................................................................................................. 51

11. STANDBY FUNCTION .............................................................................................................. 5 2

12. RESET FUNCTION .................................................................................................................... 53

13. INSTRUCTION SET ................................................................................................................... 54

14. ELECTRICAL CHARACTERISTICS ......................................................................................... 59

15. PACKAGE DRAWINGS ............................................................................................................ 8 0

16. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 82

APPENDIX A DEVELOPMENT TOOLS........................................................................................ 83

APPENDIX B RELATED DOCUMENTS ....................................................................................... 85

Page 6

PD784020, 784021

1. DIFFERENCES BETWEEN

PD784026 SUB-SERIES

The only difference between the mPD784020, mPD784021, mPD784025, and mPD784026 is their capacity of

internal memory, port functions, and part of their packages.

The mPD78P4026 is produced by replacing the masked ROM in the mPD784025 or mPD784026 with 64K-byte one-

time PROM or EPROM. Table 1-1 shows the differences between these products.

PD784026 Sub-Series

PD784025

Product

Item Internal ROM

Internal RAM P40-P47

P50-P57 P60-P63

P64, P65

Package

Table 1-1 Differences between the

PD784020

None

512 bytes Functions only as an address/data bus

Functions only as an address bus Can be switched to an output-only port

or address bus in units of 2 bits, by using software

Functions only as the RD or WR pin

80-pin plastic QFP (14 ¥ 14 mm)

PD784021

2048 bytes

80-pin plastic QFP (14 ¥ 14 mm)

80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm)

48K bytes (masked ROM)

Can be switched to a general-purpose port or address/data bus, by using software

Can be switched to a general-purpose port or address bus in units of 2 bits, by using software

Functions as the RD or WR pin when the local bus interface is used. Functions as a general-purpose port in other cases.

80-pin plastic QFP (14 ¥ 14 mm)

PD784026

64K bytes (masked ROM)

PD78P4026

64K bytes (one-time PROM or EPROM)

80-pin plastic QFP (14 ¥ 14 mm)

80-pin ceramic WQFN (14 ¥ 14 mm)

Page 7

PD784020, 784021

2. MAIN DIFFERENCES BETWEEN

Series

Item Number of basic instructions 113 65

(mnemonics) Minimum instruction execution 160 ns 333 ns

time (at 25 MHz) (at 12 MHz) Memory space (program/data) 1M byte in total 64K bytes/1M byte Timer/counter 16-bit timer/counter ¥ 1 16-bit timer/counter ¥ 1

8/16-bit timer/counter ¥ 2 8-bit timer/counter ¥ 2

8/16-bit timer ¥ 1 8-bit timer ¥ 1 Clock output function Available Unavailable Watchdog timer Available Unavailable Serial interface UART/IOE (3-wire serial I/O) ¥ 2 channels UART ¥ 1 channel

CSI (3-wire serial I/O, SBI) ¥ 1 channel CSI (3-wire serial I/O, SBI) ¥ 1 channel Interrupt Context switching Available Unavailable

Priority 4 levels 2 levels

Standby function 3 modes

PD784026 AND

PD784026 sub-series

(HALT, STOP, IDLE)

PD78234 SUB-SERIES

PD78234 sub-series

2 modes (HALT, STOP) Operation clock switching Selectable from fXX/2, fXX/4, fXX/8, or fXX/16 Fixed to fXX/2 Pin MODE pin Unavailable To specify ROM-less mode

functions (always in the high level for the mPD78233

or mPD78237)

TEST pin Pin for testing the device Unavailable

Low level during ordinary use

Package 80-pin plastic QFP (14 ¥ 14 mm) 80-pin plastic QFP (14 ¥ 14 mm)

80-pin plastic TQFP (fine pitch) 94-pin plastic QFP (20 ¥ 20 mm) (12 ¥ 12 mm): for the mPD784021 only 84-pin plastic QFJ (1150 ¥ 1150 mil) 80-pin ceramic WQFN (14 ¥ 14 mm): 94-pin ceramic WQFN (20 ¥ 20 mm): for the mPD78P4026 only for the mPD78P238 only

Page 8

3. PIN CONFIGURATION (TOP VIEW)

• 80-pin plastic QFP (14 ¥ 14 mm)

PD784020GC-3B9, mPD784021GC-3B9

• 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm)

PD784021GK-BE9

P31/ TxD/SO1

P30/RxD/SI1

P27/SI0

P26/INTP5

P25/INTP4/ASCK/SCK1

P24/INTP3

P23/INTP2/CI

P22/INTP1



REF3

P21/INTP0

P20/NMI



REF2

ANO1

ANO0



REF1



P77/ANI7

PD784020, 784021

P76/ANI6

P75/ANI5

P32/SCK0

P33/SO0/SB0

P34/ TO0

P35/TO1 P36/TO2 P37/TO3

RESET

X2 X1

V P00 P01 P02 P03 P04 P05 P06 P07

P67/REFRQ/HLDAK

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1 2 3 4 5 6 7



8

9 10 11 12 13 14 15 16 17 18 19 20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

A9

WR

RD

P63/A19

P62/A18

P61/A17

P60/A16

A15

A14

A13

A12

A11

A10

A8

AD7

AD6

AD5

AD4

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

AD3

P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0



V P17 P16 P15 P14/T

D2/SO2

D2/SI2

P13/R P12/ASCK2/SCK2 P11/PWM1 P10/PWM0

Note

TEST V ASTB AD0 AD1 AD2



P66/ WAIT/HLDRQ

Note Connect the TEST pin to VSS directly.

Page 9

PD784020, 784021

P00-P07 : Port 0 A8-A19 : Address bus P10-P17 : Port 1 RD : Read strobe P20-P27 : Port 2 WR : Write strobe P30-P37 : Port 3 WAIT : Wait P60-P63, P66, P67 : Port 6 HLDRQ : Hold request P70-P77 : Port 7 HLDAK : Hold acknowledge TO0-TO3 : Timer output ASTB : Address strobe CI : Clock input REFRQ : Refresh request RxD, RxD2 : Receive data RESET : Reset TxD, TxD2 : Transmit data X1, X2 : Crystal SCK0-SCK2 : Serial clock ANI0-ANI7 : Analog input ASCK, ASCK2 : Asynchronous serial clock ANO0, ANO1 : Analog output SI0-SI2 : Serial input AV SO0-SO2 : Serial output AV SB0 : Serial bus AV PWM0, PWM1 : Pulse width modulation output V NMI : Non-maskable interrupt V INTP0-INTP5 : Interrupt from peripherals TEST : Test AD0-AD7 : Address/data bus

REF1-AVREF3 : Reference voltage DD : Analog power supply

SS : Analog ground DD : Power supply SS : Ground

Page 10

4. SYSTEM CONFIGURATION EXAMPLE (PPC)

PD784021

PD784020, 784021

Serial  communication

PD27C1001A

O0-O7

A0-A7

Sensing paper transport



 Temperature of the 

fusing heater

Brightness of the lamp

Lever for adjusting  the tone of the copy

Lever for compensating  the tone of the copy

PD74HC573

Reset  circuit

Latch

RxD TxD

RDOE A17CE

A8-A16A8-A16

AD0-AD7

ASTB

INTP0 ANI0

ANI1

ANI2

ANI3

RESET

P11 P15

P16 P17

SCK1

SI1

SO1

P04 P06

P07

P66

PWM0

P00-P03

P33

P34

P35

P36

P37

Sensing paper Sensing paper feed Sensing paper ejection Sensing the position of the scanner station

Operator 

panel

High-voltage  control circuit

Fusing heater  control circuit

Lamp regulator

Driver

Drum, toner, and charge for  transfer

Fusing roller

Lamp for lighting the original Lamp for discharging

(DC stepping motor) 

Solenoid 

Main motor



Clutch for stopping 

the scanner station 

Clutch for forwarding 

the scanner station

Clutch for the resist 

shutter

Clutch for manual 

feeding

Clutch for cassette 

feeding

Page 11

5. BLOCK DIAGRAM

PD784020, 784021

NMI

INTP0-INTP5

INTP3

TO0 TO1

INTP0

INTP1

INTP2/CI

TO2 TO3

P00-P03

P04-P07

PWM0 PWM1

Programmable interrupt controller

Timer/counter 0

(16 bits)



Timer/counter 1

(16 bits)



Timer/counter 2

(16 bits)



Timer 3

(16 bits)



Real-time output port

PWM

78K/IV  CPU core

RAM

UART/IOE2

Baud-rate  generator

UART/IOE1

Baud-rate  generator

Clocked serial interface

Bus interface

Port 0

Port 1

Port 2

RxD/SI1 TxD/SO1

ASCK/SCK1

RxD2/SI2 TxD2/SO2

ASCK2/SCK2

SCK0 SO0/SB0 SI0

ASTB AD0-AD7 A8-A15 A16-A19

RD WR WAIT/HLDRQ REFRQ/HLDAK

P00-P07

P10-P17

P20-P27

ANO0 ANO1

REF2

REF3

ANI0-ANI7

REF1

INTP5

D/A converter

A/D converter

Watchdog timer

Remark The internal ROM or RAM capacity differs for each product.

Port 3

Port 6

Port 7

System control

P30-P37

P60-P63 P60, P67

P70-P77 RESET

TEST X1

 X2

Page 12

6. LIST OF PIN FUNCTIONS

6.1 PORT PINS

PD784020, 784021

P00-P07

P10 P11 P12 P13 P14 P15-P17 P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34-P37 P60-P63

P66

P67

P70-P77

I/O I/O

I/O

Input

I/O

Dual-function

—

PWM0 PWM1 ASCK2/SCK2 RxD2/SI2 TxD2/SO2

— NMI INTP0 INTP1 INTP2/CI INTP3 INTP4/ASCK/SCK1 INTP5 SI0 RxD/SI1 TxD/SO1 SCK0 SO0/SB0 TO0-TO3 A16-A19

WAIT/HLDRQ

REFRQ/HLDAK

ANI0-ANI7

Function

Port 0 (P0):

Ý 8-bit I/O port Ý Functions as a real-time output port (4 bits ¥ 2). Ý Inputs and outputs can be specified bit by bit. Ý The use of the pull-up resistors can be specified by software for the pins

in the input mode together. Ý Can drive a transistor. Port 1 (P1):

Ý 8-bit I/O port Ý Inputs and outputs can be specified bit by bit. Ý The use of the pull-up resistors can be specified by software for the pins

in the input mode together. Ý Can drive LED.

Port 2 (P2):

Ý 8-bit input-only port Ý P20 does not function as a general-purpose port (nonmaskable inter-

rupt). However, the input level can be checked by an interrupt service

routine. Ý The use of the pull-up resistors can be specified by software for pins

P22 to P27 (in units of 6 bits). Ý The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by

CSIM1. Port 3 (P3):

Ý 8-bit I/O port Ý Inputs and outputs can be specified bit by bit. Ý The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Port 6 (P6):

Ý P60 to P63 are an output-only port. Ý Inputs and outputs can be specified bit by bit for pins P66 and P67. Ý The use of the pull-up resistors can be specified by software for the pins

in the input mode together. Port 7 (P7):

Ý 8-bit I/O port Ý Inputs and outputs can be specified bit by bit.

Page 13

PD784020, 784021

6.2 NON-PORT PINS (1/2)

Pin I/O Dual-function Function TO0-TO3 Output P34-P37 Timer output CI Input P23/INTP2 Input of a count clock for timer/counter 2 RXD Input P30/SI1 Serial data input (UART0) RXD2 P13/SI2 Serial data input (UART2) TXD Output P31/SO1 Serial data output (UART0) TXD2 P14/SO2 Serial data output (UART2) ASCK Input P25/INTP4/SCK1 Baud rate clock input (UART0) ASCK2 P12/SCK2 Baud rate clock input (UART2) SB0 I/O P33/SO0 Serial data I/O (SBI) SI0 Input P27 Serial data input (3-wire serial I/O0) SI1 P30/RXD Serial data input (3-wire serial I/O1) SI2 P13/RXD2 Serial data input (3-wire serial I/O2) SO0 Output P33/SB0 Serial data output (3-wire serial I/O0) SO1 P31/TXD Serial data output (3-wire serial I/O1) SO2 P14/TXD2 Serial data output (3-wire serial I/O2) SCK0 I/O P32 Serial clock I/O (3-wire serial I/O0, SBI) SCK1 P25/INTP4/ASCK Serial clock I/O (3-wire serial I/O1) SCK2 P12/ASCK2 Serial clock I/O (3-wire serial I/O2) NMI Input P20 INTP0 P21 Ý Input of a count clock for timer/counter 1

INTP1 P22 Ý Input of a count clock for timer/counter 2

INTP2 P23/CI Ý Input of a count clock for timer/counter 2

INTP3 P24 Ý Input of a count clock for timer/counter 0

INTP4 P25/ASCK/SCK1 — INTP5 P26 AD0-AD7 I/O — Time multiplexing address/data bus (for connecting external memory) A8-A15 Output — High-order address bus (for connecting external memory) A16-A19 Output P60-P63 RD Output — Strobe signal output for reading the contents of external memory WR Output — Strobe signal output for writing on external memory WAIT Input P66/HLDRQ Wait signal insertion REFRQ Output P67/HLDAK Refresh pulse output to external pseudo static memory HLDRQ Input P66/WAIT Input of bus hold request HLDAK Output P67/REFRQ Output of bus hold response ASTB Output — Latch timing output of time multiplexing address (A0-A7) (for

External interrupt request

Ý Capture/trigger signal for CR11 or CR12

Ý Capture/trigger signal for CR22

Ý Capture/trigger signal for CR21

Ý Capture/trigger signal for CR02

Input of a conversion start trigger for A/D converter

High-order address bus during address expansion (for connecting external memory)

connecting external memory)

—

Page 14

PD784020, 784021

6.2 NON-PORT PINS (2/2)

Pin I/O Dual-function Function RESET Input — Chip reset X1 Input — Crystal input for system clock oscillation (A clock pulse can also be X2 — ANI0-ANI7 Input P70-P77 Analog voltage inputs for the A/D converter ANO0, ANO1 Output — Analog voltage inputs for the D/A converter AVREF1 — — Application of A/D converter reference voltage AVREF2, AVREF3 AVDD Positive power supply for the A/D converter AVSS Ground for the A/D converter VDD Positive power supply VSS Ground TEST Directly connect to VSS. (The TEST pin is for the IC test.)

input to the X1 pin.)

Application of D/A converter reference voltage

Page 15

PD784020, 784021

6.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS

Table 6-1 describes the types of I/O circuits for pins and the handling of unused pins. Fig. 6-1 shows the configuration of these various types of I/O circuits.

Table 6-1 Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)

Pin I/O circuit type I/O Recommended connection method for unused pins P00-P07 5-A I/O Input state : To be connected to VDD P10/PWM0 Output state: To be left open

P11/PWM1 P12/ASCK2/SCK2 8-A P13/RxD2/SI2 5-A P14/TxD2/SO2 P15-P17 P20/NMI 2 Input To be connected to VDD or VSS P21/INTP0 P22/INTP1 2-A To be connected to VDD P23/INTP2/CI P24/INTP3 P25/INTP4/ASCK/SCK1 8-A I/O Input state : To be connected to VDD

Output state: To be left open P26/INTP5 2-A Input To be connected to VDD P27/SI0 P30/RxD/SI1 5-A I/O Input state : To be connected to VDD P31/TxD/SO1 Output state: To be left open P32/SCK0 8-A P33/SO0/SB0 10-A P34/TO0-P37/TO3 5-A AD0-AD7 A8-A15 Output P60/A16-P63/A19 RD WR

Note

To be left open

P66/WAIT/HLDRQ I/O Input state : To be connected to VDD P67/REFRQ/HLDAK Output state: To be left open P70/ANI0-P77/ANI7 20 Input state : To be connected to VDD or VSS

Output state: To be left open ANO0, ANO1 12 Output To be left open ASTB 4

Note These pins function as output-only pins depending on the internal circuit, though their I/O type is 5-A.

Page 16

PD784020, 784021

Table 6-1 Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)

Pin I/O circuit type I/O Recommended connection method for unused pins RESET 2 Input — TEST 1 To be connected to VSS directly AVREF1-AVREF3 — To be connected to VSS AVSS AVDD To be connected to VDD

Caution When the I/O mode of an I/O dual-function pin is unpredictable, connect the pin to VDD through

a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when I/O is switched by software).

Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product.

(Some circuits are not included.)

Page 17

Fig. 6-1 I/O Circuits for Pins

PD784020, 784021

Type 1 Type 2-A

Type 2

Schmitt trigger input with hysteresis characteristics

Type 4

Data



Type 5-A

OUT

Output disable

Push-pull output which can output high impedance (both the positive and negative channels are off.)

Type 8-A

VDD

Type 12

Schmitt trigger input with hysteresis characteristics

Pull-up enable

Data

Output disable

Input enable

Pull-up enable

IN/OUT

Pull-up enable

Output disable

Type 10-A

Pull-up enable

Open drain Output disable

Data

VDD

IN/OUT

Type 20

IN/OUT

Input enable

Analog output voltage

Data

Output disable

Comparator

(Threshold voltage)

OUT

IN/OUT

+ –

REF

P N

Page 18

PD784020, 784021

7. CPU ARCHITECTURE

7.1 MEMORY SPACE

A 1M-byte memory space can be accessed. By using a LOCATION instruction, the mode for mapping internal data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be executed after a reset, and can be used only once.

(1) When the LOCATION 0 instruction is executed

Internal data areas are mapped to 0FD00H-0FFFFH for the

(2) When the LOCATION 0FH instruction is executed

Internal data areas are mapped to FFD00H-FFFFFH for the

PD784020 and 0F700H-0FFFFH for the mPD784021.

PD784020 and FF700H-FFFFFH for the mPD784021.

Page 19

PD784020, 784021

Note

(256 bytes)

Internal RAM 

Special function registers (SFRs)

When the LOCATION 0FH 

instruction is executed

FFFFFH

FFFDFH

FFFD0H

FFF00H

FFEFFH



FFEFFH

FFE80H

PD784020 Memory Map

Fig. 7-1

General-purpose 

0FEFFH

0FE80H

(512 bytes)

FFD00H

FFCFFH

FFE7FH

FFE2FH

registers 

(128 bytes)

FFE06H

Macro service control 

0FE7FH

0FE2FH

0FE06H

FFD00H

Data area (512 bytes)



word area (42 bytes)



0FD00H

External memory 

(1,047,808 bytes)

00FFFH

10000H

0FFFFH

00000H

00800H

007FFH



00080H

0007FH



CALLF entry area 

(2K bytes)CALLT table area 

00800H

007FFH



00080H

0007FH

(64 bytes)



Vector table area 

(64 bytes)



00040H

0003FH

00000H



External memory 

(960K bytes)



When the LOCATION 0 

instruction is executed

FFFFFH

10000H



(256 bytes)

Internal RAM 

(512 bytes)

Special function registers (SFRs)

0FFFFH

0FFDFH

0FFD0H

0FF00H

0FEFFH

0FD00H

0FCFFH

00000H



Note



External memory 

(64,768 bytes)



Note Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.

Page 20

(256 bytes)

Internal RAM 

(2,048 bytes)

Special function registers (SFRs)

When the LOCATION 0FH 

instruction is executed

External memory 

(1,046,272 bytes)

PD784020, 784021

Note

FFFFFH

FFFDFH

FFFD0H

FFF00H

FFEFFH

FF700H

FFEFFH

FFE80H

General-purpose 

PD784021 Memory Map

Fig. 7-2

registers 

0FEFFH

0FE80H

FF6FFH



FFE7FH

FFE2FH

(128 bytes)

0FE7FH

0FE2FH

FFE06H

Macro service control 

0FE06H

FFD00H

FFCFFH

FF700H

Program/data area 

(1,536 bytes)

Data area (512 bytes)



word area (42 bytes)



0FD00H



0FCFFH

0F700H

00FFFH

00800H

CALLF entry area 

00800H



Note



10000H

0FFFFH



007FFH



00080H

0007FH

(2K bytes)CALLT table area 

007FFH



00080H

0007FH



00000H



(64 bytes)



Vector table area 

(64 bytes)



00040H

0003FH



00000H



External memory 

(960K bytes)

When the LOCATION 0 

instruction is executed

FFFFFH



(256 bytes)

Internal RAM 

(2,048 bytes)

Special function registers (SFRs)

10000H

0FFFFH

0FFDFH

0FFD0H

0FF00H

0FEFFH

0FD00H

0FCFFH

0F700H

0F6FFH

External memory 

(63,232 bytes)



00000H

Note Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.

Page 21

PD784020, 784021

7.2 CPU REGISTERS

7.2.1 General-Purpose Registers

A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers.

Eight banks of this register set are provided. The user can switch between banks by software or the context switching function.

General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto internal RAM.

Fig. 7-3 General-Purpose Register Format

A (R1) X (R0)

AX (RP0)

B (R3) C (R2)

BC (RP1)

R5 R4

RP2

R7 R6

RP3

V

VVP (RG4)

UUP (RG5)

TDE (RG6)

W L (R14)

WHL (RG7)

The character strings enclosed in  parentheses represent absolute names. 

R9 R8

VP (RP4)

R11 R10

UP (RP5)

D (R13) E (R12)

DE (RP6)

H (R15)

HL (RP7)

8 banks

Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B,

AX, and BC registers, respectively. However, this function must be used only when using programs for the 78K/III series.

Page 22

PD784020, 784021

7.2.2 Control Registers

(1) Program counter (PC)

This register is a 20-bit program counter. The program counter is automatically updated by program execution.

Fig. 7-4 Format of Program Counter (PC)

19 0

(2) Program Status Word (PSW)

This register holds the CPU state. The program status word is automatically updated by program execution.

Fig. 7-5 Format of Program Status Word (PSW)

15 14 13 12

PSWH

PSW

PSWL

Note This flag is used to maintain compatibility with the 78K/III series. This flag must be set to 0 when programs

for the 78K/III series are being used.

(3) Stack pointer (SP)

This register is a 24-bit pointer for holding the start address of the stack. The high-order 4 bits must be set to 0.

PC 0 0 0 0

UF RBS2 RBS1 RBS0

76543210

Note

S Z RSS

Fig. 7-6 Format of Stack Pointer (SP)

23 20 0

AC IE P/V 0 CY

11 10 9 8

Page 23

PD784020, 784021

7.2.3 Special Function Registers (SFRs)

The special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H

Note

and 0FFFFH

Note Applicable when the LOCATION 0 instruction is executed. FFF00H-FFFFFH when the LOCATION 0FH

Caution Never attempt to access addresses in this area where no SFR is allocated. Otherwise, the

Table 7-1 lists the special function registers (SFRs). The titles of the table columns are explained below.

instruction is executed.

PD784021 may be placed in the deadlock state. The deadlock state can be cleared only by a

reset.

• Abbreviation ................... Symbol used to represent a built-in SFR. The abbreviations listed in the table are

reserved words for the NEC assembler (RA78K4). The C compiler (CC78K4) allows the abbreviations to be used as sfr variables of bit type with the #pragma sfr command.

• R/W ................................. Indicates whether each SFR allows read and/or write operations.

R/W : Allows both read and write operations. R : Allows read operations only. W : Allows write operations only.

• Manipulatable bits .......... Indicates the maximum number of bits that can be manipulated whenever an SFR is

manipulated. An SFR that supports 16-bit manipulation can be described in the sf r operand. For address specification, an even-numbered address must be specified. An SFR that supports 1-bit manipulation can be described in a bit manipulation instruction.

• When reset ..................... Indicates the state of each register when RESET is applied.

Page 24

Table 7-1 Special Function Registers (SFRs) (1/4)

PD784020, 784021

Note

Address

0FF00H Port 0 P0 R/W ll – Undefined 0FF01H Port 1 P1 ll – 0FF02H Port 2 P2 R ll – 0FF03H Port 3 P3 R/W ll – 0FF06H Port 6 P6 ll – 00H 0FF07H Port 7 P7 ll – Undefined 0FF0EH Port 0 buffer register L P0L ll – 0FF0FH Port 0 buffer register H P0H ll – 0FF10H Compare register (timer/counter 0) CR00 – – l 0FF12H Capture/compare register (timer/counter 0) CR01 – – l 0FF14H Compare register L (timer/counter 1) CR10 0FF15H Compare register H (timer/counter 1) – – – 0FF16H Capture/compare register L (timer/counter 1) CR11 0FF17H Capture/compare register H (timer/counter 1) – – – 0FF18H Compare register L (timer/counter 2) CR20 0FF19H Compare register H (timer/counter 2) – – – 0FF1AH Capture/compare register L (timer/counter 2) CR21

Special function register (SFR) name Abbreviation R/W

CR10W

CR11W

CR20W

CR21W

Manipulatable bits

1 bit 8 bits 16 bits

– ll

When reset

0FF1BH Capture/compare register H (timer/counter 2) – – – 0FF1CH Compare register L (timer 3) CR30 0FF1DH Compare register H (timer 3) – – – 0FF20H Port 0 mode register PM0 ll – FFH 0FF21H Port 1 mode register PM1 ll – 0FF23H Port 3 mode register PM3 ll – 0FF26H Port 6 mode register PM6 ll – 0FF27H Port 7 mode register PM7 ll – 0FF2EH Real-time output port control register RTPC ll – 00H 0FF30H Capture/compare control register 0 CRC0 – l – 10H 0FF31H Timer output control register TOC ll – 00H 0FF32H Capture/compare control register 1 CRC1 – l – 0FF33H Capture/compare control register 2 CRC2 – l – 10H

CR30W

– ll

Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is

executed, F0000H is added to each address.

Page 25

Table 7-1 Special Function Registers (SFRs) (2/4)

PD784020, 784021

Address

0FF36H Capture register (timer/counter 0) CR02 R – – l 0000H 0FF38H Capture register L (timer/counter 1) CR12 0FF39H Capture register H (timer/counter 1) – – – 0FF3AH Capture register L (timer/counter 2) CR22 0FF3BH Capture register H (timer/counter 2) – – – 0FF41H Port 1 mode control register PMC1 R/W ll – 00H 0FF43H Port 3 mode control register PMC3 ll – 0FF4EH Register for optional pull-up resistor PUO ll – 0FF50H Timer register 0 TM0 R – – l 0000H 0FF51H –– 0FF52H Timer register 1 TM1 TM1W – ll 0FF53H – – – 0FF54H Timer register 2 TM2 TM2W – ll 0FF55H – – – 0FF56H Timer register 3 TM3 TM3W – ll 0FF57H – – –

Note

Special function register (SFR) name Abbreviation R/W

CR12W

CR22W

Manipulatable bits

1 bit 8 bits 16 bits

– ll

When reset

0FF5CH Prescaler mode register 0 PRM0 R/W – l – 11H 0FF5DH Timer control register 0 TMC0 ll – 00H 0FF5EH Prescaler mode register 1 PRM1 – l – 11H 0FF5FH Timer control register 1 TMC1 ll– 00H 0FF60H D/A conversion value setting register 0 DACS0 – l – 0FF61H D/A conversion value setting register 1 DACS1 – l – 0FF62H D/A converter mode register DAM ll – 03H 0FF68H A/D converter mode register ADM ll – 00H 0FF6AH A/D conversion result register ADCR R – l – Undefined 0FF70H PWM control register PWMC R/W ll– 05H 0FF71H PWM prescaler register PWPR – l – 00H 0FF72H PWM modulo register 0 PWM0 – – l Undefined 0FF74H PWM modulo register 1 PWM1 – – l 0FF7DH One-shot pulse output control register OSPC ll– 00H 0FF80H Serial bus interface control register SBIC ll – 0FF82H Synchronous serial interface mode register CSIM ll –

Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is

executed, F0000H is added to each address.

Page 26

Table 7-1 Special Function Registers (SFRs) (3/4)

PD784020, 784021

Note 1

Address

0FF84H Synchronous serial interface mode register 1 CSIM1 R/W ll – 00H 0FF85H Synchronous serial interface mode register 2 CSIM2 ll – 0FF86H Serial shift register SIO – l – 0FF88H Asynchronous serial interface mode register ASIM ll – 0FF89H Asynchronous serial interface mode register 2 ASIM2 ll – 0FF8AH Asynchronous serial interface status register ASIS R ll– 0FF8BH Asynchronous serial interface status register 2 ASIS2 ll – 0FF8CH Serial receive buffer: UART0 RXB – l – Undefined

0FF8DH Serial receive buffer: UART2 RXB2 R – l –

0FF90H Baud rate generator control register BRGC – l – 00H 0FF91H Baud rate generator control register 2 BRGC2 – l – 0FFA0H External interrupt mode register 0 INTM0 ll – 0FFA1H External interrupt mode register 1 INTM1 ll –

Special function register (SFR) name Abbreviation R/W

Serial transmission shift register: UART0 TXS W – l – Serial shift register: IOE1 SIO1 R/W – l –

Serial transmission shift register: UART2 TXS2 W – l – Serial shift register: IOE2 SIO2 R/W – l –

Manipulatable bits

1 bit 8 bits 16 bits

When reset

0FFA4H Sampling clock selection register SCS0 – l – 0FFA8H In-service priority register ISPR R ll – 0FFAAH Interrupt mode control register IMC R/W ll – 80H 0FFACH Interrupt mask register 0L MK0L MK0 ll lFFFFH 0FFADH Interrupt mask register 0H MK0H ll 0FFAEH Interrupt mask register 1L MK1L ll – FFH 0FFC0H Standby control register STBC – l 0FFC2H Watchdog timer mode register WDM – l 0FFC4H Memory expansion mode register MM ll – 20H 0FFC5H Hold mode register HLDM ll – 00H 0FFC6H Clock output mode register CLOM ll – 0FFC7H Programmable wait control register 1 PWC1 – l – AAH 0FFC8H Programmable wait control register 2 PWC2 – – l AAAAH

Note 2

– 30H – 00H

Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is

executed, F0000H is added to each address.

2. A write operation can be performed only with special instructions MOV STBC,#byte and MOV WDM,#byte. Other instructions cannot perform a write operation.

Page 27

Table 7-1 Special Function Registers (SFRs) (4/4)

PD784020, 784021

Address

0FFCCH Refresh mode register RFM R/W ll – 00H 0FFCDH Refresh area specification register RFA ll – 0FFCFH Oscillation settling time specification register OSTS – l – 0FFD0H- External SFR area – ll– – 0FFDFH 0FFE0H Interrupt control register (INTP0) PIC0 ll – 43H 0FFE1H Interrupt control register (INTP1) PIC1 ll – 0FFE2H Interrupt control register (INTP2) PIC2 ll – 0FFE3H Interrupt control register (INTP3) PIC3 ll – 0FFE4H Interrupt control register (INTC00) CIC00 ll– 0FFE5H Interrupt control register (INTC01) CIC01 ll– 0FFE6H Interrupt control register (INTC10) CIC10 ll– 0FFE7H Interrupt control register (INTC11) CIC11 ll– 0FFE8H Interrupt control register (INTC20) CIC20 ll– 0FFE9H Interrupt control register (INTC21) CIC21 ll– 0FFEAH Interrupt control register (INTC30) CIC30 ll – 0FFEBH Interrupt control register (INTP4) PIC4 ll –

Note

Special function register (SFR) name Abbreviation R/W

Manipulatable bits

1 bit 8 bits 16 bits

When reset

0FFECH Interrupt control register (INTP5) PIC5 ll – 0FFEDH Interrupt control register (INTAD) ADIC ll– 0FFEEH Interrupt control register (INTSER) SERIC ll– 0FFEFH Interrupt control register (INTSR) SRIC ll –

Interrupt control register (INTCSI1) CSIIC1 ll– 0FFF0H Interrupt control register (INTST) STIC ll – 0FFF1H Interrupt control register (INTCSI) CSIIC ll – 0FFF2H Interrupt control register (INTSER2) SERIC2 ll– 0FFF3H Interrupt control register (INTSR2) SRIC2 ll –

Interrupt control register (INTCSI2) CSIIC2 ll– 0FFF4H Interrupt control register (INTST2) STIC2 ll –

Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is

executed, F0000H is added to each address.

Page 28

PD784020, 784021

8. PERIPHERAL HARDWARE FUNCTIONS

8.1 PORTS

The ports shown in Fig. 8-1 are provided to enable the application of wide-ranging control. Table 8-1 lists the

functions of the ports. For the inputs to port 0 to port 6, a built-in pull-up resistor can be specified by software.

Fig. 8-1 Port Configuration

P00

Port 0

P07

P10

Port 1

P17

P30

P37 P60

P63 P66 P67

P70

P77

Port 2P20-P27

Port 3

Port 6

Port 7

Page 29

PD784020, 784021

Table 8-1 Port Functions

Port name Pin Function Pull-up specification by software

Port 0 P00-P07 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in

• Operable as 4-bit real-time outputs input mode. (P00-P03, P04-P07)

• Capable of driving transistors

Port 1 P10-P17 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in

• Capable of driving LEDs input mode.

Port 2 P20-P27 • Input port Specified for the 6 bits (P22-P27) as a batch. Port 3 P30-P37 • Bit-by-bit input/output setting supported Specified as a batch for all pins placed in

input mode.

Port 6 P60-P63 • Output-only port

P66, P67 • Bit-by-bit input/output setting supported

Port 7 P70-P77 • Bit-by-bit input/output setting supported —

Specified as a batch for all pins placed in input mode.

8.2 CLOCK GENERATOR

A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed operation is not necessary.

Fig. 8-2 Block Diagram of Clock Generator

Oscillator



1/2 1/2 1/2 1/2

UART/IOE INTP0 noise eliminator Oscillation settling timer

Selector



CLK

CPU Peripheral circuits

Remark f

XX : Oscillator frequency or external clock input CLK : Internal operating frequency

Page 30

Fig. 8-3 Examples of Using Oscillator

(1) Crystal/ceramic oscillation

PD784021

PD784020, 784021

• When EXTC bit of OSTS = 1 • When EXTC bit of OSTS = 0

PD784021

PD74HC04, etc.

Caution When using the clock generator, to avoid problems caused by influences such as stray

capacitance, run all wiring within the area indicated by the dotted lines according to the following rules:

(2) External clock

Open

PD784021

• Minimize the wiring length.

• Wires must never cross other signal lines.

• Wires must never run near a line carrying a large varying current.

• The grounding point of the capacitor of the oscillator circuit must always be at the same

potential as V

SS. Never connect the capacitor to a ground pattern carrying a large current.

• Never extract a signal from the oscillator circuit.

Page 31

PD784020, 784021

8.3 REAL-TIME OUTPUT PORT

The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. Thus, pulse output that is free of jitter can be obtained.

Therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors) where an arbitrary pattern is output at arbitrary intervals.

As shown in Fig. 8-4, the real-time output port is built around port 0 and the port 0 buffer register (P0H, P0L).

Fig. 8-4 Block Diagram of Real-Time Output Port

Internal bus

INTP0 (externally) INTC10 (from timer/counter 1) INTC11 (from timer/counter 1)

Real-time output port  control register  (RTPC)

Output trigger

control circuit

P07

Buffer register

Output latch (P0)



P0LP0H

P00

Page 32

PD784020, 784021

8.4 TIMERS/COUNTERS

Three timer/counter units and one timer unit are incorporated. Moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units.

Table 8-2 Timer/Counter Operation

Name

Item Count pulse width 8 bits – lll

Operating mode Interval timer 2ch 2ch 2ch 1ch

Function Timer output 2ch – 2ch –

Note The one-shot pulse output function makes the level of a pulse output active by software, and makes the

level of a pulse output inactive by hardware (interrupt request signal). Note that this function differs from the one-shot timer function of timer/counter 2.

16 bits llll

External event counter lll– One-shot timer – – l –

Toggle output l – l – PWM/PPG output l – l – One-shot pulse output Real-time output – l –– Pulse width measurement 1 input 1 input 2 inputs – Number of interrupt requests 2 2 2 1

Timer/counter 0 Timer/counter 1 Timer/counter 2 Timer 3

Note

l –––

Page 33

PD784020, 784021

Timer/counter 0

fxx/8

INTP3

Timer/counter 1

fxx/8

INTP0

Prescaler

Edge detection

Prescaler

Event input

Edge detection

Fig. 8-5 Timer/Counter Block Diagram

Clear information

Timer register 0

Selector

INTP3

Selector

INTP0

(TM0)

Compare register (CR00)

Compare register (CR01)

Capture register (CR02)

Clear information

Timer register 1 (TM1/TM1M)

Compare register (CR10/CR10W)

Capture/compare register  (CR11/CR11W)

Capture register (CR12/CR12W) 

Match

Software trigger

OVF

Pulse output control

INTC00 INTC01

OVF

INTC10

To real-time  output port

INTC11

TO0

TO1

Timer/counter 2

INTP2/C1

INTP1

fxx/8

Edge detection

Prescaler

Edge detection

Timer 3

fxx/8

Remark OVF: Overflow flag

INTP2

Prescaler

Selector

INTP1

Clear information

Timer register 2 (TM2/TM2W)

Compare register (CR20/CR20W)

Capture/compare register (CR21/CR21W)

Capture register (CR22/CR22W)

Timer register 3  (TM3/TM3W)

Compare register (CR30/CR30W)

Match

Clear

Match

OVF

TO2

TO3

Pulse output control

INTC20 INTC21

CSI

INTC30

Page 34

PD784020, 784021

8.5 PWM OUTPUT (PWM0, PWM1)

Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 48.8 kHz (fCLK = 12.5 MHz) are incorporated. Low or high active level can be selected for the PWM output channels, independently of each other. This output is best suited to DC motor speed control.

Fig. 8-6 Block Diagram of PWM Output Unit

Internal bus

CLK

Prescaler

Remark n = 0, 1

 PWM modulo register

15 0

PWMn

8-bit  down-counter

1/256

8 7 4 3



Pulse control circuit

4-bit counter

PWM control register (PWMC)

Reload

control

Output control

PWMn (output pin)

Page 35

PD784020, 784021

8.6 A/D CONVERTER

An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated.

The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved. (The conversion time is about 10 ms at fCLK = 12.5 MHz.)

A/D conversion can be started in any of the following modes:

• Hardware start: Conversion is started by means of trigger input (INTP5).

• Software start : Conversion is started by means of bit setting the A/D converter mode register (ADM).

After conversion has started, one of the following modes can be selected:

• Scan mode : Multiple analog inputs are selected sequentially to obtain conversion data from all pins.

• Select mode: A single analog input is selected at all times to enable conversion data to be obtained

continuously.

ADM is used to specify the above modes, as well as the termination of conversion.

When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature, the results of conversion can be continuously transferred to memory by the macro service.

ANI0 ANI1 ANI2 ANI3 ANI4 ANI5 ANI6 ANI7

INTP5

Input selector

Edge  detector

A/D converter mode  register (ADM)

Fig. 8-7 Block Diagram of A/D Converter

Sample-and-hold circuit

Voltage comparator

Successive conver- sion register (SAR)

Conversion  trigger  

Trigger enable

Control  circuit

A/D conversion  result register (ADCR)

INTAD

Series resistor string

R/2

Tap selector

R/2

REF1

Internal bus

Page 36

PD784020, 784021

8.7 D/A CONVERTER

Two digital/analog (D/A) converter channels of voltage output type, having a resolution of 8 bits, are incorporated.

A resistor string system is used for conversion. By writing the value to be subject to D/A conversion in the 8-bit D/A conversion value setting register (DACSn: n = 0, 1), the resulting analog value is output on ANOn (n = 0, 1). The range of the output voltages is determined by the voltages applied to the AVREF2 and AVREF3 pins.

Because of its high output impedance, no current can be obtained from an output pin. When the load impedance is low, insert a buffer amplifier between the load and the converter.

The impedance of the ANOn pin goes high while the RESET signal is low. DACSn is set to 0 after a reset is released.

Fig. 8-8 Block Diagram of D/A Converter

REF2

REF3

ANOn

DACSn

Tap selector

RESET

DACEn

Internal bus

Remark n = 0, 1

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PD784020, 784021

8.8 SERIAL INTERFACE

Three independent serial interface channels are incorporated.

• Asynchronous serial interface (UART)/three-wire serial I/O (IOE) ¥ 2

• Synchronous serial interface (CSI) ¥ 1

• Three-wire serial I/O (IOE)

• Serial bus interface (SBI)

So, communication with points external to the system and local communication within the system can be performed

at the same time. (See Fig. 8-9.)

Fig. 8-9 Example Serial Interfaces

(a) UART + SBI

PD784021 (master)

PD4711A

RS-232-C  driver/ receiver

PD4711A

RS-232-C  driver/ receiver

(UART)

RxD TxD

Port

RxD2 TxD2

Port

SB0

SCK0

(SBI)

PD75402A (slave)

SB0 SCK

PD75328 (slave)

SB0 SCK

LCD

PD4711A

RS-232-C  driver/ receiver

(b) UART + Three-wire serial I/O

PD784021 (master)

(UART)

RxD TxD

Port

Note Handshake line

[Three-wire serial I/O]

SO0

SI0

SCK0

INTPm

Port

SO1

SI1

SCK1

INTPn

Port

Note

PD75108 (slave)

SI SO SCK Port

INT

PD78014 (slave)

SI SO SCK Port

INT

Page 38

PD784020, 784021

8.8.1 Asynchronous Serial Interface/Three-Wire Serial I/O (UART/IOE)

Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire serial I/O mode can be selected.

(1) Asynchronous serial interface mode

In this mode, 1-byte data is transferred after a start bit. A baud rate generator is incorporated to enable communication at a wide range of baud rates. Moreover, the frequency of a clock signal applied to the ASCK pin can be divided to define a baud rate. With the baud rate generator, the baud rate conforming to the MIDI standard (31.25 kbps) can be obtained.

Fig. 8-10 Block Diagram of Asynchronous Serial Interface Mode

Internal bus

RxD, RxD2

TxD, TxD2

Baud rate generator

ASCK, ASCK2

Selector

1/2

n+1

Receive buffer

Receive  shift register

Reception control parity  check

1/2m

RXB, RXB2

INTSR, INTSR2 INTSER, INTSER2

Transmission shift register

Transmission control parity  bit addition 

TXS, TXS2

INTST, INTST2

Remark f

XX: Oscillator frequency or external clock input

n = 0 to 11 m = 16 to 30

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PD784020, 784021

(2) Three-wire serial I/O mode

In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines (SI and SO). In general, a handshake line is required to check the state of communication.

Fig. 8-11 Block Diagram of Three-Wire Serial I/O Mode

Internal bus

Direction control  circuit

SIO1, SIO2

Shift register Output latch

SI1, SI2



SO1, SO2

SCK1, SCK2

Remark f

Serial clock counter

Serial clock control circuit

XX: Oscillator frequency or external clock input

n = 0 to 11 m = 1, 16 to 30

Interrupt signal generator

1/m 1/2

Selector

INTCSI1, INTCSI2

n+1

fXX/2

Page 40

PD784020, 784021

8.8.2 Synchronous Serial Interface (CSI)

With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock.

Fig. 8-12 Block Diagram of Synchronous Serial Interface

Internal bus

Direction control circuit

Set

Clear

SI0

SO0/SB0

Shift register

Selector

N-ch open-drain output enabled  (when SB0 or  SBI mode is used)

SIO

Output latch

Busy/ acknowledge  detection  circuit

Bus release/ command/ acknowledge detection  circuit

Remark f

Serial clock counter

Serial clock control circuit

CLK: Internal system clock frequency (system clock frequency/2)

Interrupt signal  generation  circuit

INTCSISCK0

Selector

TM 3 output/2

CLK

/32

Page 41

PD784020, 784021

(1) Three-wire serial I/O mode

This mode is designed for communication with a device incorporating a conventional synchronous serial interface. Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0). In general, a handshake line is required to check the state of communication.

(2) SBI mode

The SBI mode allows communication with more than one device via two lines: the serial clock (SCK0) and serial bus (SB0). The SBI mode is the standard NEC serial interface. A master device outputs an address through the SB0 pin to select a slave device with which communication is to be performed. After a target device is selected, commands and data are transmitted between the master device and slave device.

8.9 EDGE DETECTION FUNCTION

The interrupt input pins (NMI, INTP0-INTP5) are used to apply not only interrupt requests but also trigger signals for the built-in circuits. As these pins are triggered by an edge (rising or falling) of an input signal, a function for edge detection is incorporated. Moreover, a noise suppression function is provided to prevent erroneous edge detection caused by noise.

Pin Detectable edge Noise suppression method NMI Rising edge or falling edge Analog delay INTP0-INTP3 Rising edge or falling edge, or both edges Clock sampling INTP4, INTP5 Analog delay

Note INTP0 is used for sampling clock selection.

Note

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PD784020, 784021

8.10 WATCHDOG TIMER

A watchdog timer is incorporated for CPU runaway detection. The watchdog timer, if not cleared by software within a specified interval, generates a nonmaskable interrupt. Furthermore, once watchdog timer operation is enabled, it cannot be disabled by software. The user can specify whether priority is placed on an interrupt based on the watchdog timer or on an interrupt based on the NMI pin.

Fig. 8-13 Block Diagram of Watchdog Timer

CLK

Clear signal

Timer

CLK

Selector

INTWDT

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PD784020, 784021

9. INTERRUPT FUNCTION

Table 9-1 lists the interrupt request handling modes. These modes are selected by software.

Table 9-1 Interrupt Request Handling Modes

Handling mode Handled by Handling PC and PSW contents

Vectored interrupt Software Branches to a handling routine for execution The PC and PSW contents are pushed

(arbitrary handling). to and popped from the stack.

Context switching Automatically selects a register bank, and The PC and PSW contents are saved to

branches to a handling routine for execution and read from a fixed area in the (arbitrary handling). register bank.

Macro service Firmware Performs operations such as memory-to-I/O- Maintained

device data transfer (fixed handling).

9.1 INTERRUPT SOURCE

An interrupt can be issued from any one of the interrupt sources listed in Table 9-2: execution of a BRK instruction,

an operand error, or any of the 23 other interrupt sources.

Four levels of interrupt handling priority can be set. Priority levels can be set to nest control during interrupt handling

or to concurrently generate interrupt requests. Nested macro services, however, are performed without suspension.

When interrupt requests having the same priority level are generated, they are handled according to the default

priority (fixed). (See Table 9-2.)

Page 44

Table 9-2 Interrupt Sources

PD784020, 784021

Type

Software – BRK instruction Instruction execution – –

Nonmaskable – NMI Detection of edge input on the pin External –

Maskable 0 (highest) INTP0 Detection of edge input on the pin (TM1/TM1W capture trigger) External Enabled

Default priority

1 INTP1 Detection of edge input on the pin (TM2/TM2W capture trigger) 2 INTP2 3 INTP3 Detection of edge input on the pin (TM0 capture trigger) 4 INTC00 TM0-CR00 match signal issued Internal Enabled 5 INTC01 TM0-CR01 match signal issued 6 INTC10 TM1-CR10 match signal issued (in 8-bit operation mode)

7 INTC11 TM1-CR11 match signal issued (in 8-bit operation mode)

8 INTC20 TM2-CR20 match signal issued (in 8-bit operation mode)

9 INTC21 TM2-CR21 match signal issued (in 8-bit operation mode)

10 INTC30 TM3-CR30 match signal issued (in 8-bit operation mode)

11 INTP4 Detection of edge input on the pin External Enabled 12 INTP5 Detection of edge input on the pin 13 INTAD A/D converter processing completed (ADCR transfer) Internal Enabled 14 INTSER ASI0 reception error – 15 INTSR ASI0 reception completed or CSI1 transfer completed Enabled

16 INTST ASI0 transmission completed 17 INTCSI CSI0 transfer completed 18 INTSER2 ASI2 reception error – 19 INTSR2 ASI2 reception completed or CSI2 transfer completed Enabled

20 (lowest) INTST2 ASI2 transmission completed

Name Trigger

Operand error When the MOV STBC,#byte or MOV WDM,#byte instruction is

executed, exclusive OR of the byte operand and byte does not produce FFH.

WDT Watchdog timer overflow Internal

Detection of edge input on the pin (TM2/TM2W event counter input)

TM1W-CR10W match signal issued (in 16-bit operation mode)

TM1W-CR11W match signal issued (in 16-bit operation mode)

TM2W-CR20W match signal issued (in 16-bit operation mode)

TM2W-CR21W match signal issued (in 16-bit operation mode)

TM3W-CR30W match signal issued (in 16-bit operation mode)

INTCSI1

INTCSI2

Source

Internal/ Macro external service

Remark ASI: Asynchronous serial interface

CSI: Synchronous serial interface

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PD784020, 784021

9.2 VECTORED INTERRUPT

When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt

source is used as the branch address.

Interrupt handling by the CPU consists of the following operations :

• When a branch occurs : Push the CPU status (PC and PSW contents) to the stack.

• When control is returned: Pop the CPU status (PC and PSW contents) from the stack.

To return control from the handling routine to the main routine, use the RETI instruction. The branch destination

addresses must be within the range of 0 to FFFFH.

Table 9-3 Vector Table Address

Interrupt source Vector table address BRK instruction 003EH Operand error 003CH NMI 0002H WDT 0004H INTP0 0006H INTP1 0008H INTP2 000AH INTP3 000CH INTC00 000EH INTC01 0010H INTC10 0012H INTC11 0014H INTC20 0016H INTC21 0018H INTC30 001AH INTP4 001CH INTP5 001EH INTAD 0020H INTSER 0022H INTSR 0024H INTCSI1 INTST 0026H INTCSI 0028H INTSER2 002AH INTSR2 002CH INTCSI2 INTST2 002EH

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PD784020, 784021

9.3 CONTEXT SWITCHING

When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register bank.

The branch address must be within the range of 0 to FFFFH.

Fig. 9-1 Context Switching Caused by an Interrupt Request

0000B

PC19-16

Save

(Bits 8 to 11 of  temporary register)

Temporary register

Save

Transfer

PC15-0

Exchange

Save

AX BC

R5 R4

R7 V U

DE H

VP UP

Switching between register banks

RSS ← 0

IE ← 0

(RBS0-RBS2 ← n)

PSW

9.4 MACRO SERVICE

The macro service function enables data transfer between memory and special function registers (SFRs) without requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same transfer cycle to directly transfer data without having to perform data fetch.

Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible.

Fig. 9-2 Macro Service

CPU SFRMemory

Internal bus



Read Write

Macro service controller

Write Read

Page 47

9.5 EXAMPLES OF MACRO SERVICE APPLICATIONS

(1) Serial interface transmission

PD784020, 784021

Transmission data storage buffer (memory)

TxD

Transmission control



Data n

Data n-1

Data 2 Data 1

Internal bus

Transmission

shift register

TXS (SFR)

INTST

Each time a macro service request (INTST) is generated, the next transmission data is transferred from memory to TXS. When data n (last byte) has been transferred to TXS (that is, once the transmission data storage buffer becomes empty), a vectored interrupt request (INTST) is generated.

(2) Serial interface reception

Reception data storage buffer (memory)

Data n

Data n-1

Data 2 Data 1

Internal bus

RxD

Reception buffer

Reception  shift register

Reception control



RXB (SFR)

INTSR

Each time a macro service request (INTSR) is generated, reception data is transferred from RXB to memory. When data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes full), a vectored interrupt request (INTSR) is generated.

Page 48

PD784020, 784021

(3) Real-time output port

INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used to independently control two stepping motors. They can also be applied to PWM and DC motor control.

Output pattern profile (memory) Output timing profile (memory)

n–1



n–1

P00-P03

(SFR)

Internal bus

P0L

Output latch

Match

INTC10

Internal bus

CR10

TM1

(SFR)

Each time a macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer register (P0L) and compare register (CR10), respectively. When the contents of timer register 1 (TM1) and CR10 match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last byte) is transferred to CR10, a vectored interrupt request (INTC10) is generated. For INTC11, the same operation as that performed for INTC10 is performed.

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PD784020, 784021

10. LOCAL BUS INTERFACE

The local bus interface enables the connection of external memory and I/O devices (memory-mapped I/O). It

supports a 1M-byte memory space. (See Fig. 10-1.)

Fig. 10-1 Example of Local Bus Interface

PD784021

A16-A19

Decoder

REFRQ

AD0-AD7

Pseudo SRAM

PROM PD27C1001A

Data bus

Kanji character generator PD24C1000

ASTB

A8-A15

Latch

Address bus

Gate array for I/O  expansion including  Centronics interface  circuit, etc.

10.1 MEMORY EXPANSION

By adding external memory, program memory or data memory can be expanded, 64K bytes at a time, to

approximately 1M byte (three steps).

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PD784020, 784021

10.2 MEMORY SPACE

The 1M-byte memory space is divided into eight spaces, each having a logical address. Each of these spaces can be controlled using the programmable wait and pseudo-static RAM refresh functions.

Fig. 10-2 Memory Space

FFFFFH

512K bytes

80000H

7FFFFH

256K bytes

40000H

3FFFFH

20000H

1FFFFH

10000H

0FFFFH

0C000H

0BFFFH

08000H

07FFFH

04000H

03FFFH

00000H

128K bytes

64K bytes

16K bytes

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PD784020, 784021

10.3 PROGRAMMABLE WAIT

When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even when memory devices having different access times are connected.

In addition, an address wait function that extends the ASTB signal active period is provided to produce a longer address decode time. (This function is set for the entire space.)

10.4 PSEUDO-STATIC RAM REFRESH FUNCTION

Refresh is performed as follows:

• Pulse refresh : A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular

intervals. When the memory space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the REFRQ pin as the memory is being accessed. This can prevent the refresh cycle from suspending normal memory access.

• Power-down self-refresh : In standby mode, a low-level signal is output on the REFRQ pin to maintain the

contents of pseudo-static RAM.

10.5 BUS HOLD FUNCTION

A bus hold function is provided to facilitate connection to devices such as a DMA controller. Suppose that a bus hold request signal (HLDRQ) is received from an external bus master. In this case, upon the completion of the bus cycle being performed, the address bus, address/data bus, ASTB, RD, and WR pins are placed in the high-impedance state, and the bus hold acknowledge signal (HLDAK) is made active to release the bus for the external bus master.

While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.

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PD784020, 784021

11. STANDBY FUNCTION

The standby function allows the power consumption of the chip to be reduced. The following standby modes are

supported:

• HALT mode : The CPU operation clock is stopped. By occassionally inserting the HALT mode during normal operation, the overall average power consumption can be reduced.

• IDLE mode : The entire system is stopped, with the exception of the oscillator circuit. This mode consumes only very little more power than STOP mode, but normal program operation can be restored in almost as little time as that required to restore normal program operation from HALT mode.

• STOP mode : The oscillator is stopped. All operations in the chip stop, such that only leakage current flows.

These modes can be selected by software. A macro service can be initiated in HALT mode.

Fig. 11-1 Standby Mode Status Transition

Macro service request

End of one operation

End of macro service

Interrupt request

RESET input

Set HALT

Note 2

Macro service request

End of one operation

HALT

(standby)

Macro

service



Note 1

NMI, INTP4, INTP5 input

STOP

(standby)

Wait for 

oscillation 

settling

Set STOP

RESET input

IDLE

(standby)

Oscillation settling 

time elapses

Set IDLE

RESET input

NMI, INTP4, INTP5 input

Request for masked interrupt

Program

operation

Note 1



Notes 1. INTP4 and INTP5 are applied when not masked.

2. Only when the interrupt request is not masked

Remark NMI is enabled only by external input. The watchdog timer cannot be used to release one of the standby

modes (STOP or IDLE mode).

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12. RESET FUNCTION

Applying a low-level signal to the RESET pin initializes the internal hardware (reset status). When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC):

• Eight low-order bits of the PC : Contents of location at address 0000H

• Intermediate eight bits of the PC : Contents of location at address 0001H

• Four high-order bits of the PC : 0

The PC contents are used as a branch destination address. Program execution starts from that address. Therefore,

a reset start can be performed from an arbitrary address.

The contents of each register can be set by software, as required. The RESET input circuit contains a noise eliminator to prevent malfunctions caused by noise. This noise eliminator

is an analog delay sampling circuit.

Fig. 12-1 Accepting a Reset

Delay

RESET (input)

Internal reset signal 

For power-on reset, the RESET signal must be held active until the oscillation settling time (approximately 40 ms)

has elapsed.

Oscillation settling time Delay

RESET

(input)

Delay

Start reset

Fig. 12-2 Power-On Reset

Delay

End reset



Initialize PC



Execute instruction  at reset start address

Execute instruction at reset start address

Internal reset signal

End reset

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13. INSTRUCTION SET

(1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of

operands, where A is described as r.)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA

Table 13-1 Instructions Implemented by 8-Bit Addressing

2nd operand #byte A r saddr sfr !addr16 mem r3 [WHL+] n

r' saddr' !!addr24 [saddrp] PSWL [WHL–]

1st operand [%saddrg] PSWH

Note 6

A (MOV) (MOV) MOV

Note 1

ADD

r MOV (MOV) MOV MOV MOV MOV

ADD

saddr MOV

ADD

sfr MOV MOV MOV PUSH

ADD

!addr16 MOV (MOV) MOV !!addr24

mem MOV [saddrp] [%saddrg]

mem3 ROR4

r3 MOV MOV PSWL PSWH

B, C DBNZ STBC, WDM MOV [TDE+] (MOV)

[TDE–]

(XCH) XCH

Note 1

(ADD)

Note 1

(XCH) XCH XCH XCH XCH DIVUW (ADD)

(MOV)

Note 1

(ADD)

Note 1

(ADD)

ADD

(ADD) MOVM

(ADD)

Note 1

ADD

Note 6

MOV MOV INC

Note 1

ADD

Note 1

ADD

Note 1

Note 4

(MOV) (XCH)

Note 1

(ADD)

Note 1

ADD

Note 1

XCH DEC ADD

Note 1

MOV (MOV) MOV MOV (MOV)

Note 6

(XCH) (XCH) XCH (XCH)

Notes 1, 6

Note 1

(ADD)

ADD

Note 1

ADD

Note 1

ADD

Note 1

(ADD)

Note 5

MOVBK

ROR

Note 3

None

MULU

INC DEC

DBNZ

POP CHKL CHKLA

ROL4

Note 2

Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD.

2. There is no second operand, or the second operand is not an operand address.

3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR.

4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM.

5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK.

6. When saddr is saddr2 with this combination, an instruction with a short code exists.

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PD784020, 784021

(2) 16-bit instructions (The instructions enclosed in parentheses are implemented by a combination of

operands, where AX is described as rp.)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 13-2 Instructions Implemented by 16-Bit Addressing

2nd operand #word AX rp saddrp strp !addr16 mem [WHL+] byte n

rp' saddrp' !!addr24 [saddrp]

1st operand [%saddrg]

AX (MOVW) (MOVW) (MOVW)

Note 1

ADDW

rp MOVW (MOVW) MOVW MOVW MOVW MOVW SHRW

ADDW

saddrp MOVW

ADDW

sfrp MOVW MOVW MOVW PUSH

ADDW

!addr16 MOVW (MOVW) MOVW !!addr24

mem MOVW [saddrp] [%saddrg]

PSW PUSH

SP ADDWG

SUBWG

post PUSH

[TDE+] (MOVW) SACW byte MACW

(XCHW) (XCHW)

Note 1

(ADD)

Note 1

(XCHW) XCHW XCHW XCHW SHLW INCW

Note 1

(ADDW)

Note 3

(MOVW)

Note 1

(ADDW)

Note 1

(ADDW)

Note 1

ADDW MOVW MOVW INCW

Note 1

ADDW

Note 1

ADDW

Note 3

(MOVW) (XCHW) (ADDW)

ADDW

XCHW DECW ADDW

MOVW (MOVW) MOVW (MOVW)

Note 3

(XCHW) XCHW XCHW (XCHW)

Notes 1,3

Note 1

(ADDW)

Note 1

ADDW

Note 1

MOVTBLW

None

MULW

DECW

POP

POP PUSHU POPU

MACSW

Note 2

Note 4

Notes 1. SUBW and CMPW are the same as ADDW.

2. There is no second operand, or the second operand is not an operand address.

3. When saddrp is saddrp2 with this combination, an instruction with a short code exists.

4. MULUW and DIVUX are the same as MULW.

Page 56

PD784020, 784021

(3) 24-bit instructions (The instructions enclosed in parentheses are implemented by a combination of

operands, where WHL is described as rg.)

MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP

Table 13-3 Instructions Implemented by 24-Bit Addressing

2nd operand

1st operand

WHL (MOVG) (MOVG) (MOVG) (MOVG) (MOVG) MOVG MOVG MOVG

rg MOVG (MOVG) MOVG MOVG MOVG INCG

saddrg (MOVG) MOVG !!addr24 (MOVG) MOVG mem1 MOVG [%saddrg] MOVG SP MOVG MOVG INCG

#imm24 WHL rg saddrg !!addr24 mem1 [%saddrg] SP None

rg'

(ADDG) (ADDG) (ADDG) ADDG (SUBG) (SUBG) (SUBG) SUBG

ADDG (ADDG) ADDG DECG SUBG (SUBG) SUBG PUSH

Note There is no second operand, or the second operand is not an operand address.

Note

POP

DECG

Page 57

(4) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET

Table 13-4 Bit Manipulation Instructions Implemented by Addressing

PD784020, 784021

2nd operand CY saddr.bit sfr.bit /saddr.bit /sfr.bit None

A.bit X.bit /A.bit /X.bit PSWL.bit PSWH.bit /PSWL.bit /PSWH.bit mem2.bit /mem2.bit

1st operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit CY MOV1 AND1 NOT1

AND1 OR1 SET1 OR1 CLR1 XOR1

saddr.bit MOV1 NOT1 sfr.bit SET1 A.bit CLR1 X.bit BF PSWL.bit BT PSWH.bit BTCLR mem2.bit BFSET !addr16.bit !!addr24.bit

Note There is no second operand, or the second operand is not an operand address.

Note

Page 58

PD784020, 784021

(5) Call/return instructions and branch instructions

CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ

Table 13-5 Call/Return and Branch Instructions Implemented by Addressing

Instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None address operand

Basic BC instruction BR BR BR BR BR BR BR BR RET

Composite BF instruction BT

Note

BTCLR BFSET DBNZ

CALL CALL CALL CALL CALL CALL CALL CALLF CALLF BRKCS BRK

RETCS RETI RETCSB RETB

Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH

are the same as BC.

(6) Other instructions

ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT EI, DI, SWRS

Page 59

PD784020, 784021

14. ELECTRICAL CHARACTERISTICS

The electrical characteristics described in this chapter apply to the products which are improved versions of the

PD784020 and mPD784021 (other than K-rank products). For K-rank products yet to be improved (K-rank products),

please consult with our sales offices.

ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)

Parameter

Supply voltage

Input voltage Output voltage Low-level output current

High-level output current

A/D converter reference input voltage D/A converter reference input voltage

Operating ambient temperature Storage temperature

Symbol

VDD

AVDD

AVSS

VI VO IOL

IOH

AVREF1 AVREF2 AVREF3

Tstg

Each pin Total of all output pins Each pin Total of all output pins

Conditions

Rating

–0.5 to +7.0

AVSS to VDD + 0.5

–0.5 to +0.5 –0.5 to VDD + 0.5 –0.5 to VDD + 0.5

15 150 –10

–100 –0.5 to VDD + 0.3 –0.5 to VDD + 0.3 –0.5 to VDD + 0.3

–40 to +85

–65 to +150

Unit

V V V V

V mA mA mA mA

°C °C

Caution Absolute maximum ratings are rated values beyond which some physical damages may be

caused to the product; if any of the parameters in the table above exceeds its rated value even for a moment, the quality of the product may deteriorate. Be sure to use the product within the rated values.

Page 60

OPERATING CONDITIONS

• Operating ambient temperature (TA): –40 to +85 °C

• Rising and falling time (tr, tf) (for pins not especially specified): 0 to 200

• Power supply voltage and clock cycle time: See Fig. 14-1.

Fig. 14-1 Relationship between Power Supply Voltage and Clock Cycle Time

10000

4000

[ns]

1000

CYK

125 100

Clock cycle time t

Operation  guarantee  range

PD784020, 784021

CAPACITANCE (T

Parameter Input capacitance Output capacitance I/O capacitance

01234567

A = 25 °C, VDD = VSS = 0 V)

CI CO CIO

f = 1 MHz 0 V on pins other than measured pins

Power supply voltage [V]

Conditions

Typ.Min.Symbol

Max.

10 10 10

Unit

pF pF pF

Page 61

PD784020, 784021

OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 4.5 to 5.5 V, VSS = 0 V)

Resonator

Ceramic resonator or crystal

External clock

Recommended circuit Min.

Oscillator frequency (fXX)

X1 X2V

C1 C2

X1 input frequency (fX)

X1 X2

HCMOS Inverter

X1 input rising and falling times (tXR, tXF)

X1 input high-level and lowlevel widths (tWXH, tWXL)

Parameter

Max.

125

Unit

MHz

Caution When using the system clock generator, run wires in the portion surrounded by dotted lines

according to the following rules to avoid effects such as stray capacitance:

• Minimize the wiring.

• Never cause the wires to cross other signal lines.

• Never cause the wires to run near a line carrying a large varying current.

• Cause the grounding point of the capacitor of the oscillator circuit to have the same potential

SS. Never connect the capacitor to a ground pattern carrying a large current.

as V

• Never extract a signal from the oscillator.

Page 62

OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = 2.7 to 5.5 V, VSS = 0 V)

PD784020, 784021

Resonator

Ceramic resonator or crystal

External clock

Recommended circuit Min.

Oscillator frequency (fXX)

X1 X2V

C1 C2

X1 input frequency (fX)

X1 X2

HCMOS Inverter

X1 input rising and falling times (tXR, tXF)

X1 input high-level and lowlevel widths (tWXH, tWXL)

Parameter

Max.

125

Unit

MHz

Caution When using the system clock generator, run wires in the portion surrounded by dotted lines

according to the following rules to avoid effects such as stray capacitance:

• Minimize the wiring.

• Never cause the wires to cross other signal lines.

• Never cause the wires to run near a line carrying a large varying current.

• Cause the grounding point of the capacitor of the oscillator circuit to have the same potential

SS. Never connect the capacitor to a ground pattern carrying a large current.

as V

• Never extract a signal from the oscillator.

Page 63

PD784020, 784021

DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AV DD = 2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)

Parameter

Low-level input voltage

High-level input voltage

Low-level output voltage

High-level output voltage

X1 low-level input current X1 high-level input current

Symbol

VIL1

VIL2 VIL3

VIH1 VIH2 VIH3

VOL1 VOL2

VOH1 VOH2

IIL IIH

Conditions

Pins other than those described in Notes 1, 2, 3, and 4

Pins described in Notes 1, 2, 3, and 4 VDD = +5.0 V ±10 % Pins described in Notes 2, 3, and 4 Pins other than those described in Note 1 Pins described in Note 1 VDD = +5.0 V ±10 % Pins described in Notes 2, 3, and 4 IOL = 2 mA VDD = +5.0 V ±10 % IOL = 8 mA Pins described in Notes 2 and 5 IOH = –2 mA VDD = +5.0 V ±10 % IOH = –5 mA Pins described in Note 4 0 V £ VI £ VIL2 VIH2 £ VI £ VDD

Min. –0.3

–0.3 –0.3

0.7VDD

0.8VDD

2.2

VDD – 1.0

2.0

Typ. Max.

0.3VDD

0.2VDD +0.8

VDD + 0.3 VDD + 0.3 VDD + 0.3

0.4

1.0

–30 +30

Unit

V V

V V V

V V

A A

Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P13/RxD2/SI2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI,

P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P30/RxD/SI1, P32/SCK0, P33/SO0/SB0, and TEST

2. AD0 to AD7 and A8 to A15

3. P60/A16 to P63/A19, RD, WR, P66/WAIT/HLDRQ, and P67/REFRQ/HLDAK

4. P00 to P07

5. P10 to P17

Page 64

PD784020, 784021

DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AV DD = 2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)

Parameter

Input leakage current

Output leakage current VDD supply current

Pull-up resistance

Symbol

ILI

ILO IDD1

IDD2

IDD3

Conditions 0 V £ VI £ VDD Except for the X1 pin when EXTC = 0 0 V £ VI £ VDD Analog input pins 0 V £ VO £ VDD Operating mode fXX = 25 MHz

fXX = 16 MHz VDD = 2.7 to 5.5 V

HALT mode fXX = 25 MHz

fXX = 16 MHz

VDD = 2.7 to 5.5 V IDLE mode fXX = 25 MHz (EXTC = 0) fXX = 16 MHz

VDD = 2.7 to 5.5 V VI = 0 V VDD = +5.0 V ±10 % VI = 0 V VDD = 2.7 to 4.5 V

Min.

Typ.

40 12

Max. ±10

±3

±10

60 25

30 12

100

160

Unit

mA mA

Page 65

PD784020, 784021

AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)

(1) Read/write operation (1/2)

Parameter

Address setup time

ASTB high-level width

Address hold time (referred to ASTBØ) Address hold time (referred to RD•) Address Æ RDØ delay time

Address float time (referred to RDØ) Address Æ data input time

ASTBØ Æ data input time

RDØ Æ data input time

ASTBØ Æ RDØ delay time Data hold time (referred to RD•) RD• Æ address active time

RD• Æ ASTB• delay time RD low-level width

Address hold time (referred to WR•) Address Æ WRØ delay time

ASTBØ Æ data output delay time

ASTBØ Æ data output time ASTBØ Æ WRØ output delay time

Symbol

tSAST

tWSTH

tHSTLA

tHRA

tDAR

tFRA

tDAID

tDSTID

tDRID

tDSTR tHRID

tDRA

tDRST tWRL

tHWA

tDAW

tDSTOD

tDWOD tDSTW

Conditions

VDD = +5.0 V ±10 %

Upon program VDD = +5.0 V ±10 % read Upon data read VDD = +5.0 V ±10 %

VDD = +5.0 V ±10 %

Min. (0.5 + a) T – 11 (0.5 + a) T – 15 (0.5 + a) T – 17 (0.5 + a) T – 40

0.5T – 24

0.5T – 34

0.5T – 14

(1 + a) T – 5

(1 + a) T – 10

0.5T – 9 0

0.5T – 2

0.5T – 12

1.5T – 2

1.5T – 12

0.5T – 9

(1.5 + n) T – 30 (1.5 + n) T – 40

0.5T – 14

(1 + a) T – 5

(1 + a) T – 10

0.5T – 9

Max.

(2.5 + a + n) T – 37 (2.5 + a + n) T – 52 (2 + n) T – 40

(2 + n) T – 60 (1.5 + n) T – 50 (1.5 + n) T – 70

0.5T + 15

0.5T + 20

0.5T – 11

Unit

ns ns ns ns ns ns ns

ns ns ns

ns ns ns ns ns ns ns ns

ns ns ns ns ns ns

Remark T: T

a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n • 0)

CYK (system clock cycle time)

Page 66

(1) Read/write operation (2/2)

PD784020, 784021

Parameter Data setup time (referred to WR•) Data hold time (referred to WR•) WR• Æ ASTB• delay time WR low-level width

Note

Symbol

tSODW

tHWOD

tDWST tWWL

VDD = +5.0 V ±10 %

Note The hold time includes the time for holding V

4.7 kW.

Remark T: T

CYK (system clock cycle time)

n: number of wait cycles (n • 0)

(2) Bus hold timing

Parameter

HLDRQ• Æ float delay time HLDRQ• Æ HLDAK• delay time

Float Æ HLDAK• delay time HLDRQØ Æ HLDAKØ delay time

HLDAKØ Æ active delay time

Symbol

tFHQC tDHQHHAH

tDCFHA tDHQLHAL

tDHAC

VDD = +5.0 V ±10 %

Min. (1.5 + n) T – 30 (1.5 + n) T – 40

0.5T – 5

0.5T – 14

0.5T – 9 (1.5 + n) T – 30 (1.5 + n) T – 40

OH1 and VOL1 on the load conditions of CL = 50 pF and RL =

Conditions

Min.

1T – 20 1T – 30

Max.Conditions

Max. (6 + a + n) T + 50 (7 + a + n) T + 30 (7 + a + n) T + 40

1T + 30 2T + 40 2T + 60

Unit

ns ns ns ns ns ns ns

Unit

ns ns ns ns ns ns ns ns

Remark T: T

CYK (system clock cycle time)

a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n • 0)

Page 67

(3) External wait timing

PD784020, 784021

Parameter

Address Æ WAITØ input time

ASTBØ Æ WAITØ input time

ASTBØ Æ WAIT hold time

ASTBØ Æ WAIT• delay time

RDØ Æ WAITØ input time

RDØ Æ WAITØ hold time

RDØ Æ WAIT• delay time

WAIT• Æ data input time

WAIT• Æ WR• delay time WAIT• Æ RD• delay time WRØ Æ WAITØ input time

WRØ Æ WAIT hold time

WRØ Æ WAIT• delay time

Symbol

tDAWT

tDSTWT

tHSTWTH

tDSTWTH

tDRWTL

tHRWT

tDRWTH

tDWTID

tDWTW tDWTR tDWWTL

tHWWT

tDWWTH

Conditions

VDD = +5.0 V ±10 %

Min.

(0.5 + n) T + 5

(0.5 + n) T + 10

nT + 5

nT + 10

0.5T

nT + 5

nT + 10

Max. (2 + a) T – 40 (2 + a) T – 60

1.5T – 40

1.5T – 60

(1.5 + n) T – 40 (1.5 + n) T – 60

T – 50 T – 70

(1 + n) T – 40 (1 + n) T – 60

0.5T – 5

0.5T – 10

T – 50 T – 75

(1 + n) T – 40 (1 + n) T – 60

Unit

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Remark T: T

CYK (system clock cycle time)

a: 1 when address wait is applied, 0 in other cases n: number of wait cycles (n • 0)

(4) Refresh timing

Parameter Random read/write cycle time REFRQ low-level pulse width

ASTBØ Æ REFRQ delay time RD• Æ REFRQ delay time WR• Æ REFRQ delay time REFRQ• Æ ASTB delay time REFRQ high-level pulse width

Symbol

tRC tWRFQL

tDSTRFQ tDRRFQ tDWRFQ tDRFQST tWRFQH

VDD = +5.0 V ±10 %

Remark T: TCYK (system clock cycle time)

Min.

1.5T – 25

1.5T – 30

0.5T – 9

1.5T – 9

0.5T – 9

1.5T – 25

1.5T – 30

Max.Conditions

Unit

ns ns ns ns ns ns ns ns ns

Page 68

SERIAL OPERATION (CSI)

PD784020, 784021

Parameter Serial clock cycle time (SCK0)

Serial clock low-level width (SCK0)

Serial clock high-level width (SCK0)

SI0, SB0 setup time (referred to SCK0•) SI0, SB0 hold time (referred to SCK0•) SO0, SB0 output delay time (referred to SCK0Ø)

SO0, SB0 output hold time (referred to SCK0•) SB0 high hold time (referred to SCK0•) SB0 low setup time (referred to SCK0Ø) SB0 low-level width SB0 high-level width

Symbol

tCYSK0

tWSKL0

tWSKH0

tSSSK0

tHSSK0

tDSBSK1

tDSBSK2

tHSBSK1

tHSBSK2

tSSBSK

tWSBL tWSBH

Conditions

Input VDD = +5.0 V ±10 %

Output Input VDD = +5.0 V ±10 %

Output

CMOS push-pull output (three-wire serial I/O mode) Open-drain output (SBI mode), RL = 1 kW During data transfer

SBI mode

Min.

500

1000

T 210 460

0.5T – 40 210 460

0.5T – 40

0.5TCYSK0 – 40

4 4

Max.

150

400

Unit

ns ns ns ns ns ns ns ns ns ns

tCYX

tCYX tCYX

Remarks 1. The values listed in the above table are obtained when f

CYX = 1/fXX

2. t

3. T: Serial clock frequency specified using software. The minimum value is 16/fXX.

XX = 25 MHz and CL = 100 pF.

Page 69

SERIAL OPERATION (IOE1, IOE2)

PD784020, 784021

Parameter Serial clock cycle time (SCK1, SCK2)

Serial clock low-level width (SCK1, SCK2)

Serial clock high-level width (SCK1, SCK2)

SI1, SI2 setup time (referred to SCK1, SCK2•) SI1, SI2 hold time (referred to SCK1, SCK2•) SO1, SO2 output delay time (referred to SCK1, SCK2Ø) SO1, SO2 output hold time (referred to SCK1, SCK2•)

Symbol

tCYSK1

tWSKL1

tWSKH1

tSSSK1

tHSSK1

tDSOSK

tHSOSK

Conditions

Input VDD = +5.0 V ±10 %

Output Internal clock divided by 16 Input VDD = +5.0 V ±10 %

Output Internal clock divided by 16

During data transfer

Min.

250 500

210

0.5T – 40 85

210

0.5T – 40 40

0.5TCYSK1 – 40

Max.

Unit

ns ns ns ns ns ns ns ns ns ns

Remarks 1. The values listed in the above table are obtained when C

2. T: Serial clock frequency specified using software. The minimum value is 16/f

SERIAL OPERATION (UART, UART2)

Parameter

ASCK clock input cycle time

ASCK clock low-level width

ASCK clock high-level width

Symbol

tCYASK

tWASKL

tWASKH

VDD = +5.0 V ±10 %

L = 100 pF.

Min.

125 250

52.5 85

XX.

Max.Conditions

Unit

ns ns ns ns ns ns

Page 70

OTHER OPERATIONS

PD784020, 784021

Parameter NMI low-level width NMI high-level width INTP0 low-level width INTP0 high-level width INTP1-INTP3 and CI low-

level width INTP1-INTP3 and CI high-

level width INTP4 and INTP5 low-level

width INTP4 and INTP5 high-level

width RESET low-level width RESET high-level width

Remark t

CYSMP: sampling clock specified using software CYCPU: CPU operating clock specified using CPU software

Symbol

tWNIL tWNIH tWIT0L tWIT0H tWIT1L

tWIT1H

tWIT2L

tWIT2H

tWRSL tWRSH

Min.

10 3tCYSMP + 10 3tCYSMP + 10 3tCYCPU + 10

3tCYCPU + 10

Max.Conditions

Unit

ns ns ns

s s

A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = 3.4 to 5.5 V, +3.4 V £ AVREF1 £ AVDD,

SS = AVSS = 0 V)

Parameter Resolution Total error

Linearity calibration Quantization error Conversion time

Sampling time

Analog input voltage Analog input impedance AVREF1 current AVDD supply current

Note

Symbol

tCONV

tSAMP

VIAN RAN AIREF1 AIDD1 AIDD2

Conditions

VDD = AVDD = +5.0 V ±10 % +3.4 V £ AV REF1 £ AVDD +2.7 V £ VDD = AVDD £ +3.3 V +2.5 V £ AV REF1 £ AVDD

tCYK £ 500 ns, FR = 1 tCYK £ 500 ns, FR = 0 tCYK £ 500 ns, FR = 1 tCYK £ 500 ns, FR = 0

fXX = 25 MHz STOP mode, CS = 0

Min.

120 180

24 36

–0.3

Typ.

1000

0.5

2.0

Max.

1.2

1.0

0.6

±1/2

AVREF1 + 0.3

1.5

5.0 20

Unit

bit % %

LSB

tCYK tCYK tCYK tCYK

V MW mA mA

Note Quantization error is excluded. The error is represented in percent with respect to a full-scale value.

Remark t

CYK: system clock cycle time

Page 71

PD784020, 784021

D/A CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, AVREF2 = VDD = AVDD = 2.7 to 5.5 V, AVREF3 = V SS

= AVSS = 0 V)

Parameter Resolution Total error

Settling time Output resistance Analog reference voltage

Reference supply input current

Note

Symbol

RO AVREF2 AVREF3 AIREF2 AIREF3

Conditions

Load condition: VDD = 4.5 to 5.5 V 4 MW, 30 pF

VDD = 4.5 to 5.5 V AVREF2 = 0.75VDD AVREF3 = 0.25VDD AVREF2 = 0.75VDD

AVREF3 = 0.25VDD Load condition: VDD = 4.5 to 5.5 V 2 MW, 30 pF

VDD = 4.5 to 5.5 V

AVREF2 = 0.75VDD

AVREF3 = 0.25VDD

AVREF2 = 0.75VDD

AVREF3 = 0.25VDD Load condition: 2 MW, 30 pF

Note

Min.

0.75VDD 0 0

–5

Typ.

Max.

0.4

0.6

0.8

0.6

0.8

1.0

VDD

0.25VDD 5 0

Unit

bit

% % %

V mA mA

Note DACS0, DACS1 = 7FH

Page 72

DATA RETENTION CHARACTERISTICS (TA = –40 to +85 °C)

PD784020, 784021

Parameter Data retention voltage Data retention current

VDD rising time VDD falling time VDD retention time (referred to STOP mode setting) STOP release signal input time Oscillation settling time

Low-level input voltage High-level input voltage

Symbol

VDDDR IDDDR

tRVD tFVD tHVD

tDREL tWAIT

VIL VIH

Conditions STOP mode VDDDR = 2.5 to 5.5 V VDDDR = 2.5 V

Crystal Ceramic resonator Specified pins

Note 1

Note 2

Note 1

Notes 1. When the input voltage for the pins described in Note 2 satisfies the V

table

2. Pins RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, and P33/SO0/SB0

AC Timing Test Points

Min.

2.5

200 200

5 0

0.9VDDDR

Typ.

IL and VIH conditions in the above

Max.

5.5 50 10

0.1VDDDR VDDDR

Unit

ms ms ms

V V

A A

s s

VDD – 1 V

0.45 V

0.8V

0.8 V

or 2.2 V

Test points

0.8V

or 2.2 V

0.8 V

Page 73

Timing Waveform

(1) Read operation

ASTB

A8-A19

AD0-AD7

WSTH

SAST

DAR

DSTR

HSTLA

DAID

DSTID

PD784020, 784021

DRST

HRA

FRA

DRID

HRID

DRA

(2) Write operation

ASTB

A8-A19

AD0-AD7

WSTH

SAST

DAW

DSTW

HSTLA

DSTOD

DWOD

WRL

DSODW

DWST

HWA

HWOD

WWL

Page 74

Hold Timing

ASTB, A8-A19,

AD0-AD7, RD, WR

FHQC

HLDRQ

DHQHHAH

HLDAK

External WAIT Signal Input Timing

(1) Read operation

ASTB

DSTWT

DCFHA

DSTWTH

HSTWTH

DHQLHAL

PD784020, 784021

DHAC

A8-A19

AD0-AD7

WAIT

(2) Write operation

ASTB

A8-A19

AD0-AD7

DAWT

DSTWT

DRWTL

DSTWTH

HSTWTH

HRWT

DRWTH

DWTID

DWTR

WAIT

DAWT

DWWTL

HWWT

DWWTH

DWTW

Page 75

Timing Waveform for Refresh

(1) Random read/write cycle

ASTB

(2) When a refresh is performed simultaneously with a memory access

ASTB

PD784020, 784021

RD, WR

REFRQ

(3) Refresh after reading

ASTB

REFRQ

(4) Refresh after writing

DSTRFQ

WRFQL

DRFQST

WRFQH

DRRFQ

WRFQL

DRFQST

ASTB

REFRQ

DWRFQ

WRFQL

DRFQST

Page 76

Serial Operation (CSI)

(1) Three-wire serial I/O mode

SCK

WSKL0

CYSK0

WSKH0

SSSK0tHSSK0

PD784020, 784021

(2) SBI mode

Ý Bus release signal transfer

SCK

HSBSK2

SB0

Ý Command signal transfer

SCK

tHSBSK2 tSSBSK

SB0

WSBL

WSBH

DSBSK1

Output data

SSBSK

WSKL0

HSBSK1

CYSK0

WSKH0

DSBSK2

Input data

HSSK0

SSSK0

HSBSK1

Input/Output data

Page 77

Serial Operation (IOE1, IOE2)

PD784020, 784021

WSKL1

SCK

Serial Operation (UART, UART2)

ASCK,

ASCK2

CYSK1

WSKH1

WASKH

0.8V

0.8 V

DSOSK

Output data

CYASK

WASKL

HSOSK

SSSK1tHSSK1

Input data

Page 78

Interrupt Input Timing

NMI

INTP0

CI,

INTP1-INTP3

WIT0H

WIT1H

WNIH

0.8V

0.8 V

PD784020, 784021

WNIL

WIT0L

WIT1L

INTP4, INTP5

Reset Input Timing

RESET

WIT2H

WRSH

0.8V

0.8 V

WIT2L

WRSL

Page 79

External Clock Timing

0.8V

0.8 V

Data Retention Timing

Set STOP mode.

PD784020, 784021

WXH

CYX

WXL

VDD

tHVD tFVD

RESET

NMI

(Released by a falling edge)

NMI

(Released by a rising edge)

DDDR

tRVD

tDREL

0.8VDD

0.8V

tWAIT

0.8 V

Page 80

15. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14×14)

PD784020, 784021

A B

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

detail of lead end

ITEM MILLIMETERS INCHES

A 17.2±0.4 0.677±0.016 B 14.0±0.2 0.551

C 14.0±0.2 0.551 D 17.2±0.4 0.677±0.016

F 0.825 0.032 G 0.825 0.032

H 0.30±0.10 0.012

I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.6±0.2 0.063±0.008

L 0.8±0.2 0.031

M 0.15 0.006 N 0.10 0.004

P 2.7 0.106 Q 0.1±0.1 0.004±0.004 R5°±5° 5°±5° S 3.0 MAX. 0.119 MAX.

 



 



+0.10



–0.05



+0.009 

–0.008 

+0.009 

–0.008



+0.004 

–0.005



+0.009 

–0.008 +0.004

 –0.003



S80GC-65-3B9-4

Remark The shape and material of the ES version are the same as those of the corresponding mass-produced

products.

Page 81

80 PIN PLASTIC TQFP (FINE PITCH) ( 12)

ITEM MILLIMETERS INCHES

J 0.5 (T.P.)

0.10

0.004

0.020 (T.P.)

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.

A 14.0±0.2 0.551

+0.009 –0.008

B 12.0±0.2 0.472

+0.009 –0.008

C 12.0±0.2 0.472

+0.009 –0.008

D 14.0±0.2 0.551

+0.009 –0.008

G 1.25

1.25

0.049

H 0.22 0.009±0.002



P80GK-50-BE9-4

S 1.27 MAX. 0.050 MAX.

K 1.0±0.2 0.039

+0.009 –0.008

L 0.5±0.2 0.020

+0.008 –0.009

M 0.145 0.006±0.002

N 0.10 0.004 P 1.05 0.041



Q 0.05±0.05

0.002±0.002

R 5°±5° 5°±5°

+0.05 –0.04

+0.055

–0.045

detail of lead end

PD784020, 784021

Remark The shape and material of the ES version are the same as those of the corresponding mass-produced

products.

Page 82

16. RECOMMENDED SOLDERING CONDITIONS

The conditions listed below shall be met when soldering the mPD784021. For details of the recommended soldering conditions, refer to our document

Manual

(C10535E)

Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under

different conditions.

Table 16-1 Soldering Conditions for Surface-Mount Devices

PD784020GC-3B9: 80-pin plastic QFP (14 ¥ 14 mm)

(1)

mm mm

PD784021GC-3B9: 80-pin plastic QFP (14

¥¥

¥ 14 mm)

¥¥

PD784020, 784021

SMD Surface Mount Technology

Soldering process

Infrared ray reflow

VPS

Wave soldering

Partial heating method

PD784021GK-BE9: 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm)

(2)

Soldering process

Infrared ray reflow

VPS

Partial heating method

Peak package’s surface temperature: 235 ½C Reflow time: 30 seconds or less (at 210 ½C or more) Maximum allowable number of reflow processes: 3

Peak package’s surface temperature: 215 ½C Reflow time: 40 seconds or less (at 210 ½C or more) Maximum allowable number of reflow processes: 3

Solder temperature: 260 ½C or less Flow time: 10 seconds or less Number of flow process: 1 Preheating temperature: 120 ½C max. (measured on the package surface)

Terminal temperature: 300 ½C or less Flow time: 3 seconds or less (for each side of device)

Peak package’s surface temperature: 235 ½C Reflow time: 30 seconds or less (at 210 ½C or more) Maximum allowable number of reflow processes: 2 Exposure limit

Non-heat resistant trays, such as magazine and taping trays, cannot

be baked before unpacking. Peak package’s surface temperature: 215 ½C

Reflow time: 40 seconds or less (at 200 ½C or more) Maximum allowable number of reflow processes: 2 Exposure limit

Non-heat resistant trays, such as magazine and taping trays, cannot

be baked before unpacking. Terminal temperature: 300 ½C or less

Flow time: 3 seconds or less (for each side of device)

Note

Soldering conditions

: 7 days (10 hours of pre-baking is required at

125 ½C afterward.)

: 7 days (10 hours of pre-baking is required at

125 ½C afterward.)

Symbol

IR35-00-3

VP15-00-3

WS60-00-1

–

Symbol

IR35-107-2

VP15-107-2

–

Note Exposure limit before soldering after dry-pack package is opened.

Storage conditions: Temperature of 25 ½C and maximum relative humidity at 65 % or less

Caution Do not apply more than a single process at once, except for “Partial heating method.”

Page 83

PD784020, 784021

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for system development using the mPD784021.

Language Processing Software

RA78K4 CC78K4 CC78K4-L

Note 1

Assembler package for all 78K/IV series models C compiler package for all 78K/IV series models C compiler library source file for all 78K/IV series models

PROM Write Tools

PG-1500 PROM programmer PA-78P4026GC Programmer adaptor, connects to PG-1500

PA-78P4038GK PA-78P4026KK

PG-1500 controller

Note 2

Control program for PG-1500

Debugging Tools

IE-784000-R In-circuit emulator for all mPD784026 sub-series models IE-784000-R-BK Break board for all 78K/IV series models

IE-784026-R-EM1 Emulation board for evaluating mPD784026 sub-series models IE-784000-R-EM

IE-70000-98-IF-B Interface adapter when the PC-9800 series computer (other than a notebook)

IE-70000-98N-IF Interface adapter and cable when a PC-9800 series notebook is used as the

IE-70000-PC-IF-B Interface adapter when the IBM PC/ATTM is used as the host machine IE-78000-R-SV3 Interface adapter and cable when the EWS is used as the host machine

is used as the host machine

host machine

EP-78230GC-R Emulation probe for 80-pin plastic QFP (14 ¥ 14 mm) for all mPD784026

EP-78054GK-R Emulation probe for 80-pin plastic TQFP (fine pitch) (12 ¥ 12 mm) for all

EV-9200GC-80 Socket for mounting on target system board made for 80-pin plastic QFP

EV-9500GK-80 Adapter for mounting on target system board made for 80-pin plastic TQFP

EV-9900 Tool used to remove the mPD78P4026KK-T from the EV-9200GC-80 SM78K4 ID78K4

DF784026

Note 3

Note 4

sub-series

PD784021

(14 ¥ 14 mm)

(fine pitch) (12 ¥ 12 mm)

System simulator for all 78K/IV series models Integrated debugger for IE-784000-R

Device file for all mPD784026 sub-series models

Real-time OS

RX78K/IV MX78K4

Note 4

Note 2

Real-time OS for 78K/IV series models OS for all 78K/IV series models

Remark The RA78K4, CC78K4, SM78K4, and ID78K4 are used with the DF784026.

Page 84

Notes 1. • Based on PC-9800 series (MS-DOSTM)

• Based on IBM PC/AT and compatibles (PC DOS

• Based on HP9000 series 700

• Based on SPARCstation

• Based on NEWS

• Based on PC-9800 series (MS-DOS)

(NEWS-OSTM)

(SunOSTM)

(HP-UXTM)

• Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS)

• Based on PC-9800 series (MS-DOS + Windows)

• Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS)

• Based on HP9000 series 700 (HP-UX)

• Based on SPARCstation (SunOS)

• Based on PC-9800 series (MS-DOS)

• Based on IBM PC/AT and compatibles (PC DOS, Windows, MS-DOS, and IBM DOS)

• Based on HP9000 series 700 (HP-UX)

• Based on SPARCstation (SunOS)

PD784020, 784021

, WindowsTM, MS-DOS, and IBM DOSTM)

Page 85

APPENDIX B RELATED DOCUMENTS

Documents Related to Devices

PD784020, 784021

Document name

PD784020, 784021 Data Sheet U11514J This manual

PD784025, 784026 Data Sheet

PD78P4026 Data Sheet

PD784026 Sub-Series User's Manual, Hardware U10898J U10898E

PD784026 Sub-Series Special Function Registers U10593J —

PD784026 Sub-Series Application Note, Hardware Basic U10573J 78K/IV Series User's Manual, Instruction U10905J IEU-1386 78K/IV Series Instruction Summary Sheet U10594J — 78K/IV Series Instruction Set U10595J —

78K/IV Series Application Note, Software Basic U10095J —

To be released soon To be released soon

Document No.

Japanese English

IP-3230

IP3231

—

Documents Related to Development Tools (User’s Manual)

Document name

RA78K Series Assembler Package Operation EEU-809 EEU-1399

Language EEU-815 EEU-1404 RA78K Series Structured Assembler Preprocessor EEU-817 EEU-1402 CC78K Series C Compiler Operation EEU-656 EEU-1280

Language EEU-655 EEU-1284 CC78K Series Library Source File EEU-777 — PG-1500 PROM Programmer EEU-651 EEU-1335 PG-1500 Controller PC-9800 Series (MS-DOS) Base EEU-704 EEU-1291 PG-1500 Controller IBM PC Series (PC DOS) Base EEU-5008 U10540E IE-784000-R EEU-5004 EEU-1534 IE-784026-R-EM1 EEU-5017 EEU-1528 EP-78230 EEU-985 EEU-1515 EP-78054GK-R EEU-932 EEU-1468 SM78K4 System Simulator Windows Base Reference U10093J U10093E SM78K Series System Simulator

ID78K4 Integrated Debugger Reference U10440J U10440E

External Parts User Open

Interface Specifications

Document No.

Japanese English

U10092J U10092E

Caution The above documents may be revised without notice. Use the latest versions when you design

application systems.

Page 86

Documents Related to Software to Be Incorporated into the Product (User’s Manual)

PD784020, 784021

Document name

78K/IV Series Real-Time OS Basic U10603J —

Installation U10604J — Debugger U10364J —

OS for 78K/IV Series MX78K4 To be created —

Datasheet UPD784021GK-BE9, UPD784021GC-3B9, UPD784020GC-3B9 Datasheet (NEC)

78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM

FUNCTIONS

CONTENTS

APPENDIX A DEVELOPMENT TOOLS

APPENDIX B RELATED DOCUMENTS