Datasheet uPD77114GC-xxx-9EU, uPD77113AF1-xxx-CN1 Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD77113A, 77114

16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS

DESCRIPTION

The µPD77113A and 77114 are 16-bit fixed-point digital signal processors (DSPs).
Compared with the µPD77016 family, these DSPs have improved power consumption and are ideal for battery-

powered mobile terminals such as PDAs and cellular phones.

Both mask ROM and RAM models are available.

For details of the functions of these DSPs, refer to the following User’s Manuals:

PD77111 Family User’s Manual : U14623E

µ

PD77016 Family User’s Manual - Instructions: U13116E

µ

FEATURES

Instruction cycle (operating clock)

z

PD77113A : 13.3 ns MIN (75 MHz MAX)

µ

PD77114 : 13.3 ns MIN (75 MHz MAX)

µ

Memory

z

• Internal instruction memory
PD77113A : RAM 3.5K words × 32 bits

µ

Mask ROM 48K words × 32 bits

PD77114 : RAM 3.5K words × 32 bits

µ

Mask ROM 48K words × 32 bits

• Data memory
PD77113A : RAM 16K words × 16 bits × 2 banks

µ

Mask ROM 32K words × 16 bits × 2 banks

PD77114 : RAM 16K words × 16 bits × 2 banks

µ

Mask ROM 32K words × 16 bits × 2 banks
External memory space 8K words × 16 bits × 2 banks

ORDERING INFORMATION

Part Number Package

PD77113AF1-xxx-CN1 80-pin plastic fine-pitch BGA (9 × 9)

µ

PD77114GC-xxx-9EU 100-pin plastic TQFP (fine pitch) (14 × 14)

µ

Remark

Document No. U14373EJ3V0DS00 (3rd edition)
Date Published February 2001 N CP(K)
Printed in Japan

xxx indicates ROM code suffix.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

The mark shows major revised points.

©

1999

BLOCK DIAGRAM

BSFT

µµµµ

PD77113A, 77114

X bus

Y bus

R0 - R7

Y memory

data

addressing

unit

Main bus

ALU (40)

MAC

16 × 16 + 40 → 40

Program

control unit

Operation unit

Instruction

memory

PC stack

PLL

CLKOUT CLKIN

Note

WAKEUP

Interrupt

control

Host I/O

CPU control

Wait

RESET

Note

INT1 - INT4

controller

option.

Note The WAKEUP pin is multiplexed with the INT4 pin. The function of the WAKEUP pin can be activated or deactivated by mask

IE

I/O

X memory Y memory

Data memory unit

X memory

data

addressing

unit

Serial

I/O #1

Peripheral units

External memory

2

Serial

I/O #2

Data Sheet U14373EJ3V0DS

Port

Loop control

stack

PIN CONFIGURATION

Serial interface #1

Serial interface #2

SO1
SORQ1
SOEN1
SCK1
SI1
SIEN1
SIAK1

SO2
SOEN2
SCK2
SI2
SIEN2

+2.5 V +3 V

IV

DD

EV

WAKEUP

DD

RESET

INT1 - INT4

CLKIN

CLKOUT

Note 1

(4)

µµµµ

PD77113A, 77114

Reset, interrupt

Clock

System control

Notes 1.

Port

Host interface

For debugging

P0 - P3

(4)

HCS
HA0, HA1

(2)

HRD
HRE
HWR
HWE
HD0 - HD7

(8)

TDO, TICE

(2)

TCK, TDI, TMS, TRST

(4)

GND

DA0 - DA12

X/Y

D0 - D15

MRD

MWR

HOLDRQ

HOLDAK

BSTB

(13)

(16)

The function of this pin can be activated or deactivated by mask option.
An external data memory interface is not provided on the

2.

PD77113A.

µ

External data
memory

Note 2

Data bus
control

Data Sheet U14373EJ3V0DS

3

4

DSP FUNCTION LIST

Item PD77016

Memory space
(words × bits)

Data Sheet U14373EJ3V0DS

Instruction cycle (at maximum speed)
Multiple

Serial interface (two channels)

Supply voltage

Internal instruction RAM
Internal instruction ROM
Data RAM

(X/Y memory)

Data ROM
(X/Y memory)

External instruction
memory

External data memory
(X/Y memory)

µµµµµ µ µ

1.5K × 32 256 × 32 4K × 32 1K × 32
None

2K × 16 each 3K × 16 each 3K × 16 each

None 12K × 16 each 16K × 16 each

48K × 32

48K × 16 each 16K × 16 each None 16K × 16 each

30 ns (33 MHz)

–

Channels 1 and 2
have same function.

5 V 3 V DSP core: 2.5 V

×1, 2, 3, 4, 8 (mask option) Fixed to ×4 Integer of ×1 to 16 (mask option)

Channel 1 has same function as PD77016. Channel 2 does not have SORQ2 and SIAK2 pins (for connection of codec).

PD77019 PD77018A PD77019-013 PD77111 PD77112

24K × 32 None

16.6 ns (60 MHz) 13.3 ns (75 MHz)

µ

PD77110

35.5K × 32

24K × 16 each

None

32K × 16 each

15.3 ns (65 MHz)

Integer of ×1 to 8

(external pin)

31.75K × 32

None

I/O pins : 3 V

µµ

PD77113A PD77114

3.5K × 32
48K × 32

16K × 16 each

32K × 16 each

None 8K × 16 each

Package

160-pin QFP

116-pin BGA

100-pin TQFP 80-pin TQFP

80-pin FBGA

100-pin TQFP100-pin TQFP

80-pin FBGA 100-pin TQFP

µµ

µ

µ

PD77113A, 77114

PIN CONFIGURATION

µµµµ

PD77113A, 77114

80-pin plastic fine-pitch BGA (9

PD77113AF1-xxx-CN1

µµµµ

9)

××××

(Bottom View) (Top View)

9
8
7
6
5
4
3
2
1

JHGFEDCBA ABCDEFGHJ

Index mark

Pin No. Pin Name Pin No. Pin Nam e Pin No. Pin Name Pin No. Pin Nam e

A1

−

C3 NU E6 HCS G8 P1
A2 NU C4 RESET E7 GND G9 GND
A3 EV

DD

C5 TDI E8 HD1 H1 NU
A4 INT3 C6 TDO E9 HD2 H2 NU
A5 GND C7 CLKIN F1 NU H3 SCK1
A6 TMS C8 HA0 F2 NU H4 SOEN2
A7 GND C9 EV
A8 TRST D1 EV
A9

−

D2 NU F5 HD0 H7 P0

DD

DD

F3 SOEN1 H5 SIEN2
F4 GND H6 P3

B1 NU D3 INT2 F6 SI2 H8 HD7
B2 NU D4 NU F7 HD3 H9 NU
B3 INT1 D5 TCK F8 HD6 J1
B4
B5 IV

INT4/WAKEUP

DD

Note

D6 GND F9 HD5 J2 NU

D7 HWR G1 EV

DD

J3 SI1

−

B6 TICE D8 HRD G2 GND J4 SORQ1
B7 IV

DD

D9 EV

DD

G3 SIEN1 J5 SO2
B8 HA1 E1 NU G4 SO1 J6 SCK2
B9 CLKOUT E2 GND G5 IV

DD

J7 EV

DD

C1 GND E3 SIAK1 G6 HD4 J8 NU
C2 NU E4 NU G7 P2 J9

−

The function of the WAKEUP pin can be activated or deactivated by a mask option.

Note

Data Sheet U14373EJ3V0DS

5

µµµµ

PD77113A, 77114

100-pin plastic TQFP (fine-pitch) (14

PD77114GC-xxx-9EU

µµµµ

EVDDX/Y

I.C.

MRD

100

999897969594939291908988878685848382818079787776

GND

NC

NC
DA12
DA11
DA10

DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0

D15
D14
D13
D12
D11
D10

D9
D8

EV

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

26272829303132333435363738394041424344454647484950

14) (Top View)

××××

MWRNCBSTB

HOLDAK

HOLDRQ

INT1

INT2

Note

INT3

INT4/WAKEUP

RESET

GND

IVDDTRST

TMS

TDI

TCK

TICE

TDO

GND

IVDDGND

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

EV

DD

CLKIN
CLKOUT
HA1
HA0
HWR
HRD
HCS
HWE
HRE
GND

DD

EV
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
P0
P1
P2
P3
GND

D7D6D5D4D3D2D1

GND

The functions can be activated or deactivated by a mask option.

Note

D0

DD

SI1

IV

GND

SIEN1

SCK1

SIAK1

SO1

SOEN1

SOEN2

SORQ1

SO2

SCK2

SIEN2

SI2

NC

DD

EV

6

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

Pin No. Pin Name Pin No. Pin Nam e Pin No. Pin Name Pin No. Pin Nam e

1 GND 26 GND 51 GND 76 GND
2 NC 27D7 52P3 77IV

DD

3 NC 28D6 53P2 78GND
4 DA12 29D5 54P1 79TDO
5 DA11 30D4 55P0 80TICE
6 DA10 31D3 56HD7 81TCK
7 DA9 32 D2 57 HD6 82 TD1
8 DA8 33 D1 58 HD5 83 TMS
9 DA7 34 D0 59 HD4 84 TRST

10 DA6 35 I V

DD

60 HD3 85 IV

DD

11 DA5 36 GND 61 HD2 86 GND
12 DA4 37 SI1 62 HD1 87 RESET
13 DA3 38 S IEN1 63 HD0 88
14 DA2 39 S CK1 64 EV

DD

89 INT3

INT4/WAKEUP

15 DA1 40 SIAK1 65 GND 90 INT2
16 DA0 41 SO1 66 HRE 91 INT1
17 D15 42 S ORQ1 67 HWE 92 HOLDRQ
18 D14 43 S OEN1 68 HCS 93 HOLDAK
19 D13 44 S OEN2 69 HRD 94 BSTB
20 D12 45 S O2 70 HWR 95 NC
21 D11 46 S CK2 71 HA0 96 MWR
22 D10 47 S IEN2 72 HA1 97 MRD
23 D9 48 SI2 73 CLKOUT 98 I.C.
24 D8 49 NC 74 CLKIN 99 X/Y
25 EV

DD

50 E V

DD

75 E V

DD

100 EV

DD

Note

The function of the WAKEUP pin can be activated or deactivated by a mask option.

Note

Data Sheet U14373EJ3V0DS

7

PIN NAME

BSTB : Bus Strobe
CLKIN : Clock Input
CLKOUT : Clock Output
D0 - D15 : 16-bit Data Bu s
DA0 - DA12 : External Data Memory Address Bus

DD

EV
GND : Ground
HA0, HA1 : Host Data Access
HCS : Host Chip Select
HD0 - HD7 : Host Data Bus
HOLDAK : Hold Acknowledge
HOLDRQ : Hold Request
HRD : Host Read
HRE : Host Read Enable
HWE : Host Write Enable
HWR : Host Write
I.C. : Internally Connected
INT1 - INT4 : Interrupt

DD

IV
MRD : Memory Read Output
MWR : Memory Wri te Output
NC : Non-Connection
NU : Not Used
P0 - P3 : Port
RESET : Reset
SCK1, SCK2 : Serial Clock Input
SI1, SI2 : Serial Data Input
SIAK1 : Serial Input Acknowledge
SIEN1, SIEN2 : Serial Input Enable
SO1, SO2 : Serial Data Output
SOEN1, SOEN2: Serial Output Enable
SORQ1 : Serial Output Request
TCK : Test Clock Input
TDI : Test Data Input
TDO : Test Data Output
TICE : Test In-Circuit Emulator
TMS : Test Mode Select
TRST : Test Reset
WAKEUP : Wakeup from STOP Mode
X/Y : X/Y Memory Select

: Power Supply for I/O Pins

: Power Supply for DSP Core

µµµµ

PD77113A, 77114

8

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

CONTENTS

1. PIN FUNCTION................................................................................................................................. 10

1.1 Pin Function Description.......................................................................................................... 10

1.2 Connection of Unused Pins ..................................................................................................... 15

2. FUNCTION OUTLINE....................................................................................................................... 17

2.1 Program Control Unit................................................................................................................ 17

2.2 Arithmetic Unit........................................................................................................................... 18

2.3 Data Memory Unit...................................................................................................................... 19

2.4 Peripheral Units......................................................................................................................... 19

3. CLOCK GENERATOR...................................................................................................................... 20

4. RESET FUNCTION........................................................................................................................... 20

4.1 Hardware Reset ......................................................................................................................... 20

4.2 Initializing PLL........................................................................................................................... 21

5. FUNCTIONS OF BOOT-UP ROM...................................................................................................21

5.1 Boot at Reset ............................................................................................................................. 21

5.2 Reboot ........................................................................................................................................ 22

5.3 Signature Operation.................................................................................................................. 23

5.4 Instruction ROM Modification.................................................................................................. 23

6. STANDBY MODES........................................................................................................................... 24

6.1 HALT Mode................................................................................................................................. 24

6.2 STOP Mode ................................................................................................................................ 24

7. MEMORY MAP.................................................................................................................................. 25

7.1 Instruction Memory ................................................................................................................... 25

7.2 Data Memory.............................................................................................................................. 27

8. MASK OPTION ................................................................................................................................. 28

8.1 Clock Control Options.............................................................................................................. 28

8.2 WAKEUP Function .................................................................................................................... 29

9. INSTRUCTIONS................................................................................................................................. 30

9.1 Outline of Instructions.............................................................................................................. 30

9.2 Instruction Set and Operation.................................................................................................. 31

10. ELECTRICAL SPECIFICATIONS..................................................................................................... 37

11. PACKAGE DRAWINGS.................................................................................................................... 56

12. RECOMMENDED SOLDERING CONDITIONS............................................................................... 58

Data Sheet U14373EJ3V0DS

9

µµµµ

PD77113A, 77114

1. PIN FUNCTION

Because the pin numbers differ depending on the package, refer to the diagram of the package to be used.

1.1 Pin Function Description

• Power supply

Pin Name

DD

IV

DD

EV

GND 1, 26, 36, 51,

Remark

100-pin TQFP 80-pin BGA
35, 77, 85 B5, B7, G5
25, 50, 64, 75,

100

65, 76, 78, 86

Please supply voltage to the IV

Pin No.

A3, C9, D1, D9,
G1, J7

A5, A7, C1, D6,
E2, E7, F4, G2,
G9

I/O Function Shared by:

Power to DSP core (+2.5 V)

−

Power to I/O pins (+3 V)

−

Ground

−

DD

and EVDD pins simultaneously.

• System control

Pin Name

100-pin TQFP 80-pin BGA

CLKIN 74 C7 Input System clock i nput
CLKOUT 73 B9 Output Internal system clock output
RESET 87 C4 Input Internal system reset signal input
WAKEUP 88 B4 Input St op mode releas e signal input.

Pin No.

I/O Function Shared by:

• When this pin is asserted active, the stop
mode is released. The functi on of this pin
can be activated or deacti vated by a mask
option.

−

−

−

−

−

INT4

• Interrupt

Pin Name

100-pin TQFP 80-pin BGA
INT1 - INT3 91 - 89 B3, D3, A4 Input
INT4 88 B4 Input

10

Pin No.

Data Sheet U14373EJ3V0DS

I/O Function Shared by:

External maskable int errupt input.

• Detected at the fall i ng edge.

−

WAKEUP

µµµµ

PD77113A, 77114

• External data memory interface (

Pin No.

Pin Name

100-pin TQFP 80-pin BGA

X/Y 99

DA0 - DA12 16 - 4

D0 - D15 34 - 27, 24 - 17

MRD 97

MWR 96

HOLDRQ 92

BSTB 94

HOLDAK 93

PD77114 only)

µµµµ

−

−

−

−

−

−

−

−

I/O Function Shared by:

Output

(3S)

Output

(3S)

I/O

(3S)

Output

(3S)

Output

(3S)

Input Hold request signal

Output Bus strobe si gnal

Output Hold acknowledge signal

Memory select signal output.

0: Uses X memory.
1: Uses Y memory.

Address bus of external data memory.

• Accesses the external memory.

• Continuously outputs the external memory
address accessed las t when the external
memory is not being accessed. Kept low
(0x000) if the external memory is never
accessed after reset.

16-bit data bus.

• Accesses the external memory.

Read output

• External memory read

Write output

• External memory write

• Input a low level to t hi s pin when the external
device uses the external data memory bus of
the

PD77114.

µ

• This pin goes l ow when the
the external data memory bus .

• This pin goes low when the ex t ernal device
is enabled to use the external data memory
bus of the

PD77114.

µ

PD77114 uses

µ

−

−

−

−

−

−

−

−

Remark

Pins marked “3S” under the heading “I/O” go into a high-impedance state in the following conditions:
X/Y, DA0-DA12, MRD, MWR: When the bus is released (HOLDAK = low level)
D0-D15: When the external data memory is not being accessed and when the bus is released
(HOLDAK = low level)

Data Sheet U14373EJ3V0DS

11

• Serial interface

µµµµ

PD77113A, 77114

Pin Name

SCK1 39 H3 Input Serial 1 cloc k input
SORQ1 42 J4 Output Serial output 1 request
SOEN1 43 F3 Input Serial output 1 enable
SO1 41 G4 Output

SIEN1 38 G3 Input Serial input 1 enable
SI1 37 J3 Input Serial data input 1
SIAK1 40 E3 Output Serial i nput 1 acknowledge
SCK2 46 J6 Input Serial 2 clock input
SOEN2 44 H4 Input Serial output 2 enable
SO2 45 J5 Output

SIEN2 47 H5 Input Serial input 2 enable
SI2 48 F6 Input Serial data input 2

Remark

100-pin TQFP 80-pin BGA

The pins marked “3S” under the heading “I/O” go into a high-impedance state on completion of data

Pin No.

I/O Function Shared by:

Serial data output 1

(3S)

Serial data output 2

(3S)

transfer and input of the hardware reset (RESET) signal.

−

−

−

−

−

−

−

−

−

−

−

−

12

Data Sheet U14373EJ3V0DS

• Host interface

µµµµ

PD77113A, 77114

Pin Name

100-pin TQFP 80-pin BGA

HA1 72 B8 Input Spec i fies the register to be accessed by HD7

HA0 71 C8 Input Spec i fies the register to be accessed by HD7

HCS 68 E6 Input Chip select input
HRD 69 D8 Input Host read input
HWR 70 D7 Input Host write input
HRE 66
HWE 67
HD0 - HD7 63 - 56 F5, E8, E9, F7,

Pin No.

G6, F9, F8, H8

I/O Function Shared by:

through HD0.

• 1: Accesses the hos t i nterface status

register (HST).

• 0: Accesses the hos t transmit data register

(HDT (out)) when read (HRD = 0), and
host receive data regist er (HDT (i n))
when written (HWR = 0).

through HD0.

• 1: Accesses bits 15 through 8 of HST, HDT

(in), and HDT (out).

• 0: Accesses bits 7 through 0 of HST, HDT

(in), and HDT (out).

−

−

Output Host read enable output
Output Host write enable output

I/O

(3S)

8-bit host data bus

−

−

−

−

−

−

−

−

Remark

The pins marked “3S” under the heading “I/O” go into a high-impedance state when the host interface is
not being accessed.

• I/O ports

Pin Name

100-pin TQFP 80-pin BGA
P0 55 H7 I/O
P1 54 G8 I/O
P2 53 G7 I/O
P3 52 H6 I/O

Pin No.

I/O Function Shared by:

General-purpose I/O port

−

−

−

−

Data Sheet U14373EJ3V0DS

13

• Debugging interface

µµµµ

PD77113A, 77114

Pin Name

100-pin TQFP 80-pin BGA
TDO 79 C6 Output
TICE 80 B6 Output
TCK 81 D5 Input
TDI 82 C5 Input
TMS 83 A6 Input
TRST 84 A8 Input

Pin No.

I/O Function Shared by:

• Others

Pin Name

100-pin TQFP 80-pin BGA
I.C. 98

NU

NC 2, 3, 49, 95

−−

Pin No.

−−

−

A2, B1, B2, C2,
C3, D2, D4, E1,
E4, F1, F2, H1,
H2, H9, J2, J8

−−

A1, A9, J1, J9

I/O Function Shared by:

For debugging

Internally connected. Leave this pin
unconnected.

No function pins. Connect to EV

−

resistor, or connect to GND via pull-down
resistor.

No-connect pins. Leave these pins
unconnected.

Pins to strengthen sol deri ng. Connect these

−

pins to the board as necessary.

DD

via pull-up

−

−

−

−

−

−

−

−

−

−

Caution If any signal is input to these pins or if an attempt is made to read these pins, the normal

operation of the

PD77113A and 77114 is not guaranteed.

µµµµ

14

Data Sheet U14373EJ3V0DS

1.2 Connection of Unused Pins

1.2.1 Connection of Function Pins

When mounting, connect unused pins as follows:

Pin I/O Recommended Connection
INT1 - INT4 Input Connect to EVDD.
X/Y Output
DA0 - DA12 Output
D0 - D15
MRD, MWR Output Leave unconnected.
HOLDRQ Input Leave unconnected. (i nternally pulled up).
BSTB, HOLDAK Output Leave unconnected.
SCK1, SCK2 Input
SI1, SI2 Input
SIEN1, SIEN2 Input
SOEN1, SOEN2 Input
SORQ1 Output
SO1, SO2 Output
SIAK1 Output
HA0, HA1 Input Connect to EVDD or GND.
HCS, HRD, HWR Input Connec t to EVDD.
HRE, HWE Output Leave unconnected.
HD0 - HD7
P0 - P3 I/O
TCK Input Connect to GND via pull-down resistor.
TDO, TICE Out put Leave unconnected.
TMS, TDI Input Leave unconnected. (internally pulled up).
TRST Input Leave unconnected. (internal l y pul l ed down).
CLKOUT Output Leave unconnected.

Note 1

Note 2

I/O Connect to E VDD via pull-up resistor, or c onnect to GND via pull-down resistor.

I/O

Leave unconnected.

DD

Connect to EV

Connect to GND.

Leave unconnected.

Connect to EV

or GND.

DD

via pull-up resistor, or c onnect to GND via pull-down resistor.

µµµµ

PD77113A, 77114

Notes 1.

These pins may be left unconnected if the external data memory is not accessed in the program.
However, connect these pins as recommended in the halt and stop modes when the power
consumption must be lowered.
These pins may be left unconnected if HCS, HRD, and HWR are fixed to the high level.

2.

However, connect these pins as recommended in the halt and stop modes when the power
consumption must be lowered.

Data Sheet U14373EJ3V0DS

15

1.2.2 Connection of no-function pins

Pin I/O Recommended Connection

µµµµ

PD77113A, 77114

I.C.
NU
NC

−

−

−

Leave unconnected.
Connect to EVDD via pull-up resistor, or c onnect to GND via pull-down resistor.
Leave unconnected.

16

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

2. FUNCTION OUTLINE

2.1 Program Control Unit

This unit is used to execute instructions, and control branching, loops, interrupts, the clock, and the standby mode

of the DSP.

2.1.1 CPU control

A three-stage pipeline architecture is employed and almost all the instructions, except some instructions such as

branch instructions, are executed in one system clock.

2.1.2 Interrupt control

Interrupt requests input from external pins (INT1 through INT4) or generated by the internal peripherals (serial
interface and host interface) are serviced. The interrupt of each interrupt source can be enabled or disabled.
Multiple interrupts are also supported.

2.1.3 Loop control task

A loop function without any hardware overhead is provided. A loop stack with four levels is provided to support
multiple loops.

2.1.4 PC stack

A 15-level PC stack that stores the program counter supports multiple interrupts and subroutine calls.

2.1.5 PLL

A PLL is provided as a clock generator that can multiply or divide an external clock input to supply an operating
clock to the DSP. A multiple of ×1 to ×16 or a division ratio of 1/1 to 1/16 can be set by a mask option.

Two standby modes are available for lowering the power consumption while the DSP is not in use.

• HALT mode : Set by execution of the HALT instruction. The current consumption drops to several mA. The
normal operation mode is recovered by an interrupt or hardware reset.

• STOP mode: Set by execution of the STOP instruction. The current consumption drops to several 10 µA. The
normal operation mode is recovered by hardware reset or WAKEUP pin

If the WAKEUP function is activated by mask option

Note

2.1.6 Instruction memory

The capacity and type of the memory differ depending on the model of the DSP.
64 words of the instruction RAM are allocated to interrupt vectors.
A boot-up ROM that boots up the instruction RAM is provided, and the instruction RAM can be initialized or

rewritten by self boot (boot from the internal data ROM or external data space) or host boot (boot via host interface).

The µPD77113A and 77114 have 3.5K-word instruction RAM and 48K-word instruction ROM.

Note

.

Data Sheet U14373EJ3V0DS

17

µµµµ

PD77113A, 77114

2.2 Arithmetic Unit

This unit performs multiplication, addition, logical operations, and shift, and consists of a 40-bit multiply

accumulator, 40-bit data ALU, 40-bit barrel shifter, and eight 40-bit general-purpose registers.

2.2.1 General-purpose registers (R0 through R7)

These eight 40-bit registers are used to input/output data for arithmetic operations, and load or store data from/to

data memory.

A general-purpose register (R0 to R7) is made up of three parts: R0L through R7L (bits 15 through 0), R0H
through R7H (bits 31 through 16), and R0E through R7E (bits 39 through 32). Depending on the type of operation,
RnL, RnH, and RnE are used as one register or in different combinations.

2.2.2 Multiply accumulator (MAC)

The MAC multiplies two 16-bit values, and adds or subtracts the multiplication result from one 40-bit value, and
outputs a 40-bit value.

The MAC is provided with a shifter (MSFT: MAC ShiFTer) at the stage preceding the input stage. This shifter can
arithmetically shift the 40-bit value to be added to or subtracted from the multiplication result 1 or 16 bits to the right .

2.2.3 Arithmetic logic unit (ALU)

This unit inputs one or two 40-bit values, executes an arithmetic or logical operation, and outputs a 40-bit value.

2.2.4 Barrel shifter (BSFT: Barrel ShiFTer)

The barrel shifter inputs a 40-bit value, shifts it to the left or right by any number of bits, and outputs a 40-bit value.
The data may be arithmetically shifted to the right shifted to the right, in which case the data is sign-extended, or
logically shifted to the right, in which case 0 is inserted from the MSB.

18

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

2.3 Data Memory Unit

The data memory unit consists of two banks of data memory and two data addressing units.

2.3.1 Data memory

The capacity and type of the memory differ depending on the model of the DSP. All DSPs have two banks of data

memory (X data memory and Y data memory). A 64-word peripheral area is assigned in the data memory space.

The µPD77113A and 77114 have 16K words × 2 banks data RAM and 32K words × 2 banks data ROM.
In addition, the µPD77114 has an external data memory interface so that the external memory can be expanded

to 8K words × 2 banks.

2.3.2 Data addressing unit

An independent data addressing unit is provided for each of the X data memory and Y data memory spaces.
Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or

DMY), and an address ALU.

2.4 Peripheral Units

A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal
peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as
memory-mapped I/Os.

2.4.1 Serial interface (SIO)

Two serial interfaces are provided. These serial interfaces have the following features:

• Serial clock : Supplied from external source to each interface. The same clock is used for input and output
on the interface.

• Frame length: 8 or 16 bits, and MSB or LSB first selectable for each interface and input or output

• Handshake : Handshaking with external devices is implemented with a dedicated status signal. With the
internal units, polling, wait, or interrupt are used.

2.4.2 Host interface (HIO)

This is an 8-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In
the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external
device is implemented by using a dedicated status signal. Handshaking with internal units is achieved by means of
polling, wait, or interrupts.

2.4.3 General-purpose I/O port (PIO)

This is a 4-bit I/O port that can be set in the input or output mode in 1-bit units.

2.4.4 Wait cycle register

The number of wait cycles to be inserted when the external data memory area is accessed can be specified in
advance by using a register (DWTR)

This function is not available on the µPD77113A because this DSP does not have an external data area.

Note

Note

. The number of wait cycles that can be set is 1, 3, or 7.

Data Sheet U14373EJ3V0DS

19

µµµµ

PD77113A, 77114

3. CLOCK GENERATOR

The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and

supplies the generated clock to the internal units of the DSP.

For details of how to set the PLL multiple, refer to

4.2 Initializing PLL

, and

8.1 Clock Control Options

.

Halt mode

CLKIN

CLKOUT

Stop mode

PLL control circuit

×m

Output divider Halt divider

÷n ÷l

4. RESET FUNCTION

When a low level of a specified width is input to the RESET pin, the device is initialized.

4.1 Hardware Reset

Internal
system clock

If the RESET pin is asserted active (low level) for a specified period, the internal circuitry of the DSP is initialized.
If the RESET pin is then deasserted inactive (high level), boot processing of the instruction RAM is performed
according to the status of the port pins (P0 and P1). After boot processing, processing is executed starting from the
instruction at address 0x200 of instruction memory (reset entry). In addition, a self-check is performed by the internal
data RAM at the same time as the boot processing. This check takes about 20 ms (at 50 MHz operation, the length
of this period is in inverse proportion to the operating frequency.)

On power application, the RESET pin must be asserted active (low level) after 4 input clocks have been input with
the RESET pin in the inactive status (high level), after the supply voltage has reached the level of the operating
voltage. In other words, no power-ON reset function is available. On power application, the PLL must be initialized.

20

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

4.2 Initializing PLL

Initializing the PLL starts from the 1024th input clock after the RESET pin has been asserted active (low level).

Initialization takes 1024 clocks and it takes the PLL 100 µs to be locked.

After that, the DSP operates with the set value of the PLL specified by a mask option when the RESET pin is

deasserted inactive (high level).

After initializing the PLL, be sure to execute boot-up processing to re-initialize the internal RAM. To initialize the

PLL, the internal memory contents and register status of the DSP are not retained.

If the RESET pin is deasserted inactive before the PLL initialization mode is set, the DSP is normally reset (the

PLL is not initialized).

CLKIN

10241 2048

RESET

PLL initialization
(internal status)

Approx. 100 s
PLL lock time

PLL initialization
mode

µ

Caution Do not deassert the RESET signal inactive in the PLL initialization mode and during PLL lock

period.

5. FUNCTIONS OF BOOT-UP ROM

To rewrite the contents of the instruction memory on power application or from program, boot up the instruction

RAM by using the internal boot-up ROM.

The µPD77113A and 77114 have a function to verify the contents of the internal instruction RAM and a function to

modify the instruction ROM in the boot-up ROM.

5.1 Boot at Reset

After hardware reset has been cleared, the boot program first reads the general-purpose I/O ports P0 and P1 and,
depending on their bit pattern, determines the boot mode (self boot or host boot). After boot processing, processing
is executed starting from the instruction at address 0x200 (reset entry) of the instruction memory.

The pins (P0 and P1) that specify the boot mode must be kept stable for the duration of 3 clocks before and for
the duration of 12 clocks after reset has been cleared (the clock is input from CLKIN).

If host boot or self boot is specified, a self-check of the internal data RAM is performed at the same time as boot
processing.

P1 P0 Boot Mode

Note

00
0 1 Ex ecutes host boot and then branches to address 0x200.
1 1 Ex ecutes self boot and then branches to address 0x200.
1 0 Set ting prohibited

Does not execute boot but branc hes to address 0x200

.

This setting is used when the DSP must be reset to recover from the standby mode after reset boot has

Note

been executed once.

Data Sheet U14373EJ3V0DS

21

µµµµ

PD77113A, 77114

5.1.1 Self boot

The boot-up ROM transfers the instruction code stored in the data memory space to the instruction RAM, based
on the boot parameter written to address 0x4000 of the Y data memory. Generally, with a mask ROM model, this
function is implemented by storing the instructions to be booted in the data ROM.

In addition, the instructions to be booted can be also stored in an external data area in the form of flash ROM, and
self boot can be executed from this external data area.

5.1.2 Host boot

In this boot mode, a boot parameter and instruction code are obtained via the host interface, and transferred to the
instruction RAM.

5.2 Reboot

By calling the next reboot entry from the program, the contents of the instruction RAM can be rewritten.

Reboot Mode Entry Address

Self boot

Y memory

Host boot Host reboot 0x5

5.2.1 Self reboot

The instruction codes stored in the data memory are transferred to the instruction RAM.

Set the following parameters and call the entry address of the corresponding reboot mode to execute self reboot.

• R7L: Number of instruction steps for rebooting

• DP3: First address of X memory in which instruction codes are stored (in the case of reboot from X memory),
or first address of the instruction memory to be loaded (in the case of reboot from Y memory)

• DP7: First address of instruction memory to be loaded (in the case of reboot from X memory), or first address
of X memory in which instruction codes are stored (in the case of reboot from Y memory)

5.2.2 Host reboot

An instruction code is obtained via the host interface and transferred to the instruction RAM.
The entry address of is 0x5. Host reboot is executed by calling this address after setting the following parameter:

Word reboot 0x2X memory
Byte reboot 0x4
Word reboot 0x1
Byte reboot 0x3

• R7L: Number of instruction steps for rebooting

• DP3: First address of instruction memory to be loaded

22

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

5.3 Signature Operation

The µPD77113A and 77114 have a signature operation function so that the contents of the internal instruction
RAM can be verified. The signature operation performs a specific arithmetic operation on the data in the instruction
RAM booted up, and returns the result to a register. Perform the signature operation in advance on the device when
it is operating normally, and repeat the signature operation later to check whether the data in RAM is correct by
comparing the operation result with the previous result. If the results are identical, there is no problem.

The entry address is 0x9. Execute the operation by calling this address after setting the following parameter. The
operation result is stored in register R7.

• R7L: Number of instruction steps for operation

• DP3: First address of instruction memory for operation

5.4 Instruction ROM Modification

The µPD77113A and 77114 have a function to modify the contents of the internal instruction mask ROM.
Instructions at up to four addresses can be modified.

The entry address is 0x10D. By calling this address with the following parameters, modification is performed.

R7L : Address of instruction ROM to be modified

R6H, R6L : Instruction code (32 bits)

Data Sheet U14373EJ3V0DS

23

µµµµ

PD77113A, 77114

6. STANDBY MODES

Two standby modes are available. By executing the corresponding instruction, each mode is set and the power

consumption can be reduced.

6.1 HALT Mode

To set this mode, execute the HALT instruction. In this mode, functions other than clock circuit and PLL are

stopped to reduce the current consumption.

To release the HALT mode, use an interrupt or hardware reset. When releasing the HALT mode using an
interrupt, the contents of the internal registers and memory are retained. It takes several 10 system clocks to release
the HALT mode when the HALT mode is released using an interrupt.

In the HALT Mode, the clock circuit of the µPD77111 family supplies the following clock as the internal system
clock. The clock output from the CLKOUT pin is also as follows.

The clock output from the CLKOUT pin, however, has a high-level width that is equivalent to 1 cycle of the normal
operation (i.e., the duty factor is not 50%).

PD77113A, 77114: 1/l of internal system clock (l = integer from 1 to 16, specified by mask option)

•

µ

6.2 STOP Mode

To set this mode, execute the STOP instruction. In this mode, all the functions, including the clock circuit and
PLL, are stopped and the power consumption is minimized with only leakage current flowing.

To release the STOP mode, use hardware reset or WAKEUP pin.

When releasing the STOP mode by using the WAKEUP pin, the contents of the internal registers and memory are
retained, but it takes several 100 µs to release the mode.

The WAKEUP pin is multiplexed with the INT4 pin. Usually, this pin functions as an interrupt pin, but functions as
the WAKEUP pin when it is asserted active in the STOP mode. Whether the WAKEUP pin is used to release the
STOP mode is selected by mask option. For details, refer to

8.2 WAKEUP Function

.

24

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

7. MEMORY MAP

A Harvard architecture, in which the instruction memory space and data memory space are separated is

employed.

7.1 Instruction Memory

7.1.1 Instruction memory map

The instruction memory space consists of 64K words × 32 bits, and the capacity and type of the memory differ

depending on the product.

µ

PD77113A, 77114

0x FFFF

Internal instruction
ROM
(48K words)

00xx430

0F0

F

F

00xx100F0F0

F

00xx0022430

F

00xx00210F0

F

00xx00100F0

F

0x0000

System

Internal instruction RAM

(3.5K words)

Vector area (64 words)

System

Boot-up ROM

(256 words)

Caution Programs and data cannot be placed at addresses reserved for the system, nor can these

addresses be accessed. If these addresses are accessed, the normal operation of the device
cannot be guaranteed.

Data Sheet U14373EJ3V0DS

25

µµµµ

PD77113A, 77114

7.1.2 Interrupt vector table

Addresses 0x200 through 0x23F of the instruction memory are entry points (vectors) of interrupts. Four
instruction addresses are assigned to each interrupt source.

Vector Interrupt Source
0x200 Reset
0x204
0x208
0x20C
0x210 INT1
0x214 INT2
0x218 INT3
0x21C INT4
0x220 SI1 input
0x224 SO1 output
0x228 SI2 input
0x22C SO2 output
0x230 HI input
0x234 HO output
0x238
0x23C

Reserved

Reserved

Cautions 1. Although reset is not an interrupt, it is handled like an interrupt as an entry to a vector.

2. It is recommended that unused interrupt source vectors be used to branch an error
processing routine.

3. Because a vector area also exists in the internal RAM area of the mask ROM model, this
area must be booted up. In addition, because the entry address after reset is 0x200,
address 0x200 must be booted up even when the internal instruction RAM and interrupts are
not used.

26

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

7.2 Data Memory

7.2.1 Data memory map

The data memory space consists of an X memory space and a Y memory space of 64K words × 16 bits each, and

the memory capacity and memory type differ depending on the product.

µ

0x FFFF
00xxED0

0F0

F

00xxCB0F0F0

F

F

PD77113A

Data RAM
(8K words)

System

µ

PD77114

Data RAM

(8K words)

External data
memory
(8K words)

00xx430F0F0
00xx3388430

00xx33870F0
00xx320F0F0

00xx210F0F0

00xx100F0F0

0x0000

F
F

F
F

F

F

Data ROM

(32K words)

System

Peripheral
(64 words)

System

Data RAM
(4K words)

System

Data RAM
(4K words)

Data ROM

(32K words)

System

Peripheral

(64 words)

System

Data RAM

(4K words)

System

Data RAM

(4K words)

Caution Programs and data cannot be placed at addresses reserved for the system, nor can these

addresses be accessed. If these addresses are accessed, the normal operation of the device
cannot be guaranteed.

Data Sheet U14373EJ3V0DS

27

µµµµ

PD77113A, 77114

7.2.2 Internal peripherals

The internal peripherals are mapped to the internal data memory space.

X/Y Memory Address Register Name Function Peripheral Name

0x3800 SDT1 First serial data register
0x3801 SST1 Firs t serial status register
0x3802 SDT2 Second serial data regist er
0x3803 SST2 Sec ond serial status register
0x3804 PDT Port data register
0x3805 PCD Port command regis ter
0x3806 HDT Host data register
0x3807 HST Host status register
0x3808 DWTR Data memory wait cycle register WTR

0x3809 - 0x383F Reserved area

Caution Do not access this area.

SIO

PIO

HIO

−

Cautions 1. The register names listed in this table are not reserved words of the assembler or the C

language. Therefore, when using these names in assembler or C, the user must define
them.

2. The same register is accessed, as long as the address is the same, regardless of whether
the X memory space or Y memory space is accessed.

3. Even different registers cannot be accessed at the same time from both the X and Y memory
spaces.

8. MASK OPTION

The µPD77113A and 77114 have mask options that must be specified when an order for a ROM is placed. This
section explains these mask options. The mask options are specified in the Workbench (WB77016) development
tool. To order a mask ROM, output a mask ROM ordering file format (.msk file) using WB77016.

8.1 Clock Control Options

The following four clock related options must be specified.

• PLL multiple

• Output division ratio

• HALT division ratio

• Validity of CLKOUT pin

28

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

When the PLL multiple is m, output division ratio is n, and halt division ratio is l, the relationship between each

operation mode and operating clock is as follows:

Operation Mode Clock S uppl i ed Inside DSP
Normal operation mode m/n times external input cl ock
HALT mode m/n/l times ex t ernal i nput clock
STOP mode S topped

The PLL control circuit multiplies the input clock by an integer from 1 to 16. Specify the mask option of the PLL

multiple so that the multiplied frequency falls within the specified PLL lock frequency range.

The output divider divides the clock multiplied by the PLL by an integer from 1 to 16. Specify the mask option of
the output division ratio so that the frequency m/n times the external input clock supplied to the DSP falls within the
specified operating frequency range of the DSP.

The HALT divider functions only in the HALT mode. It divides the clock of the output divider by an integer from 1
to 16 and supplies the divided clock to the internal circuitry. Specify the mask option of the HALT division ratio so
that necessary division can be performed.

Whether the clock supplied to the internal circuitry of the DSP (internal system clock) is “output” or “not output”
from the CLKOUT pin can be specified. Specify the mask option as necessary.

If an odd value (other than 1) is specified as the output division ratio, the high-level width of the clock output from
the CLKOUT pin is equal to one cycle during normal operation (i.e., the clock does not have a duty factor of 50%).

8.2 WAKEUP Function

The WAKEUP pin can be used to release the STOP mode as well as a hardware reset.

If the STOP mode is released by means of a hardware reset, the status before the STOP mode was set cannot be
restored after the STOP mode has been released. If the WAKEUP pin is used, however, the status before the STOP
mode is set can be retained and program execution can be resumed starting from the instruction after the STOP
instruction.

Whether the WAKEUP pin is used to release the STOP mode can be specified by a mask option.

When the WAKEUP function is specified valid, the WAKEUP pin is multiplexed with the INT4 pin and it usually
functions as an interrupt pin. The pin functions as the WAKEUP pin only in the STOP mode (if this pin is asserted
active in the STOP mode, it is used only to release the STOP mode, and execution does not branch to an interrupt
vector).

Data Sheet U14373EJ3V0DS

29

µµµµ

PD77113A, 77114

9. INSTRUCTIONS

9.1 Outline of Instructions

An instruction consists of 32 bits. Almost all the instructions, except some such as branch instructions, are
executed with one system clock. The maximum instruction cycle of the µPD77113A and 77114 is 13.3 ns. The
following nine types of instructions are available:

(1) Trinomial operation instructions

These instructions specify an operation by the MAC. As the operands, three general-purpose registers can be
specified.

(2) Binomial operation instructions

These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose
registers can be specified. An immediate value can be specified for some of these instructions, instead of a
general-purpose register, for one input.

(3) Uninominal operation instructions

These instructions specify an operation by the ALU. As the operands, one general-purpose register can be
specified.

(4) Load/store instructions

These instructions transfer 16-bit values between memory and a general-purpose register. Any general-purpose
register can be specified as the transfer source or destination.

(5) Register-to-register transfer instructions

These instructions transfer data from one general-purpose register to another.

(6) Immediate value setting instructions

These instructions write an immediate value to a general-purpose register and the registers of the address
operation unit.

(7) Branch instructions

These instruction specify branching of program execution.

(8) Hardware loop instructions

These instruction specify repetitive execution of an instruction.

(9) Control instructions

These instructions are used to control the program.

30

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

9.2 Instruction Set and Operation

An operation is written in the operation field for each instruction in accordance with the operation representation

format of that instruction. If two or more parameters can be written, select one of them.

(a) Representation formats and selectable registers

The following table shows the representation formats and selectable registers.

Representation Format Selectable Register
r0, r0′, r0
rI, rI
rh, rh
re R0E - R7E
reh R0EH - R7EH
dp DP0 - DP7
dn DN0 - DN7
dm DMX, DMY
dpx DP0 - DP3
dpy DP4 - DP7
dpx_mod DPn, DPn++, DPn−−, DPn##, DPn%%, !DPn## (n = 0 - 3)
dpy_mod DPn, DPn++, DPn−−, DPn##, DPn%%, !DPn## (n = 4 - 7)
dp_imm DPn##imm (n = 0 - 7)
*xxx Contents of memory with address xxx

″

′

′

R0 - R7
R0L - R7L
R0H - R7H

<Example> I f the contents of the DP0 register are 1000, *DP 0 i ndi c ates the contents of

address 1000 of the memory.

Data Sheet U14373EJ3V0DS

31

µµµµ

PD77113A, 77114

(b) Modifying data pointer

The data pointer is modified after the memory has been accessed. The result of modification becomes valid
starting from the instruction that immediately follows. The data pointer cannot be modified.

Example Operation
DPn Nothing is done (value of DPn is not changed.)
DPn++ DPn ← DPn + 1
DPn

−−

DPn## DPn ← DPn + DNn

DPn%%

!DPn## Reverses bits of DPn and t hen ac cesses memory.

DPn##imm DPn ← DPn + imm

DPn ← DPn − 1

(Adds value of correspondi ng DN0 to DN7 to DP0 to DP7.)
Example: DP0 ← DP0 + DN0

(n = 0 - 3) DPn = ((DPL + DNn) mod (DMX + 1)) + DP
(n = 4 - 7) DPn = ((DP

After memory access, DPn ← DPn + DNn

L

+ DNn) mod (DMY + 1)) + DP

H

H

(c) Instructions that can be simultaneously written

Instructions that can be simultaneously written are indicated by √.

(d) Status of overflow flag (OV)

The status of the overflow flag is indicated by the following symbol:

: Not affected

z

: Set to 1 when overflow occurs

Caution If an overflow does not occur as a result of an operation, the overflow flag is not reset but

retains the status before the operation.

32

Data Sheet U14373EJ3V0DS

Instruction Set

Instruc­tion

Instruction
Name

Mnemonic Operation

µµµµ

PD77113A, 77114

Instructions Si m ul taneously Written Flag

Trino­mial

Bino­mial

Unino­minal

Load/
store

Trans­fer

Imme­diate­value

Bran­ch

Loop

Cont­rol

OV

Trinomial
operation

Binomial
operation

Multiply add ro = ro + rh * rh
Multiply sub ro = ro − rh * rh
Sign unsign

multiply add

ro = ro + rh * rl
(rl is in positive integer

′

′

ro ← ro + rh * rh
ro ← ro − rh * rh
ro ← ro + rh * rl

format.)

Unsign unsign
multiply add

ro = ro + rl * rl

′

(rl and rl’ are in positive

ro ← ro + rl * rl

integer format.)

ro

+ rh * rh

1-bit shift

ro = (ro>>1) + rh * rh

ro ←

′

2

multiply add

ro

+ rh * rh

ro ←

16-bit shift

ro = (ro>>16) + rh * rh

′

16

2

multiply add
Multiply ro = rh * rh
Add ro″ = ro + ro

′

′

ro ← rh * rh
ro″ ← ro + ro

′√

Immediate add ro′ = ro + imm ro′ ← ro + imm

(where imm ≠ 1)

Sub ro″ = ro − ro

′

ro″ ← ro − ro

Immediate sub ro′ = ro − imm ro ← ro − imm

(where imm ≠ 1)

Arithmetic right

ro′ = ro SRA rl ro′ ← ro >> rl

shift
Immediate

ro′ = ro SRA imm ro′ ← ro >> imm
arithmetic right
shift

Logical right

ro′ = ro SRL rl ro′ ← ro >> rl
shift

Immediate

ro′ = ro SRL imm ro′ ← ro >> imm
logical right
shift

Logical left shift ro′ = ro SLL rl ro′ ← ro << rl
Immediate

ro′ = ro SLL imm ro′ ← ro << imm
logical left shift

AND ro″ = ro & ro
Immediate

ro′ = ro & imm ro′ ← ro & imm

′

ro″ ← ro & ro

AND
OR ro″ = ro  ro

′

ro″ ← ro  ro
Immediate OR ro′ = ro  imm ro′ ← ro  imm
Exclusive OR ro″ = ro ∧ ro
Immediate

ro′ = ro ∧ imm ro′ ← ro ∧ imm

′

ro″ ← ro ∧ ro

exclusive OR

′√
′√

√

′√

′

′

√

√

′√

′√

√

√

√

′√

′√

′√

z

z

z

z

z

z

z

z

z

z

z

z

z

z

Data Sheet U14373EJ3V0DS

33

Instruc­tion

Binomial
operation

Uninom­inal
operation

Instruction
Name

Less than ro″ = LT (ro, ro′)

Clear CLR (ro)

Mnemonic Operation

if (ro < ro′)

″ ←

{ro

0x0000000001}

″ ←

else {ro

0x0000000000}

ro ← 0x0000000000
Increment ro′ = ro + 1 ro′ ← ro + 1
Decrement ro′ = ro − 1ro

′ ←

ro − 1

Absolute value ro′ = ABS (ro) if (ro < 0)

{ro′ ← −ro}

else {ro′ ← ro}
1’s

ro′ = ~ro ro′ ← ~ro

complement
2’s

ro′ = −ro ro′ ← −ro

complement
Clip ro′ = CLIP (ro)

if ( ro > 0x007FFFFFFF)

′ ←

{ro

0x007FFFFFFF}
elseif {ro < 0xFF80000000}
{ro′ ← 0xFF80000000}

′ ←

else {ro

ro}

µµµµ

PD77113A, 77114

Instructions Si m ul taneously Written Flag

Trino­mial

Bino­mial

Unino­minal

Load/
store

Trans­fer

Imme­diate­value

Bran­ch

√

√√
√√
√√
√√

√√

√√

√√

Loop

Cont­rol

OV

z

z

z

z

Round ro′ = ROUND (ro)

if (ro > 0x007FFF0000)

′ ←

{ro

0x007FFF0000}
elseif {ro < 0xFF80000000}
{ro′ ← 0xFF80000000}

′ ←

else {ro
& 0xFFFFFF0000}

Exponent ro′ = EXP (ro)

ro′ ← log

Substitution ro′ = ro ro′ ← ro
Accumulated

ro′ + = ro ro′ ← ro′ + ro

addition
Accumulated

ro′ − = ro ro′ ← ro′ − ro

subtraction
Division ro′ / = ro

if (sign (ro′) == sign (ro))

′ ←

{ro

(ro′ − ro) << 1}

else

′ ←

{ro

(ro′ + ro)<<1}

if (sign (ro

′ ←

{ro

ro′ + 1}

(ro + 0x8000)

1

2

(

)

ro

′

)==0)

√√

√√
√√

z

z

z

√√

√√

√√

34

Data Sheet U14373EJ3V0DS

Instruc­tion

Load/
store

Register­to-register
transfer

Immediate
value
setting

Instruction
Name

Parallel
load/store

Partial load/
store

addressing
load/store

Notes 1, 2

Notes 1, 2, 3

Note 4

Immediate
value index
load/store

Note 5

Register-to­register

Note 6

transfer
Immediate

value setting

Mnemonic Operation

ro = *dpx_mod ro′ =

ro ← *dpx, ro′ ← *dpy

*dpy_mod
ro = *dpx_mod

ro ← *dpx, *dpy ←rh

*dpy_mod = rh
*dpx_mod = rh ro =

*dpx ← rh, ro ← *dpy

*dpy_mod
*dpx_mod = rh

*dpy_mod = rh

′

dest = *dpx_mod
dest′ = *dpy_mod

dest = *dpx_mod
*dpy_mod = source

*dpx_mod = source
dest = *dpy_mod

*dpx_mod = source
*dpy_mod = source

*dpx ← rh, *dpy ← rh

dest ← *dpx,
dest′ ← *dpy

dest ← *dpx,
*dpy ← source

*dpx ← source,
dest ← *dpy

*dpx ← source,
*dpy ← source

′

dest = *addr dest ← *addrDirect
*addr = source *addr ← source

dest = *dp_imm dest ← *dp
*dp_imm = source *dp ← source

dest = rl dest ← rl
rl = source rl ← source

rl = imm

rl ← imm

(where imm = 0 to 0xFFFF)
dp = imm

dp ← imm

(where imm = 0 to 0xFFFF)
dn = imm

dn ← imm

(where imm = 0 to 0xFFFF)
dm = imm

dm ← imm

(where imm = 1 to 0xFFFF)

µµµµ

PD77113A, 77114

Instructions Si m ul taneously Written Flag

Trino-

Bino-

Unino-

mial

mial

minal

√√√

Load/
store

Trans­fer

Imme­diate­value

Bran­ch

Loop

Cont­rol

OV

z

′

z

′

z

z

√

z

z

Notes 1.

Of the two mnemonics, either one of them or both can be written.
After transfer, modification specified by mod is performed.

2.

Select any of dest, dest’ = {ro, reh, re, rh, rl}, source, source’ = {re, rh, rl}.

3.

Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl},

4.

Select any of dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}.

5.

Select any register other than general-purpose registers as dest and source.

6.

Data Sheet U14373EJ3V0DS

addr =

0: X-0xFFF
0: Y-0xFFFF

: X (X memory)
: Y (Y memory)

.

35

Instruc­tion

Instruction
Name

Mnemonic Operation

µµµµ

PD77113A, 77114

Instructions Si m ul taneously Written Flag

Trino­mial

Bino­mial

Unino­minal

Load/
store

Trans­fer

Imme­diate­value

Bran­ch

Loop

Cont­rol

OV

Branch

Hard­ware
loop

Jump JMP imm PC ← imm
Register

JMP dp PC ← dp

indirect jump
Subroutine call CALL imm SP ← SP + 1

STK ← PC + 1
PC ← imm

Register
indirect
subroutine call

CALL dp SP ← SP + 1

STK ← PC + 1
PC ← dp

Return RET PC ← STK

SP ← SP − 1

Interrupt return RETI PC ← STK

STK ← SP − 1
Recovery of interrupt
enable flag

Repeat REP count

Start RC ← count

During repeat PC

End PC

Loop LOOP count

Start RC ← count

(instruction of two or
more lines)

During repeat PC

End PC

RF

RC

RF

RF

RC

RF

←

←
←
←

←

←

←
←
←

←

0
PC
RC − 1
PC + 1
1

0
PC
RC − 1
PC + 1
1

√

z

√

z

√

z

√

z

√

z

√

z

z

z

Control

36

Loop hop LPOP LC ← LSR3

LE ← LSR2
LS ← LSR1

LSP ← LSP − 1
No operation NOP PC ← PC + 1
Halt HALT CPU stops.
Stop STOP CPU, PLL, and

OSC stop.
Condition IF (ro cond) Condition test
Forget interrupt FINT Discard interrupt

request

Data Sheet U14373EJ3V0DS

√√√

z

z

z

z

z

z

10. ELECTRICAL SPECIFICATIONS

µµµµ

PD77113A, 77114

Absolute Maximum Ratings (TA = +25

C)

°°°°

Parameter Symbol Condition Rating Unit

DD

IV

EV
Input voltage V
Output voltage V
Storage temperature T
Operating temperature T

O

stg

A

DD

I

For DSP core
For I/O pins
VI < EVDD + 0.5 V

0.5 to +3.6 VSupply voltage

−

0.5 to +4.6 V

−

0.5 to +4.1 V

−

0.5 to +4.1 V

−

65 to +150

−

40 to +85

−

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used unber
conditions that ensure that the absolute maximum ratings are not exceeded.

Recommended Operating Conditions

Parameter Symbol Condition MIN. TYP. MAX. Unit

DD

Operating voltage

IV

EV

Input voltage V

For DSP core 1.8 2.7 V

DD

For I/O
pins

I

IVDD = 1.8 to 2.7 V 3.3

DD

IV

= 2.3 to 2.7 V

2.7

0EV

3.6

DD

C

°

C

°

V

V

Capacitance (TA = +25

C, IVDD = 0 V, EVDD = 0 V)

°°°°

Parameter Symbol Condition MIN. TYP. MAX. Unit
Input capacitance C
Output capacitance C
I/O capacitance C

I

f = 1 MHz,
Pins other than those

O

IO

tested: 0 V

10 pF
10 pF
10 pF

Data Sheet U14373EJ3V0DS

37

µµµµ

PD77113A, 77114

DC Characteristics (Unless otherwise specified, TA =

operating condition range)

Parameter Symbol Condition MIN. TYP. MAX. Unit

IHN

High-level input voltage

Low-level output voltage V
High-level input leakage

current
Low-level input leakage

current
Pull-up pin current I
Pull-down pin current I
Internal supply current

IHN

[V

IHS

= V

= EVDD, VIL = 0 V,

I

no load]

V
V

V

DD

I

I

V
V

I

I

DDH

DDS

LH

PUI

PDI

Pins other than below 0.7 EV

IHS

CLKIN, RESET,
INT1 - INT4, SCK1, SIEN1,
SOEN1, SCK2, SIEN2, SOEN2

IHC

CLKIN 0.5 EV

IL

Pins other than below 0 0.2 EV

IC

CLKIN 0 0.5 EV

OH

IOH = −2.0 mA 0.7 EV
IOH = −100 µA 0.8 EV

OL

IOL = 2.0 mA 0.2 EV
Other than TDI, TMS, and TRST

I

DD

V

= EV

LL

Other than TDI, TMS, and TRST

I

V

= 0 V
TDI, TMS, 0 V ≤ VI ≤ EV
TRST, 0 V ≤ VI ≤ EV

Note

During operating, 30 ns, IVDD =

2.7 V
In halt mode, tcC = 30 ns,

divided by eight, IV
In stop mode, 0°C < TA < 60°C 100

40 to +85

−−−−

DD

DD

DD

= 2.7 V

C, with IVDD and EVDD within recommended

°°°°

0.8 EV

DD

DD

DD

EV
EV

EV

DD

DD

DD

V
V

V

+0.25

DD

DD

VLow-level input voltage
V

–0.25

DD

DD

DD

010

10 0

−

250 0

−

0 250

VHigh-level output voltage V
V
V

A

µ

A

µ

A

µ

A

µ

TBD 75 mA

TBD 10 mA

A

µ

38

The TYP. values are when an ordinary program is executed.

Note

The MAX. values are when a special program that brings about frequent switching inside the device is
executed.

Data Sheet U14373EJ3V0DS

Common Test Criteria of Switching Characteristics

CLKIN, RESET, INT1 - INT4,
SCK1, SIEN1, SOEN1, SCK2,
SIEN2, SOEN2

Input

(other than above)

0.8 EV

0.5 EV

0.2 EV

0.7 EV

0.5 EV

0.2 EV

0.5 EV

µµµµ

PD77113A, 77114

DD
DD
DD

DD
DD
DD

DD

Test points

Test points

Test pointsOutput

0.8 EV

0.5 EV

0.2 EV

0.7 EV

0.5 EV

0.2 EV

0.5 EV

DD
DD
DD

DD
DD
DD

DD

Data Sheet U14373EJ3V0DS

39

µ

PD77113A, 77114

A

=

AC Characteristics (T

40 to +85

−−−−

Clock

Timing requirements

Parameter Symbol Condition MIN. TYP. MAX. Unit

CLKIN cycle time

CLKIN high-level width t
CLKIN low-level width t
CLKIN rise/fall time t

requirements

Note 1

Note 3

µµµµ

PD77113A, 77114

C, with IVDD and EVDD within recommended operating condition range)

°°°°

cCX

t

Note 2

IVDD = 1.8
to 2.7 V

PLL lock
range

IVDD = 2.3

25 ns

25 × m 50 × mns

10 × m 50 × mns

to 2.7 V

wCXH

wCXL

rfCX

cC (R)

t

IVDD = 1.8 to 2.7 V 25 nsInternal clock cycle time

12.5 ns

12.5 ns
5ns

IVDD = 2.3 to 2.7 V 13.3 ns

Notes 1.

m: Multiple, n: Division ratio
This is the range in which the PLL is locked (stably oscillates). Input t

2.

cCX

3.

Input t

so that the value of (t

Switching characteristics

Parameter Symbol Condition MIN. TYP. MAX. Unit

Internal clock cycle

CLKOUT cycle time t
CLKOUT width t

CLKOUT rise/fall time t

m: Multiple, n: Division ratio, l: HALT division ratio

Note

Note

cC

t

cCO

wCO

rfCO

dCO

cCX

within this range.

cCX

÷ m × n) satisfies this condition.

During normal operation t
In HALT mode

During
normal
operation

n = 1, or even number
n = odd number

(other than 1)

In HALT mode

tcC ÷ 2 − 3ns

cC

÷ n ÷ 2 − 3

t

tcC ÷ n ÷ 2 − 3

cCX

× n ÷ mns

cCX

t

× n ÷ m × l

cC

t

5ns

IVDD = 1.8 to 2.7 V 20 nsCLK OUT del ay time t
IVDD = 2.3 to 2.7 V 15 ns

ns
ns

ns

ns

40

Data Sheet U14373EJ3V0DS

µ

Clock I/O timing

CLKIN

Internal clock

µµµµ

PD77113A, 77114

PD77113A, 77114

t

cCX

t

t

wCXH

t

dCO

t

wCO

t

cC, tcC(R)

t

cCO

t

wCXL

t

wCO

rfCX

t

rfCO

t

rfCX

t

rfCO

CLKOUT

Data Sheet U14373EJ3V0DS

41

µ

PD77113A, 77114

Reset, Interrupt

Timing requirements

Parameter Symbol Condition MIN. TYP. MAX. Unit

WAKEUP low-level width t
INT1 - INT4 low-level width t
INT1 - INT4 recovery time t

Notes 1.

The value on power application is the time from when the supply voltages have reached IV
and EVDD = 2.7 V. A stable clock input is also required.
Note that tcC is I (I = integer of 1 to 16) times that during normal operation in the HALT mode.

2.

If the low-level width of RESET is greater than 1024tcC, the PLL initialization mode is triggered. If there

3.

is no need to use the PLL initialization mode, set the width to less than 1024tcC.
When the power is turned on, a recovery period of 4t

4.

w (RL)

rec (R)

w (WAKEUPL)

w (INTL)

rec (INT)

On power application

Note 1

in STOP mode
During normal operation,

in HALT mode
On power application

Note 4

µµµµ

PD77113A, 77114

,

100 +

2048t

cC

4t

4t

cC

4t

cCX

Note 2

Note 2

cCX

Note 3

100

Note 2

cC

3t

cC

3t

cCX

is necessary before inputting RESET.

µ

ns

nsRESET recovery time t
ns

µ

ns
ns

DD

= 1.8 V

sRESET low-level width t

s

Reset timing

RESET

WAKEUP timing

WAKEUP

Interrupt timing

INT1 - INT4

t

w(RL)

t

w (WAKEUPL)

t

w(INTL)

t

rec(R)

t

rec(INT)

42

Data Sheet U14373EJ3V0DS

µµµµ

µ

PD77113A, 77114

PD77113A, 77114

External Data Memory Access (

Timing requirements

Parameter Symbol Condition MIN. TYP. MAX. Unit
Read data setup time t
Read data hold time t

Switching characteristics

Parameter Symbol Condition MIN. TYP. MAX. Unit
Address cycle time t
Address output hold time t
MRD output delay time t
Write data output valid ti m e t
Write data output hold time t
MWR output delay time t
MWR output hold time t
MWR low-level width t
MWR high-level width t

PD77114 only)

µµµµ

suDDRD

hDDRD

rcDA

hDA

dDR

vDDWD

hDDWD

dDW

hDA

wDWL

wDWH

18 ns

0ns

Note

cDW

tcC + (tcC × t

)

ns

0ns

5ns

5ns
0ns
0 0.5 t

cC

ns

0ns

cDW

tcC × t

− 3

ns

0.5 tcC − 3ns

Note

cDW

: Number of data wait cycles

t

Data Sheet U14373EJ3V0DS

43

µ

PD77113A, 77114

External data memory access timing (read)

DA0 - DA12

X/Y

t

dDR

MRD

D0 - D15

External data memory access timing (write)

DA0 - DA12

t

rcDA

t

suDDRD

µµµµ

PD77113A, 77114

t

dDR

t

hDDRD

X/Y

MWR

D0 - D15

t

t

t

vDDWD

dDW

t

wDWL

rcDA

t

wDWH

t

dDW

t

vDDWD

t

hDA

t

hDDWD

Hi-Z Hi-Z

44

Data Sheet U14373EJ3V0DS

µµµµ

µ

PD77113A, 77114

PD77113A, 77114

Bus Arbitration (

PD77114 only)

µµµµ

Timing requirements

Parameter Symbol Condition MIN. TYP. MAX. Unit
HOLDRQ setup time t
HOLDRQ hold time t

Switching characteristics

Parameter Symbol Condition MIN. TYP. MAX. Unit
BSTB hold time t
BSTB output delay ti m e t
HOLDAK output delay time t
Data hold time during bus

arbitration
Data valid time during bus

arbitration

suHRQ

hHRQ

hBS

dBS

dHAK

h (BS-D)

t

v (BS-D)

t

0ns
0ns

0ns

20 ns
18 ns
25 ns

25 ns

Data Sheet U14373EJ3V0DS

45

µ

PD77113A, 77114

Bus arbitration timing (when bus is idle)

CLKIN

µµµµ

PD77113A, 77114

(Bus busy) Bus idle

t

hBS

BSTB

suHRQ

t

HOLDRQ

HOLDAK

X/Y, DA0 - DA12,

MRD, MWR

Bus arbitration timing (when bus is busy)

CLKIN

(Bus busy) Bus busy

Bus release Bus idle (Bus busy)

dBS

t

t

t

dHAK

t

h (BS-D)

hHRQ

t

suHRQ

Hi-Z

Bus idle Bus idle (Bus busy)

t

hBS

Bus release

t

dBS

t

dHAK

t

v (BS-D)

t

hHRQ

BSTB

HOLDRQ

HOLDAK

X/Y, DA0 - DA12,

MRD, MWR

t

suHRQ

t

hHRQ

t

dHAK

t

h (BS-D)

Hi-Z

t

suHRQ

t

dHAK

t

v (BS-D)

t

hHRQ

46

Data Sheet U14373EJ3V0DS

µ

Serial Interface

Timing requirements

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD77113A, 77114

PD77113A, 77114

SCK cycle time t
SCK high-/low-level widt h t
SCK rise/fall time t

Switching characteristics

cSC

wSC

rfSC

suSOE

hSOE

suSIE

hSIE

suSI

hSI

60 ns
25 ns

20 ns

IVDD = 1.8 to 2.7 V

10

nsSOEN setup time t
IVDD = 2.3 to 2.7 V 5 ns
IVDD = 1.8 to 2.7 V 15 nsSOEN hold time t
IVDD = 2.3 to 2.7 V 10 ns
IVDD = 1.8 to 2.7 V 10 nsSIEN setup time t
IVDD = 2.3 to 2.7 V 5 ns
IVDD = 1.8 to 2.7 V 15 nsSIEN hold time t
IVDD = 2.3 to 2.7 V 10 ns
IVDD = 1.8 to 2.7 V 10 nsSI setup time t
IVDD = 2.3 to 2.7 V 5 ns
IVDD = 1.8 to 2.7 V 15 nsSI hold time t
IVDD = 2.3 to 2.7 V 10 ns

Parameter Symbol Condition MIN. TYP. MAX. Unit

SORQ hold time t

SO hold time t

SIAK hold time t

dSOR

hSOR

dSO

hSO

dSIA

hSIA

IVDD = 1.8 to 2.7 V 30 nsS ORQ output delay time t
IVDD = 2.3 to 2.7 V 25 ns

0ns
IVDD = 1.8 to 2.7 V 30 nsS O output delay time t
IVDD = 2.3 to 2.7 V 25 ns

0ns
IVDD = 1.8 to 2.7 V 30 nsS I AK output delay time t
IVDD = 2.3 to 2.7 V 25 ns

0ns

Data Sheet U14373EJ3V0DS

47

µµµµ

µ

PD77113A, 77114

PD77113A, 77114

Caution If noise is superimposed on the serial clock, the serial interface may be deadlocked. Bear in

mind the following points when designing your system:

• Reinforce the wiring for power supply and ground (if noise is superimposed on the power and
ground lines, it has the same effect as if noise were superimposed on the serial clock).

• Shorten the wiring between the device's SCK1 and SCK2 pins, and clock supply source.

• Do not cross the signal lines of the serial clock with any other signal lines. Do not route the
serial clock line in the vicinity of a line through which a high alternating current flows.

• Supply the clock to the SCK1 and SCK2 pins of the device from the clock source on a one-to­one basis. Do not supply clock to several devices from one clock source.

• Exercise care that the serial clock does not overshoot or undershoot. In particular, make sure
that the rising and falling of the serial clock waveform are clear.

××

Make sure that the serial clock
rises and falls linearly.

The serial clock must not bound. Noise
must not be superimposed on the serial clock.

The serial clock must not rise or
fall step-wise.

48

Data Sheet U14373EJ3V0DS

µ

Serial output timing 1

t

wSC

SCK1,

SCK2

t

dSOR

t

cSC

t

wSC

t

hSOR

µµµµ

PD77113A, 77114

PD77113A, 77114

t

rfSC

t

rfSC

SORQ1

t

t

suSOE

t

hSOE

suSOE

t

hSOE

SOEN1,

SOEN2

t

SO1,

Hi-Z

SO2

Serial output timing 2 (during successive output)

t

cSC

t

wSC

SCK1,

SCK2

SORQ1

SOEN1,

SOEN2

t

wSC

t

dSOR

t

suSOE

t

hSOE

dSO

t

hSOR

t

dSO

1st Last

t

rfSC

t

rfSC

t

hSO

SO1,

SO2

t

dSO

Last

Data Sheet U14373EJ3V0DS

1st Last

t

hSO

49

µ

PD77113A, 77114

Serial input timing 1

SCK1,

SCK2

SIAK1

SIEN1,

SIEN2

t

dSIA

t

wSC

t

suSIE

µµµµ

PD77113A, 77114

t

cSC

t

wSC

t

hSIA

t

suSIE

t

hSIE

t

hSIE

t

suSI

t

hSI

t

rfSC

t

rfSC

SI1,

SI2

Serial input timing 2 (during successive input)

t

cSC

t

wSC

SCK1,

SCK2

SIAK1

SIEN1,

SIEN2

SI1,

SI2

t

wSC

t

dSIA

t

suSIE

LastLast–1 2nd

1st

t

hSIA

t

hSIE

t

suSI

t

hSI

2nd

rfSC

t

1st

3rd

t

rfSC

3rd

50

Data Sheet U14373EJ3V0DS

µ

Host Interface

Timing requirements

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD77113A, 77114

PD77113A, 77114

HRD width t
HCS, HA0, HA1, read hold

time
HCS, HA0, HA1 write hold time t
HRD, HWR recovery time t

HWR width t
HWR hold time t

Switching characteristics

Parameter Symbol Condition MIN. TYP. MAX. Unit

HRD hold time t

dHR

wHR

hHCAR

t

hHCAW

recHS

dHW

wHW

hHDW

suHDW

dHE

hHE

vHDR

hHDR

IVDD = 1.8 to 2.7 V 15 nsHRD delay time t
IVDD = 2.3 to 2.7 V 10 ns

60 ns

0ns

0ns

60 ns
IVDD = 1.8 to 2.7 V 15 nsHWR delay time t
IVDD = 2.3 to 2.7 V 10 ns

60 ns

0

ns
IVDD = 1.8 to 2.7 V 15 nsHWR setup time t
IVDD = 2.3 to 2.7 V 10 ns

IVDD = 1.8 to 2.7 V 30 nsHRE , HWE output delay time t
IVDD = 2.3 to 2.7 V 25 ns
IVDD = 1.8 to 2.7 V 30 nsHRE , HWE hold time t
IVDD = 2.3 to 2.7 V 25 ns
IVDD = 1.8 to 2.7 V 30 nsHRD v a l i d time t
IVDD = 2.3 to 2.7 V 25 ns

0ns

Data Sheet U14373EJ3V0DS

51

µ

PD77113A, 77114

Host read interface timing

CLKIN

HCS, HA0, HA1

HRD

HD0 - HD7

HRE

µµµµ

PD77113A, 77114

t

hHCAR

t

dHR

t

dHE

t

hHE

t

vHDR

t

wHR

t

hHDR

t

recHS

Hi-ZHi-Z

Host write interface timing

CLKIN

HCS, HA0, HA1

HWR

HD0 - HD7

HWE

t

hHCAW

t

dHW

t

dHE

t

hHE

t

wHW

t

suHDW

t

hHDW

t

recHS

52

Data Sheet U14373EJ3V0DS

µ

General-purpose I/O Port

Timing requirements

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD77113A, 77114

PD77113A, 77114

Port input setup time t

Switching characteristics

Parameter Symbol Condition MIN. TYP. MAX. Unit

General-purpose I/O port timing

CLKIN

P0 - P3

(Output)

suPI

hPI

dPO

0ns
IVDD = 1.8 to 2.7 V 15 nsPort input hold time t
IVDD = 2.3 to 2.7 V 10 ns

IVDD = 1.8 to 2.7 V 30 nsP ort output delay time t
IVDD = 2.3 to 2.7 V 25 ns

t

dPO

P0 - P3

(Input)

t

suPI

t

hPI

Data Sheet U14373EJ3V0DS

53

µ

PD77113A, 77114

Debugging Interface (JTAG)

Timing requirements

Parameter Symbol Condition MIN. TYP. MAX. Unit

µµµµ

PD77113A, 77114

TCK cycle time t
TCK high-/low-level width t
TCK rise/fall time t

TRST setup time t

Switching characteristics

Parameter Symbol Condition MIN. TYP. MAX. Unit

cTCK

wTCK

rfTCK

suDI

hDI

suJIN

hJIN

suTRST

dDO

dJOUT

120 ns

50 ns

20 ns
IVDD = 1.8 to 2.7 V 25 nsTMS, TDI setup time t
IVDD = 2.3 to 2.7 V 20 ns
IVDD = 1.8 to 2.7 V 25 nsTMS, TDI hold time t
IVDD = 2.3 to 2.7 V 20 ns
IVDD = 1.8 to 2.7 V 25 nsInput pin setup time t
IVDD = 2.3 to 2.7 V 20 ns
IVDD = 1.8 to 2.7 V 25 nsInput pin hold time t
IVDD = 2.3 to 2.7 V 20 ns

100 ns

IVDD = 1.8 to 2.7 V 25 nsTDO out put del ay time t
IVDD = 2.3 to 2.7 V 20 ns
IVDD = 1.8 to 2.7 V 25 nsOut put pi n output delay time t
IVDD = 2.3 to 2.7 V 20 ns

54

Data Sheet U14373EJ3V0DS

µ

Debugging interface timing

t

cTCK

t

wTCK

t

wTCK

TCK

t

suTRST

TRST

µµµµ

PD77113A, 77114

PD77113A, 77114

t

rfTCK

t

suDI

t

hDI

t

rfTCK

TMS, TDI

TDO

Capture state

Update state

Remark

For details of JTAG, refer to

Valid

t

dDO

IEEE1149.1

Valid Valid

Valid

dJOUT

t

.

t

suJIN

t

hJIN

Data Sheet U14373EJ3V0DS

55

11. PACKAGE DRAWINGS

80-PIN PLASTIC FBGA (9x9)

µµµµ

PD77113A, 77114

Q

S

R

KS

A

WSB

B

D

C

PIndex mark

WSA

J

I

Y1 S

H

FEG

M

φ

SML

AB

B

9
8

A

7
6
5
4
3
2
1

JABCDEFGH

ITEM MILLIMETERS

A 9.00±0.10
B

8.40
C 8.40
D 9.00±0.10

E

1.30

F 0.8 (T.P.)
G 0.35±0.1
H

0.36

0.96

I
J 1.31±0.15
K 0.10

+0.05

L

M 0.08

P

Q R0.3
R25°
W

Y1 0.20

0.50

φ

–0.10

C1.0

0.20

S80F1-80-CN1-1

56

Data Sheet U14373EJ3V0DS

100-PIN PLASTIC TQFP (FINE PITCH) (14x14)

A
B

µµµµ

PD77113A, 77114

75

76

100

1

51

25

50

26

F

G

M

H

I

P

SN

NOTE

Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.

J

K

L

M

C D

detail of lead end

S

Q

R

ITEM MILLIMETERS

A

16.0±0.2

B

14.0±0.2
C 14.0±0.2
D

16.0±0.2
F 1.0
G

1.0
H 0.22

I 0.10
J
K
L

M 0.145

N
P
Q

R3°

S 1.27 MAX.

+0.05

−0.04

0.5 (T.P.)

1.0±0.2

0.5±0.2

+0.055

−0.045

0.10

1.0±0.1

0.1±0.05

+7°

−3°

S100GC-50-9EU-2

Data Sheet U14373EJ3V0DS

57

µµµµ

PD77113A, 77114

12. RECOMMENDED SOLDERING CONDITIONS

It is recommended to solder this product under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document

Mounting Technology Manual (C10535E)

.

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Surface mount type

PD77113AF1-xxx-CN1: 80-pin plastic fine-pitch BGA (9 x 9)

µµµµ

Semiconductor Device

Soldering

Method

Infrared reflow Package peak temperature: 230°C, Time: 30 sec. Max. (at 210°C or higher).

Count: two times or less
Exposure limit: 3 day s

After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Note

PD77114GC-xxx-9EU: 100-pin plastic TQFP (fine-pitch) (14 x 14)

µµµµ

Soldering

Method

Infrared reflow Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher).

Count: two times or less
Exposure limit: 3 day s

VPS Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher).

Count: two times or less
Exposure limit: 3 day s

Partial heating Pin temperature: 300°C Max., Time: 3 sec . M ax. (per pin row) –

Note

Note

Note

Soldering Conditions Recommended

Condition Symbol

IR30-103-2

(after that prebake at 125°C for 10 hours)

Soldering Conditions Recommended

Condition Symbol

IR35-103-2

(after that prebake at 125°C for 10 hours)

VP15-103-2

(after that prebake at 125°C for 10 hours)

After opening the dry pack, store is at 25°C or less and 65% RH or less for the allowable storage period.

Note

Caution Do not use different soldering methods together (except for partial heating for pins).

58

Data Sheet U14373EJ3V0DS

[MEMO]

µµµµ

PD77113A, 77114

Data Sheet U14373EJ3V0DS

59

µµµµ

PD77113A, 77114

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

60

Data Sheet U14373EJ3V0DS

µµµµ

PD77113A, 77114

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore
Tel: [phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP Brasil
Tel: [phone]
Fax: [phone]

Data Sheet U14373EJ3V0DS

J00.7

61

µµµµ

PD77113A, 77114

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

•

The information in this document is current as of January, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

•

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.

•

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.

•

NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4