Datasheet UPD75P0116GB-3BS-MTX, UPD75P0116CU Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD75P0116

4-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The µPD75P0116 replaces the µPD750108’s internal mask ROM with a one-time PROM and features expanded

ROM capacity.

µ

Because the

development using the

Detailed information about product features and specifications can be found in the following document

PD75P0116 supports programming by users, it is suitable for use in prototype testing for system

µ

PD750104, 750106, or 750108 products, and for use in small-lot production.

µ

PD750108 User's Manual: U11330E

FEATURES

• Compatible with µPD750108

• Memory capacity:

• PROM : 16384 × 8 bits

• RAM : 512 × 4 bits

µ

• Can operate in same power supply voltage as the mask ROM version

DD = 1.8 to 5.5 V

• V

ORDERING INFORMATION

Part number Package ROM (× 8 bits)

µ

PD75P0116CU 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 16384

µ

PD75P0116GB-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) 16384

Caution On-chip pull-up resistors by mask option cannot be provided.

PD750108

Document No. U12603EJ1V0DS00 (1st edition)
Date Published June 1997 N
Printed in Japan

The information in this document is subject to change without notice.

©

1997

µ

PD75P0116

FUNCTION LIST

Item Function

Instruction execution time • 4, 8, 16, 64 µs (main system clock: at 1.0 MHz operation)

• 2, 4, 8, 32 µs (main system clock: at 2.0 MHz operation)

• 122 µs (subsystem clock: at 32.768 kHz operation)

On-chip memory PROM 16384 × 8 bits

RAM 512 × 4 bits

General register • In 4-bit operation: 8 × 4 banks

• In 8-bit operation: 4 × 4 banks

I/O port CMOS input 8 Connection of on-chip pull-up resistor specifiable by software: 7

CMOS I/O 18 Direct LED drive capability

Connection of on-chip pull-up resistor specifiable by software: 18

N-ch open drain I/O 8 Direct LED drive capability

13 V withstand voltage

Total 34

Timer 4 channels

• 8-bit timer/event counter: 1 channel

• 8-bit timer counter: 1 channel (with watch timer output function)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

Serial interface • 3-wire serial I/O mode ... Switching of MSB/LSB-first

• 2-wire serial I/O mode

• SBI mode
Bit sequential buffer (BSB) 16 bits
Clock output (PCL) • Φ, 125, 62.5, 15.6 kHz (main system clock: at 1.0 MHz operation)

• Φ, 250, 125, 31.3 kHz (main system clock: at 2.0 MHz operation)
Buzzer output (BUZ) • 2, 4, 32 kHz (subsystem clock: at 32.768 kHz operation)

• 0.488, 0.977, 7.813 kHz (main system clock: at 1.0 MHz operation)

• 0.977, 1.953, 15.625 kHz (main system clock: at 2.0-MHz operation)
Vectored interrupt External: 3 Internal: 4
Test input External: 1 Internal: 1
System clock oscillation circuit • Main system clock oscillation RC oscillation circuit (with external resistor and capacitor)

• Subsystem clock oscillation crystal oscillation circuit
Standby function STOP/HALT mode
Operating ambient temperature TA = –40 to +85 ˚C
Supply voltage VDD = 1.8 to 5.5 V
Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)

2

µ

PD75P0116

TABLE OF CONTENTS

1. PIN CONFIGURATION (Top View) .................................................................................................... 4

2. BLOCK DIAGRAM............................................................................................................................. 6

3. PIN FUNCTIONS................................................................................................................................ 7

3.1 Port Pins ..................................................................................................................................................... 7

3.2 Non-port Pins ............................................................................................................................................. 8

3.3 I/O Circuits for Pins ................................................................................................................................... 9

3.4 Handling of Unused Pins ........................................................................................................................ 11

4. SWITCHING BETWEEN MK I AND MK II MODES .......................................................................... 12

4.1 Differences between Mk I Mode and Mk II Mode................................................................................... 12

4.2 Setting of Stack Bank Selection (SBS) Register................................................................................... 13

5. DIFFERENCES BETWEEN µPD75P0116 AND µPD750104, 750106, AND 750108 ...................... 14

6. MEMORY CONFIGURATION ........................................................................................................... 15

7. INSTRUCTION SET .......................................................................................................................... 17

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY................................................... 28

8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 28

8.2 Steps in Program Memory Write Operation .......................................................................................... 29

8.3 Steps in Program Memory Read Operation........................................................................................... 30

8.4 One-Time PROM Screening .................................................................................................................... 31

9. ELECTRICAL SPECIFICATIONS..................................................................................................... 32

10. CHARACTERISTIC CURVES (REFERENCE VALUE) .................................................................... 46

11. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUE)...... 47

12. PACKAGE DRAWINGS .................................................................................................................... 49

13. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 51

APPENDIX A. FUNCTION LIST OF µPD750008, 750108, AND 75P0116............................................. 52

APPENDIX B. DEVELOPMENT TOOLS................................................................................................. 54

APPENDIX C. RELATED DOCUMENTS ................................................................................................ 58

3

1. PIN CONFIGURATION (Top View)

•42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

µ

PD75P0116CU

µ

PD75P0116

XT1
XT2

RESET

CL1

CL2
P33/MD3
P32/MD2
P31/MD1
P30/MD0

P81

P80

P03/SI/SB1

P02/SO/SB0

P01/SCK
P00/INT4

P13/TI0
P12/INT2
P11/INT1
P10/INT0

Note

VPP

VDD

Note Directly connect V

1
2

3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21

PP to VDD in the normal operation mode.

42
41

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

VSS
P40/D0

P41/D1
P42/D2
P43/D3
P50/D4
P51/D5
P52/D6
P53/D7
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ

• 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)

µ

PD75P0116GB-3BS-MTX

P73/KR7

P20/PTO0

44

10
11

43

1
2
3
4
5
6
7
8
9

12

13

NC

P43/D3

P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0

P53/D7
P52/D6
P51/D5
P50/D4

Note Directly connect V

Note

DD

P23/BUZ

V

39

38

17

18

SS

V

P40/D0

PP

V

P10/INT0

37

19

XT1

XT2

P11/INT1

36

35

20

21

RESET

P12/INT2

NC

34

33
32
31
30
29
28
27
26
25
24
23

22

CL1

CL2

P21/PTO1

P22/PCL

42

41

40

14

15

16

P42/D2

P41/D1

PP to VDD in the normal operation mode.

P13/TI0
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P80
P81
P30/MD0
P31/MD1
P32/MD2
P33/MD3

4

µ

PD75P0116

PIN NAMES

BUZ : Buzzer Clock P70-P73 : Port7
CL1, CL2 : Main System Clock (RC) P80, P81 : Port8
D0-D7 : Data Bus 0-7 PCL : Programmable Clock
INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 PTO0, PTO1 : Programmable Timer Output 0, 1
INT2 : External Test Input 2 RESET : Reset
KR0-KR7 : Key Return 0-7 SB0, SB1 : Serial Data Bus 0, 1
MD0-MD3 : Mode Selection 0-3 SCK : Serial Clock
NC : No Connection SI : Serial Input
P00-P03 : Port0 SO : Serial Output
P10-P13 : Port1 TI0 : Timer Input 0
P20-P23 : Port2 V
P30-P33 : Port3 VPP : Programming Power Supply
P40-P43 : Port4 V
P50-P53 : Port5 XT1, XT2 : Subsystem Clock (Crystal)
P60-P63 : Port6

DD : Positive Power Supply

SS : Ground

5

2. BLOCK DIAGRAM

µ

PD75P0116

TI0/P13

PTO0/P20

PTO1/P21

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT0/P10
INT1/P11
INT2/P12
INT4/P00

KR0/P60-
KR7/P73

BUZ/P23

BASIC INTERVAL
TIMER/
WATCHDOG
TIMER

INTBT

8-BIT
TIMER/EVENT
COUNTER #0

INTT0

8-BIT TIMER

COUNTER

CLOCKED
SERIAL
INTERFACE

INTCSI

INTERRUPT

CONTROL

8



#1

INTT1

WATCH

TIMER

INTW

RESET



TOUT0

TOUT0

PROGRAM

COUNTER (14)

PROGRAM

MEMORY

(PROM)

16384 × 8 BITS

CLOCK
OUTPUT
CONTROL

fx/2

CLOCK

DIVIDER

N

SYSTEM CLOCK

GENERATOR

ALU

DECODE

AND

CONTROL

CPU CLOCK

Φ

MAINSUB

CY

STAND BY
CONTROL

SP (8)

SBS

BANK

GENERAL 
REGISTER

DATA

MEMORY

(RAM)

512 × 4 BITS

BIT SEQ.

BUFFER (16)

PORT0 P00-P034

PORT1

PORT2 4

PORT3 P30/MD0-P33/MD34

PORT4 P40/D0-P43/D34

PORT5 P50/D4-P53/D74

PORT6 P60-P634

PORT7 P70-P734

PORT8 P80, P812

P10-P134

P20-P23

PCL/P22

XT1

XT2

CL2CL1

VSSVDD RESETVPP

6

3. PIN FUNCTIONS

3.1 Port Pins

µ

PD75P0116

Pin name I/O Shared by Function 8-bit When I/O circuit

P00 I INT4 This is a 4-bit input port (PORT0). × Input <B>
P01 I/O SCK are software-specifiable in 3-bit units. <F>-A
P02 I/O SO/SB0 <F>-B
P03 I/O SI/SB1 <M>-C
P10 I INT0 This is a 4-bit input port (PORT1). × Input <B>-C
P11 INT1 specifiable in 4-bit units.
P12 INT2
P13 TI0
P20 I/O PTO0 This is a 4-bit I/O port (PORT2). × Input E-B
P21 PTO1 specifiable in 4-bit units.
P22 PCL
P23 BUZ
P30 I/O MD0 This is a programmable 4-bit I/O port (PORT3). × Input E-B
P31 MD1 units. On-chip pull-up resistor connections are
P32 MD2
P33 MD3

Note 2

P40

Note 2

P41

Note 2

P42

Note 2

P43

Note 2

P50

Note 2

P51

Note 2

P52

Note 2

P53
P60 I/O KR0 This is a programmable 4-bit I/O port (PORT6). Input <F>-A
P61 KR1 On-chip pull-up resistor connections are software­P62 KR2
P63 KR3

I/O D0 This is an N-ch open-drain 4-bit I/O port (PORT4). High-

D1
D2
D3

I/O D4 This is an N-ch open-drain 4-bit I/O port (PORT5). High-

D5
D6
D7

For P01 to P03, on-chip pull-up resistor connections

On-chip pull-up resistor connections are software­P10/INT0 can select noise elimination circuit.

On-chip pull-up resistor connections are software-

Input and output can be specified in single-bit
software-specifiable in 4-bit units.

In the open-drain mode, withstands up to 13 V. impedance M-E

In the open-drain mode, withstands up to 13 V. impedance M-E

Input and output can be specified in single-bit units.
specifiable in 4-bit units.

I/O reset type

Note 1

P70 I/O KR4 This is a 4-bit I/O port (PORT7). Input <F>-A

On-chip pull-up resistor connections are software-

P71 KR5 specifiable in 4-bit units.
P72 KR6
P73 KR7
P80 I/O — This is a 2-bit I/O port (PORT8). × Input E-B

On-chip pull-up resistor connections are software-

P81 — specifiable in 2-bit units.

Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.

2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.

7

3.2 Non-port Pins

µ

PD75P0116

Pin name I/O Shared by Function When I/O circuit

TI0 I P13 External event pulse input to timer/event counter Input <B>-C
PTO0 O P20 Timer/event counter output Input E-B
PTO1 P21 Timer counter output
PCL P22 Clock output
BUZ P23 Outputs any frequency (for buzzer or system clock trimming)
SCK I/O P01 Serial clock I/O Input <F>-A
SO/SB0 P02 Serial data output <F>-B

SI/SB1 P03 Serial data input <M>-C

INT4 I P00 Edge-triggered vectored interrupt input <B>

INT0 I P10 Edge-triggered vectored interrupt input With noise eliminator Input <B>-C

INT1 P11 circuit. Asynchronous
INT2 P12 Rising edge-triggered testable input Asynchronous
KR0-KR3 I P60-P63 Falling edge-triggered testable input Input <F>-A
KR4-KR7 I P70-P73 Falling edge-triggered testable input Input <F>-A
CL1 — — Resistor (R) and capacitor (C) connection for main system — —

CL2 —
XT1 I — Crystal resonator connection for subsystem clock. — —

XT2 — ed clock to X2. XT1 can be used as a 1-bit (test) input.
RESET I — System reset input (low level active) — <B>
MD0-MD3 I P30-P33 Mode selection for program memory (PROM) write/verify. Input E-B
D0-D3 I/O P40-P43 Data bus pin for program memory (PROM) write/verify. Input M-E
D4-D7 P50-P53

Note 2

VPP

VDD — — Positive power supply — —
VSS — — Ground potential — —

— — Programmable voltage supply in program memory (PROM) — —

Serial data bus I/O

Serial data bus I/O

(Detects both rising and falling edges).

(detected edge is selectable). /asynch selectable
INT0/P10 can select noise elimination

clock oscillation. External clock cannot be input.

If using an external clock, input it to XT1 and input the invert-

write/verify mode.
In normal operation mode, connect directly to VDD.
Apply +12.5 V in PROM write/verify mode.

reset type

Note 1

Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.

2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin.

8

3.3 I/O Circuits for Pins

The I/O circuits for the µPD75P0116’s pin are shown in schematic diagrams below.



TYPE A TYPE D

VDD

Data

IN

CMOS standard input buffer

P-ch

N-ch

Output

disable

Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).

µ

PD75P0116

VDD

P-ch

OUT

N-ch

(1/2)

TYPE E-BTYPE B

IN

Output

disable

Schmitt trigger input with hysteresis characteristics.

TYPE B-C TYPE F-A

VDD

P.U.R.

P-ch

P.U.R.
enable

Data

P.U.R.
enable

Type D

P.U.R. : Pull-Up Resistor

P.U.R.
enable

VDD

P.U.R.

P-ch

IN/OUT

Type A

VDD

P.U.R.

P-ch

IN

P.U.R. : Pull-Up Resistor

Data

Output

disable

Type D

IN/OUT

Type B

P.U.R. : Pull-Up Resistor

9

TYPE F-B

output
disable
(P)

data

output
disable

output
disable
(N)

P.U.R.
enable


V

DD

P.U.R. : Pull-Up Resistor

P-ch

N-ch

V

DD

IN/OUT

P.U.R.

P-ch

µ

TYPE M-E

data

output
disable

V

DD

Input
instruction

P-ch

P.U.R.

Note Pull-up resistor that operates only when an input
instruction has been executed. (Current flows
from V

DD

to the pins when at low level)

Note

Voltage

limitation

circuit

N-ch
(+13 V)

(+13 V)

PD75P0116

(2/2)

IN/OUT

TYPE M-C

data

output
disable

P.U.R.
enable


N-ch

P.U.R. : Pull-Up Resistor


V

DD

P.U.R.

P-ch

IN/OUT

10

3.4 Handling of Unused Pins

P00/INT4 Connect to VSS or VDD
P01/SCK Individually connect to VSS or VDD via resistor
P02/SO/SB0
P03/SI/SB1 Connect to VSS
P10/INT0-P12/INT2 Connect to VSS or VDD
P13/TI0
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
P30/MD0-P33/MD3
P40/D0-P43/D3 Connect to VSS
P50/D4-P53/D7
P60/KR0-P63/KR3
P70/KR4-P73/KR7
P80, P81

Note

XT1

Note

XT2
VPP Make sure to connect directly to VDD

Table 3-1. Handling of Unused Pins

Pin Recommended connection

Input mode : individually connect to VSS or VDD

via resistor

Output mode : open

Input mode : individually connect to VSS or VDD

via resistor

Output mode : open

Connect to VSS or VDD
Open

µ

PD75P0116

Note When the subsystem clock is not used, set SOS. 0 to 1 (not to use the internal feedback resistor).

11

µ

PD75P0116

4. SWITCHING BETWEEN MK I AND MK II MODES

Setting a stack bank selection (SBS) register for the µPD75P0116 enables the program memory to be switched
between the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD750104, 750106, or 750108
using the µPD75P0116.

µ

When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of

When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD750104, 750106, and 750108)

4.1 Differences between Mk I Mode and Mk II Mode

Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the

Table 4-1. Differences between Mk I Mode and Mk II Mode

Item Mk I mode Mk II mode
Program counter PC13-0
Program memory (bytes) 16384
Data memory (bits) 512 × 4
Stack Stack bank Selectable from memory banks 0 and 1

Stack bytes 2 bytes 3 bytes

Instruction BRA !addr1 None Provided

CALLA !addr1
Instruction CALL !addr 3 machine cycles 4 machine cycles
execution time CALLF !faddr 2 machine cycles 3 machine cycles
Supported mask ROM versions and Mk I mode of µPD750104, 750106, and Mk II mode of µPD750104, 750106, and

mode 750108 750108

PD750104, 750106, and 750108)

µ

PD75P0116.

Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This

mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes (usable area) used in execution of a
subroutine call instruction increases by 1 per stack compared to the Mk I mode. Furthermore, when
a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle.
Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.

12

µ

PD75P0116

4.2 Setting of Stack Bank Selection (SBS) Register

Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format

for doing this.

The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode,

Note

be sure to initialize the stack bank selection register to 100×B

Note

II mode, be sure to initialize it to 000×B

.

at the beginning of the program. When using the Mk

Note Set the desired value for ×.

Figure 4-1. Format of Stack Bank Selection Register

Address 3 2 1 0

SBS3 SBS2 SBS1 SBS0F84H

Symbol

SBS

Stack area specification

0

0

Memory bank 0

0

1

Memory bank 1

1

0

Setting prohibited

1

1

0 Be sure to set 0 for bit 2.

Mode selection specification

01Mk II mode

Mk I mode

Caution SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When using

instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the instructions.

13

µ

PD75P0116

5. DIFFERENCES BETWEEN µPD75P0116 AND µPD750104, 750106, AND 750108

The µPD75P0116 replaces the internal mask ROM in the µPD750104, 750106, and 750108 with a one-time PROM
and features expanded ROM capacity. The µPD75P0116’s Mk I mode supports the Mk I mode in the µPD750104, 750106,
and 750108 and the µPD75P0116’s Mk II mode supports the Mk II mode in the µPD750104, 750106, and 750108.

µ

Table 5-2 lists differences among the
differences between corresponding versions beforehand, especially when a PROM version is used for debugging or
prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production.

µ

Please refer to the

PD750108 User's Manual (U11330E) for details on CPU functions and on-chip hardware.

Table 5-1. Differences between

PD75P0116 and the µPD750104, 750106, and 750108. Be sure to check the

µ

PD75P0116 and µPD750104, 750106, and 750108

Item
Program counter 12-bit 13-bit 14-bit
Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM

Data memory (× 4 bits) 512
Mask options Pull-up resistor for Yes (On-chip/not on-chip can be specified.) No (On-chip not

port 4 and port 5 possible)
Wait time when Yes (29/fCC or none)

releasing STOP mode
by interrupt generation

Feedback resistor Yes (can select usable or unusable.) No (usable)
for subsystem clock

Pin connection Pins 6-9 (CU) P33-P30 P33/MD3-P30/MD0

Pins 23-26 (GB)
Pin 20 (CU) IC VPP
Pin 38 (GB)
Pins 34-37 (CU) P53-P50 P53/D7-P50/D4
Pins 8-11 (GB)
Pins 38-41 (CU) P43-P40 P43/D3-P40/D0
Pins 13-16 (GB)

Other Noise resistance and noise radiation may differ due to the different circuit complexities and

µ

PD750104

4096 6144 8192 16384

mask layouts.

Note

µ

PD750106

µ

PD750108

µ

No (fixed at 29/fCC)

PD75P0116

Note

Note 29/fCC : 256 µs at 2.0 MHz, 512 µs at 1.0 MHz

Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using

a mask ROM version instead of the PROM version for processes between prototype development and
full production, be sure to fully evaluate the CS of the mask ROM version (not ES).

14

6. MEMORY CONFIGURATION

76 0

MBE

RBE

0000H

0002H

0004H

0006H

0008H

000AH

000CH





MBE





MBE





MBE





MBE





MBE





MBE

Internal reset start address (higher 6 bits)



Internal reset start address (lower 8 bits)

RBE

INTBT/INT4 start address (higher 6 bits)



INTBT/INT4 start address (lower 8 bits)

RBE

INT0 start address (higher 6 bits)



INT0 start address (lower 8 bits)

RBE

INT1 start address (higher 6 bits)



INT1 start address (lower 8 bits)

RBE

INTCSI start address (higher 6 bits)



INTCSI start address (lower 8 bits)

RBE

INTT0 start address (higher 6 bits)



INTT0 start address (lower 8 bits)

RBE

INTT1 start address (higher 6 bits)
INTT1 start address (lower 8 bits)

Figure 6-1. Program Memory Map

CALLF

!faddr instruction

entry address

BRCB

!caddr instruction

branch address

Branch address for

the following instructions

µ

PD75P0116



• BR BCDE

• BR BCXA

• BR !addr

• CALL !addr

• BRA !addr1

• CALLA !addr1

Note

Note

0020H

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH













Reference table for GETI instruction

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address



Branch/call

address

by GETI

BR $addr instruction

relative branch address

(–15 to –1,

+2 to +16)

Note Can be used only at Mk II mode.

Remark For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to

branch to addresses with changes in the PC’s lower 8 bits only.

15

Figure 6-2. Data Memory Map

µ

PD75P0116

Data area

static RAM

(512 × 4)

General
register

area

Stack area

Note

000H

01FH
020H

0FFH
100H

1FFH

Data memory

(32 × 4)

256 × 4



(224 × 4)

256 × 4

Memory bank

0

1

Unimplemented

F80H

Peripheral hardware area

FFFH

128 × 4

Note For the stack area, one memory bank can be selected from memory bank 0 or 1.

15

16

µ

PD75P0116

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s
operand representations (for further description, refer to the RA75X Assembler Package User’s Manual - Language
(EEU-1363)). When there are several codes, select and use just one. Upper-case letters, and + and – symbols are key
words that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Instead of mem, fmem, pmem, bit, etc, a register flag symbol can be described as a label descriptor. (For further

µ

description, refer to the
restricted.

reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L
rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1 BC, DE, HL, XA’, BC’, DE’, HL’
rpa HL, HL+, HL–, DE, DL
rpa1 DE, DL
n4 4-bit immediate data or label
n8 8-bit immediate data or label
mem 8-bit immediate data or label
bit 2-bit immediate data or label
fmem FB0H-FBFH, FF0H-FFFH immediate data or label
pmem FC0H-FFFH immediate data or label
addr 0000H-3FFFH immediate data or label
addr1 0000H-3FFFH immediate data or label (in Mk II mode only)
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label
taddr 20H-7FH immediate data (however, bit0 = 0) or label
PORTn PORT0-PORT8
IEXXX IEBT, IECSI, IET0, IET1, IE0-IE2, IE4, IEW
RBn RB0-RB3
MBn MB0, MB1, MB15

PD750108 User's Manual (U11330E)) Labels that can be entered for fmem and pmem are

Representation Coding format

Note

Note When processing 8-bit data, only even addresses can be specified.

17

(2) Operation legend

A : A register; 4-bit accumulator
B : B register
C : C register
D : D register
E : E register
H : H register
L : L register
X : X register
XA : Register pair (XA); 8-bit accumulator
BC : Register pair (BC)
DE : Register pair (DE)
HL : Register pair (HL)
XA’ : Expansion register pair (XA’)
BC’ : Expansion register pair (BC’)
DE’ : Expansion register pair (DE’)
HL’ : Expansion register pair (HL’)
PC : Program counter
SP : Stack pointer
CY : Carry flag; bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn : Port n (n = 0 to 8)
IME : Interrupt master enable flag
IPS : Interrupt priority select register
IE××× : Interrupt enable flag
RBS : Register bank select register
MBS : Memory bank select register
PCC : Processor clock control register
. : Delimiter for address and bit
(××) : Contents of address ××

××H : Hexadecimal data

µ

PD75P0116

18

(3) Description of symbols used in addressing area

MB = MBE • MBS

*1

MB = 0

*2

MBE = 0 :

*3

MBE = 1 :

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

*4

MB = 15, pmem = FC0H-FFFH

*5

addr = 0000H-3FFFH

*6

addr, addr1 =*7(Current PC) –15 to (Current PC) –1

caddr =0000H-0FFFH (PC

*8

MBS = 0, 1, 15

MB = 0 (000H-07FH)
MB = 15 (F80H-FFFH)
MB = MBS
MBS = 0, 1, 15

(Current PC) +2 to (Current PC) +16

13, 12

= 00B) or
1000H-1FFFH (PC13, 12 = 01B) or
2000H-2FFFH (PC13, 12 = 10B) or
3000H-3FFFH (PC13, 12 = 11B)

µ

PD75P0116

Data memory

addressing

Program memory

addressing

faddr = 0000H-07FFH

*9

taddr = 0020H-007FH

*10

addr1 = 0000H-3FFFH (Mk II mode only)

*11

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

19

µ

PD75P0116

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as
shown below.

• No skip .......................................................................... S = 0

• Skipped instruction is 1-byte or 2-byte instruction......... S = 1

Note

• Skipped instruction is 3-byte instruction

Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1

Caution The GETI instruction is skipped for one machine cycle.

................. S = 2

One machine cycle equals one cycle (= t

CY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.

20

µ

PD75P0116

Group Mnemonic Operand

Transfer MOV A, # n4 1 1 A ← n4 String-effect A

reg1, # n4 2 2 reg1 ← n4
XA, # n8 2 2 XA ← n8 String-effect A
HL, # n8 2 2 HL ← n8 String-effect B
rp2, # n8 2 2 rp2 ← n8
A, @HL 1 1 A ← (HL) *1
A, @HL+ 1 2 + S A ← (HL), then L ← L + 1 *1 L = 0
A, @HL– 1 2 + S A ← (HL), then L ← L – 1 *1 L = FH
A, @rpa1 1 1 A ← (rpa1) *2
XA, @HL 2 2 XA ← (HL) *1
@HL, A 1 1 (HL) ← A*1
@HL, XA 2 2 (HL) ← XA *1
A, mem 2 2 A ← (mem) *3
XA, mem 2 2 XA ← (mem) *3
mem, A 2 2 (mem) ← A*3
mem, XA 2 2 (mem) ← XA *3
A, reg 2 2 A ← reg
XA, rp’ 2 2 XA ← rp’
reg1, A 2 2 reg1 ← A
rp’1, XA 2 2 rp’1 ← XA

XCH A, @HL 1 1 A ↔ (HL) *1

A, @HL+ 1 2 + S A ↔ (HL), then L ← L + 1 *1 L = 0
A, @HL– 1 2 + S A ↔ (HL), then L ← L – 1 *1 L = FH
A, @rpa1 1 1 A ↔ (rpa1) *2
XA, @HL 2 2 XA ↔ (HL) *1
A, mem 2 2 A ↔ (mem) *3
XA, mem 2 2 XA ↔ (mem) *3
A, reg1 1 1 A ↔ reg1

XA, rp’ 2 2 XA ↔ rp’
Table MOVT XA, @PCDE 1 3 XA ← (PC13-8 + DE)ROM
reference XA, @PCXA 1 3 XA ← (PC13-8 + XA)ROM

XA, @BCDE 1 3 XA ← (BCDE)ROM

XA, @BCXA 1 3 XA ← (BCXA)ROM

No. of Machine
bytes cycle area

Operation

Note

Note

Addressing

*6
*6

Skip

condition

Note As for the B register, only the lower 2 bits are valid.

21

µ

PD75P0116

Group Mnemonic Operand

Bit transfer MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4

CY, pmem.@L 2 2 CY ← (pmem7-2 + L3-2.bit(L1-0)) *5
CY, @H + mem.bit 2 2 CY ← (H + mem3-0.bit) *1
fmem.bit, CY 2 2 (fmem.bit) ← CY *4
pmem.@L, CY 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← CY *5
@H + mem.bit, CY 2 2 (H + mem3-0.bit) ← CY *1

Operation ADDS A, #n4 1 1 + S A ← A + n4 carry

XA, #n8 2 2 + S XA ← XA + n8 carry
A, @HL 1 1 + S A ← A + (HL) *1 carry
XA, rp’ 2 2 + S XA ← XA + rp’ carry
rp’1, XA 2 2 + S rp’1 ← rp’1 + XA carry

ADDC A, @HL 1 1 A, CY ← A + (HL) + CY *1

XA, rp’ 2 2 XA, CY ← XA + rp’ + CY
rp’1, XA 2 2 rp’1, CY ← rp’1 + XA + CY

SUBS A, @HL 1 1 + S A ← A – (HL) *1 borrow

XA, rp’ 2 2 + S XA ← XA – rp’ borrow
rp’1, XA 2 2 + S rp’1 ← rp’1 – XA borrow

SUBC A, @HL 1 1 A, CY ← A – (HL) – CY *1

XA, rp’ 2 2 XA, CY ← XA – rp’ – CY
rp’1, XA 2 2 rp’1, CY ← rp’1 – XA – CY

AND A, #n4 2 2 A ← A ^ n4

A, @HL 1 1 A ← A ^ (HL) *1
XA, rp’ 2 2 XA ← XA ^ rp’
rp’1, XA 2 2 rp’1 ← rp’1 ^ XA

OR A, #n4 2 2 A ← A v n4

A, @HL 1 1 A ← A v (HL) *1
XA, rp’ 2 2 XA ← XA v rp’
rp’1, XA 2 2 rp’1 ← rp’1 v XA

XOR A, #n4 2 2 A ← A v n4

A, @HL 1 1 A ← A v (HL) *1
XA, rp’ 2 2 XA ← XA v rp’
rp’1, XA 2 2 rp’1 ← rp’1 v XA

No. of Machine
bytes cycle area

Operation

Addressing

Skip

condition

22

µ

PD75P0116

Group Mnemonic Operand

Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An
manipulate NOT A 2 2 A ← A
Increment/ INCS reg 1 1 + S reg ← reg + 1 reg = 0
decrement rp1 1 1 + S rp1 ← rp1 + 1 rp1 = 00H

@HL 2 2 + S (HL) ← (HL) + 1 *1 (HL) = 0

mem 2 2 + S (mem) ← (mem) + 1 *3 (mem) = 0

DECS reg 1 1 + S reg ← reg – 1 reg = FH

rp’ 2 2 + S rp’ ← rp’ – 1 rp’ = FFH
Compare SKE reg, #n4 2 2 + S Skip if reg = n4 reg = n4

@HL, #n4 2 2 + S Skip if (HL) = n4 *1 (HL) = n4

A, @HL 1 1 + S Skip if A = (HL) *1 A = (HL)

XA, @HL 2 2 + S Skip if XA = (HL) *1 XA = (HL)

A, reg 2 2 + S Skip if A = reg A = reg

XA, rp’ 2 2 +S Skip if XA = rp’ XA = rp’
Carry flag SET1 CY 1 1 CY ← 1
manipulate CLR1 CY 1 1 CY ← 0

SKT CY 1 1 + S Skip if CY = 1 CY = 1
NOT1 CY 1 1 CY ← CY

No. of Machine
bytes cycle area

Operation

Addressing

Skip

condition

23

µ

PD75P0116

Group Mnemonic Operand

No. of Machine

Operation

Addressing

bytes cycle area

Skip

condition
Memory bit SET1 mem.bit 2 2 (mem.bit) ← 1*3
manipulate fmem.bit 2 2 (fmem.bit) 1 *4

pmem.@L 2 2 (pmem
@H + mem.bit 2 2 (H + mem

CLR1 mem.bit 2 2 (mem.bit) 0 *3

fmem.bit 2 2 (fmem.bit) 0 *4
pmem.@L 2 2 (pmem

←

7-2 + L3-2.bit(L1-0)) 1 *5

3-0.bit) ← 1*1

←

←

←

7-2 + L3-2.bit(L1-0)) 0 *5

←

@H + mem.bit 2 2 (H + mem3-0.bit) ← 0*1

SKT mem.bit 2 2 + S Skip if(mem.bit) = 1 *3 (mem.bit) = 1

fmem.bit 2 2 + S Skip if(fmem.bit) = 1 *4 (fmem.bit) = 1
pmem.@L 2 2 + S Skip if(pmem
@H + mem.bit 2 2 + S Skip if(H + mem

7-2 + L3-2.bit(L1-0)) = 1 *5 (pmem.@L) = 1

3-0.bit) = 1 *1

(@H + mem.bit) = 1

SKF mem.bit 2 2 + S Skip if(mem.bit) = 0 *3 (mem.bit) = 0

fmem.bit 2 2 + S Skip if(fmem.bit) = 0 *4 (fmem.bit) = 0
pmem.@L 2 2 + S Skip if(pmem
@H + mem.bit 2 2 + S Skip if(H + mem

7-2 + L3-2.bit(L1-0)) = 0 *5 (pmem.@L) = 0

3-0.bit) = 0 *1

(@H + mem.bit) = 0

SKTCLR fmem.bit 2 2 + S Skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1

pmem.@L 2 2 + S
@H + mem.bit 2 2 + S Skip if(H + mem

Skip if(pmem7-2 + L3-2.bit (L1-0)) = 1 and clear

3-0.bit) = 1 and clear *1

*5 (pmem.@L) = 1

(@H + mem.bit) = 1

AND1 CY, fmem.bit 2 2 CY ← CY ^ (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY ^ (pmem7-2 + L3-2.bit(L1-0)) *5
CY, @H + mem.bit 2 2 CY ← CY

(H + mem3-0.bit) *1

^

OR1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY v (pmem
CY, @H + mem.bit 2 2 CY ← CY v (H + mem

XOR1 CY, fmem.bit 2 2 CY ← CY v

CY, pmem.@L 2 2 CY ← CY v

7-2 + L3-2.bit(L1-0)) *5

3-0.bit) *1

(fmem.bit) *4
(pmem7-2 + L3-2.bit(L1-0)) *5

CY, @H + mem.bit 2 2 CY ← CY v (H + mem3-0.bit) *1

24

µ

PD75P0116

Group Mnemonic Operand

Branch BR

Note 1

addr — — PC13-0 ← addr *6

addr1 — — PC13-0 ← addr1 *11

!addr 3 3 PC13-0 ← addr *6
$addr 1 2 PC13-0 ← addr *7
$addr1 1 2 PC13-0 ← addr1
PCDE 2 3 PC13-0 ← PC13-8 + DE
PCXA 2 3 PC13-0 ← PC13-8 + XA
BCDE 2 3 PC13-0 ← BCDE
BCXA 2 3 PC13-0 ← BCXA

Note 1

BRA

!addr1 3 3 PC13-0 ← addr1 *11

BRCB !caddr 2 2 PC13-0 ← PC13, 12 + caddr11-0 *8

No. of Machine

Operation

Addressing

bytes cycle area

Assembler selects the most
appropriate instruction among
the following:

• BR !addr

• BRCB !caddr

• BR $addr

Assembler selects the most
appropriate instruction among
the following:

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

Note 2

Note 2

*6
*6

Skip

condition

Notes 1. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

2. As for the B register, only the lower 2 bits are valid.

25

µ

PD75P0116

Group Mnemonic Operand

No. of Machine

Operation

bytes cycle area

Subroutine CALLA

Note

!addr1 3 3 (SP – 5) ← 0, 0, PC13,12 *11

stack control (SP – 6)(SP – 3)(SP – 4) ← PC11-0

(SP – 2)

←

×, ×, MBE, RBE

PC13–0

←

CALL

Note

!addr 3 3 (SP

–

(SP

– 3) ←

PC13–0

addr1, SP

4)(SP

←

addr, SP

←

SP – 6

–

1)(SP

– 2) ←

PC11-0 *6

(MBE, RBE, PC13, 12)

←

SP – 4

4 (SP – 5) ← 0, 0, PC13,12

(SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP

– 2) ←

×, ×, MBE, RBE

PC13-0

←

CALLF

Note

!faddr 2 2 (SP

(SP
PC13-0

addr, SP

–

4)(SP

– 3) ←

←

000 + faddr, SP

← SP –

6

–

1)(SP

– 2) ←

PC11-0 *9

(MBE, RBE, PC13, 12)

←

SP – 4

3 (SP – 5) ← 0, 0, PC13,12

(SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP – 2)

←

×, ×, MBE, RBE

PC13-0

←

000 + faddr,SP ← SP – 6

Note

RET

1 3 (MBE, RBE, PC13, 12) ← (SP + 1)

PC11-0 → (SP)(SP + 3)(SP + 2)
SP ← SP + 4
×, ×, MBE, RBE ← (SP + 4)
0, 0, PC13-12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 6

Note

RETS

1 3 + S (MBE, RBE, PC13, 12) ← (SP + 1) Unconditional

PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 4
then skip unconditionally
×, ×, MBE, RBE ← (SP + 4)
0, 0, PC13-12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 6
then skip unconditionally

Note

RETI

1 3 MBE, RBE, PC13, 12 ← (SP + 1)

PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6
0, 0, PC13, 12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6

Addressing

Skip

condition

Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

26

µ

PD75P0116

Group Mnemonic Operand

No. of Machine

Operation

bytes cycle area
Subroutine PUSH rp 1 1 (SP – 1)(SP – 2) ← rp, SP ← SP – 2
stack control BS 2 2

(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2

POP rp 1 1 rp ← (SP + 1)(SP), SP ← SP + 2

BS 2 2

MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
Interrupt EI 2 2 IME(IPS.3) ← 1
control IE××× 22IE××× ← 1

DI 2 2 IME(IPS.3) ← 0

IE××× 22IE××× ← 0

I/O IN

Note 1

A, PORTn 2 2 A ← PORTn (n = 0 - 8)
XA, PORTn 2 2 XA ← PORTn+1, PORTn (n = 4, 6)

Note 1

OUT

PORTn, A 2 2 PORTn ← A (n = 2 - 8)
PORTn, XA 2 2 PORTn+1, PORTn ← XA (n = 4, 6)

CPU control HALT 2 2 Set HALT Mode(PCC.2 ← 1)

STOP 2 2 Set STOP Mode(PCC.3 ← 1)
NOP 1 1 No Operation

Special SEL RBn 2 2 RBS ← n (n = 0 - 3)

MBn 2 2 MBS ← n (n = 0, 1, 15)

Note 2, 3

GETI

taddr 1 3 • When using TBR instruction *10

PC13-0 ← (taddr)5-0 + (taddr + 1)

- - - - - - - - - - - - - - - - - - - - - - - - -

• When using TCALL instruction

(SP – 4)(SP – 1)(SP – 2) ← PC11-0

(SP – 3) ← MBE, RBE, PC13, 12

PC13-0 ← (taddr)5-0 + (taddr + 1)

SP ← SP – 4

- - - - - - - - - - - - - - - - - - - - - - - - -

• When using instruction other than Determined by

TBR or TCALL referenced

Execute (taddr)(taddr + 1) instructions instruction

1 3 • When using TBR instruction *10

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PC13-0 ← (taddr)5-0 + (taddr + 1)

4 • When using TCALL instruction

(SP – 5) ←
(SP – 6)(SP – 3)(SP – 4) ←

(SP

– 2) ←

0, 0, PC13, 12

PC11-0

×, ×, MBE, RBE

PC13-0 ← (taddr)5-0 + (taddr + 1)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

SP ← SP – 6

3 • When using instruction other than Determined by

TBR or TCALL referenced

Execute (taddr)(taddr + 1) instructions instruction

Addressing

Skip

condition

- - - - - - - - - - -

- - - - - - - - - - -

Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.

2. TBR and TCALL are assembler directives for the GETI instruction’s table definitions.

3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

27

µ

PD75P0116

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory in the µPD75P0116 is a 16384 × 8-bit electronic write-enabled one-time PROM. The pins listed
in the table below are used for this PROM’s write/verify operations. Clock input from the CL1 pins is used instead of
address input as a method for updating addresses.

Pin name Function

VPP Pin (usually VDD) where programming voltage is applied during

CL1, CL2 Clock input to the CL1 pin for address updating during program

MD0/P30-MD3/P33 Operation mode selection pin for program memory write/verify
D0/P40-D3/P43 (lower 4) 8-bit data I/O pin for program memory write/verify

D4/P50-D7/P53 (higher 4)
VDD Pin where power supply voltage is applied. Power voltage

Caution Pins not used for program memory write/verify should be processed as follows.

• All unused pins except XT2 ...... Connect to Vss via a pull-down resistor

• XT2 pin ........................................Leave open

program memory write/verify

memory write/verify. Leave the CL2 pin open.

range for normal operation is 1.8 to 5.5 V. Apply 6.0 V for
program memory write/verify.

8.1 Operation Modes for Program Memory Write/Verify

µ

When +6 V is applied to the

PD75P0116’s VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes
are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown
below.

Operation mode specification Operation mode
VPP VDD MD0 MD1 MD2 MD3
+12.5 V +6 V H L H L Zero-clear program memory address

L H H H Write mode
L L H H Verify mode

H × H H Program inhibit mode

Remark ×: L or H

28

µ

V

PP

V

DD

VDD+ 1

V

DD

V

PP

V

DD

CL1

D0/P40-D3/P43
D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

X repetitions

Write

Verify

Additional

write

Address increment

Data input

Data output

Data input

PD75P0116

8.2 Steps in Program Memory Write Operation

High-speed program memory write can be executed via the following steps.

SS

(1) Pull down unused pins to V

via resistors. Set the CL1 pin to low.
(2) Apply +5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Zero-clear mode for program memory addresses.
(5) Apply +6 V to V

DD and +12.5 V power to VPP.

(6) Write data using 1-ms write mode.
(7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7).
(8) X [= number of write operations from steps (6) and (7)] × 1 ms additional write
(9) 4 pulse inputs to the CL1 pin updates (increments +1) the program memory address.
(10) Repeat steps (6) to (9) until the last address is completed.
(11) Zero-clear mode for program memory addresses.
(12) Apply +5 V to the V

DD and VPP pins.

(13) Power supply OFF

The following diagram illustrates steps (2) to (9).

29

µ

PD75P0116

8.3 Steps in Program Memory Read Operation

The µPD75P0116 can read out the program memory contents via the following steps.

SS

(1) Pull down unused pins to V

via resistors. Set the CL1 pin to low.
(2) Apply +5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Zero-clear mode for program memory addresses.
(5) Apply +6 V power to V

DD and +12.5 V to VPP.

(6) Verify mode. When a clock pulse is input to the CL1 pin, data is output sequentially to one address at a time based

on a cycle of four pulse inputs.
(7) Zero-clear mode for program memory addresses.
(8) Apply +5 V power to the V

DD and VPP pins.

(9) Power supply OFF

The following diagram illustrates steps (2) to (7).

V

PP

V

PP

V

DD

VDD+ 1

V

DD

V

DD

CL1

D0/P40-D3/P43
D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

Data output Data output

“L”

30

MD3/P33

µ

PD75P0116

8.4 One-Time PROM Screening

Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
the screening process, that is, after the required data is written to the PROM and the PROM is stored under the high­temperature conditions shown below, the PROM should be verified.

Storage temperature Storage time

125 ˚C 24 hours

31

µ

PD75P0116

9. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25 ˚C)

Parameter Symbol Conditions Ratings Unit
Supply voltage V DD –0.3 to + 7.0 V
PROM supply voltage VPP –0.3 to + 13.5 V
Input voltage VI1 Other than ports 4, 5 –0.3 to VDD + 0.3 V

VI2 Ports 4, 5 (N-ch open drain) –0.3 to + 14 V
Output voltage VO –0.3 to VDD + 0.3 V
High-level output current IOH Per pin –10 mA

Total of all pins –30 mA

Low-level output current IOL Per pin 30 mA

Total of all pins 220 mA

Operating ambient TA –40 to + 85 ˚C
temperature

Storage temperature Tstg –65 to + 150 ˚C

Caution If the absolute maximum rating of even one of the parameters is exceeded even momentarily,

the quality of the product may be degraded. The absolute maximum ratings are therefore values
which, when exceeded, can cause the product to be damaged. Be sure that these values are
never exceeded when using the product.

Capacitance (T

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input capacitance CIN f = 1 MHz 15 pF
Output capacitance COUT Pins other than tested pins: 0 V 15 pF
I/O capacitance CIO 15 pF

A = 25 ˚C, VDD = 0 V)

32

µ

PD75P0116

Main System Clock Oscillation Circuit Characteristics (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)

Resonator

RC oscillation Oscillation frequency 0.4 2.0 MHz

Recommended

constants

CL1 CL2

Parameter Conditions MIN. TYP. MAX. Unit

Note

(fCC)

Note The oscillation frequency shown above indicates characteristics of the oscillation circuit only. For the

instruction execution time and oscillation frequency characteristics, refer to AC Characteristics.

Caution When using the main system clock oscillation circuit, wire the portion enclosed in the dotted

line in the above figure as follows to prevent adverse influences due to wiring capacitance:

· Keep the wiring length as short as possible.

· Do not cross the wiring with other signal lines.

· Do not route the wiring in the vicinity of a line through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillation circuit at the same potential

DD.

as V
Do not ground to a power supply pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

33

Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

µ

PD75P0116

Resonator

Crystal Oscillation frequency 32 32.768 35 kHz
resonator (fXT)

External XT1 input frequency 32 100 kHz
clock (fXT)

Recommended

constants

XT1 XT2

R

C3 C4

XT1 XT2

Parameter Conditions MIN. TYP. MAX. Unit

Note 1

Oscillation VDD = 4.5 to 5.5 V 1.0 2 s
stabilization time

Note 1

XT1 input high-, 5 15
low-level widths
(tXTH, tXTL)

Note 2

10 s

µ

s

Notes 1. The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the

instruction execution time, refer to AC Characteristics.

2. The oscillation stabilization time is the time required for oscillation to be stabilized after V

DD has been

applied.

Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line

in the above figure as follows to prevent adverse influences due to wiring capacitance:

· Keep the wiring length as short as possible.

· Do not cross the wiring with other signal lines.

· Do not route the wiring in the vicinity of a line through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillation circuit at the same potential

DD.

as V
Do not ground to a power supply pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

The subsystem clock oscillation circuit has a low amplification factor to reduce current
dissipation and is more susceptible to noise than the main system clock oscillation circuit.
Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit.

34

µ

PD75P0116

DC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Low-level IOL Per pin 15 mA
output current Total of all pins 150 mA
High-level input VIH1 Ports 2, 3, 8 2.7 ≤ VDD ≤ 5.5 V 0.7 VDD VDD V
voltage 1.8 ≤ VDD ≤ 2.7 V 0.9 VDD VDD V

VIH2 Ports 0, 1, 6, 7, RESET 2.7 ≤ VDD ≤ 5.5 V 0.8 VDD VDD V

1.8 ≤ VDD ≤ 2.7 V 0.9 VDD VDD V

VIH3 Ports 4, 5 (N-ch open drain) 2.7 ≤ VDD ≤ 5.5 V 0.7 VDD 13 V

1.8 ≤ VDD ≤ 2.7 V 0.9 VDD 13 V

VIH4 XT1 VDD–0.1 VDD V
Low-level input VIL1 Ports 2-5, 8 2.7 ≤ VDD ≤ 5.5 V 0 0.3 VDD V
voltage 1.8 ≤ VDD ≤ 2.7 V 0 0.1 VDD V

VIL2 Ports 0, 1, 6, 7, RESET 2.7 ≤ VDD ≤ 5.5 V 0 0.2 VDD V

1.8 ≤ VDD ≤ 2.7 V 0 0.1 VDD V

VIL3 XT1 0 0.1 V
High-level output VOH SCK, SO, ports 2, 3, 6-8 VDD–0.5 V

voltage IOH = –1.0 mA
Low-level output VOL1 SCK, SO, IOL = 15 mA, VDD = 5.0 V ± 10 % 0.2 2.0 V
voltage ports 2-8 IOL = 1.6 mA 0.4 V

VOL2 SB0, SB1 N-ch open drain 0.2 VDD V

Pull-up resistor ≥ 1 kΩ
High-level input ILIH1 VIN = VDD Pins other than XT1 3
leakage current ILIH2 XT1 20

ILIH3 VIN = 13 V Ports 4, 5 (N-ch open drain) 20
Low-level input ILIL1 VIN = 0 V Pins other than ports 4, 5, XT1 –3
leakage current ILIL2 XT1 –20

ILIL3 Ports 4, 5 (N-ch open drain) When –3

High-level output ILOH1 VOUT = VDD SCK, SO/SB0, SB1, Ports 2, 3, 6-8 3
leakage current ILOH2
Low-level output ILOL VOUT = 0 V –3
leakage current
Internal pull-up RL VIN = 0 V Ports 0-3, 6-8 (except P00 pin) 50 100 200 kΩ
resistor

VOUT = 13 V

input instruction is not executed
Ports 4, 5 (N-ch
open drain)
When input VDD = 5.0 V –10 –27
instruction is
executed

Ports 4, 5 (N-ch open drain) 20

VDD = 3.0 V –3 –8

–30

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

35

DC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Supply current

Note 1

IDD1 VDD = 5.0 V ± 10 %

IDD2 VDD = 5.0 V ± 10 % 370 920

IDD3 VDD = 3.0 V ± 10 % 55.0 200

IDD4

IDD5 VDD = 5.0 V ± 10 % 0.05 5.0

Note 2

1.0 MHz
RC oscillation
R = 22 kΩ,
C = 22 pF

32.768

Note 5

kHz
crystal
oscillation

Note 8

XT1 = 0V
STOP
mode

VDD = 3.0 V ± 10 %

Note 3

Note 4

0.9 1.8 mA

250 500

HALT
mode

VDD = 3.0 V ± 10 % 170 340

Low­voltage
mode

Low
current
dissipation
mode

HALT
mode

VDD = 2.0 V ± 10 % 22.0 70.0

Note 6

VDD = 3.0 V, TA = 25 ˚C 55.0 90.0
VDD = 3.0 V ± 10 % 50.0 150
VDD = 3.0 V, TA = 25 ˚C 50.0 85.0

Note 7

Low­voltage
mode

Low current
consumption
mode

VDD = 3.0 V ± 10 %
VDD = 2.0 V ± 10 %

Note 6

VDD = 3.0 V, TA = 25 ˚C
VDD = 3.0 V ± 10 %

Note 7

VDD = 3.0 V, TA = 25 ˚C

5.0 30.0

2.5 10.0

5.0 10.0

4.0 15.0

4.0 7.0

VDD = 3.0 V ± 10 % 0.02 2.5

TA = 25 ˚C 0.02 0.2

µ

PD75P0116

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

Notes 1. The current flowing through the internal pull-up resistor is not included.

2. Including the case when the subsystem clock oscillates.

3. When the device operates in high-speed mode with the processor clock control register (PCC) set to

0011.

4. When the device operates in low-speed mode with PCC set to 0000.

5. When the device operates on the subsystem clock, with the system clock control register (SCC) set to

1001 and oscillation of the main system clock stopped.

6. When the suboscillation circuit control register (SOS) is set to 0000.

7. When SOS is set to 0010.

8. When SOS is set to 00×1, and the suboscillation circuit feedback resistor is not used (×: don’t care).

36

µ

PD75P0116

AC Characteristics (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

CPU clock cycle tCY Operates with main system clock 2.0 128

Note 1

time
(minimum instruction
execution time = 1
machine cycle)

TI0 input frequency fTI VDD = 2.7 to 5.5 V 0 1.0 MHz

TI0 high-, low-level t TIH, tTIL VDD = 2.7 to 5.5 V 0.48
widths 1.8
Interrupt input high-, tINTH, INT0 IM02 = 0 Note 2
low-level widths tINTL IM02 = 1 10

RESET low-level width
RC oscillation fCC R = 22 kΩ,VDD = 2.7 to 5.5 V 0.9 1.0 1.3 MHz
frequency C = 22 pF VDD = 1.8 to 5.5 V 0.55 1.0 1.3 MHz

tRSL 10

Operates with subsystem clock 114 122 125

0 275 kHz

INT1, 2, 4 10
KR0-KR7 10

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

Notes 1. The cycle time of the CPU clock (φ) (minimum instruction execution time) when the device operates with

the main system clock is determined by the time constant of the connected resistor (R) and capacitor
(C), and the value of the processor clock control register (PCC). When the device operates with the

φ

subsystem clock, the cycle time of the CPU clock (

) is determined by the oscillation frequency of the
connected oscillator (and external clock), and the values of the system clock control register (SCC) and
processor clock control register (PCC).
The figure on the below shows the supply voltage V

DD vs. cycle time tCY characteristics when the device

operates with the main system clock.

CY or 128/fCC depending on the setting of the interrupt mode register (IM0).

2. 2t

t

CY

vs V

DD

(with main system clock)

128

6
5

Operation guaranteed range

µ

( s)

CY

4

3

2

Cycle time t

1

0.5
0

1 2 3 4 5.5561.8

Supply voltage V

DD

[V]

37

Serial Transfer Operation

µ

PD75P0116

2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY1 VDD = 2.7 to 5.5 V 1300 ns

SCK high-, low-level widths tKL1,VDD = 2.7 to 5.5 V

tKH1

Note 1

SI

setup time tSIK1 VDD = 2.7 to 5.5 V 150 ns

(vs. SCK ↑) 500 ns

Note 1

SI

hold time tKSI1 VDD = 2.7 to 5.5 V 400 ns
(vs. SCK ↑) 600 ns
SCK ↓ → SO
delay time CL = 100 pF 0 1000 ns

Note 1

output tKSO1 RL = 1 kΩ

Note 2

VDD = 2.7 to 5.5 V 0 2 50 ns

A = –40 to +85 °C, VDD = 1.8 to 5.5 V)

3800 ns

tKCY1/2–50

tKCY1/2–150

Notes 1. Read as SB0 or SB1 when using the 2-wire serial I/O mode.

2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.

2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (T

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY2 VDD = 2.7 to 5.5 V 800 ns

SCK high-, low-level widths tKL2,VDD = 2.7 to 5.5 V 400 ns

tKH2 1600 ns

Note 1

SI

setup time tSIK2 VDD = 2.7 to 5.5 V 100 ns
(vs. SCK ↑) 150 ns

Note 1

SI

hold time tKSI2 VDD = 2.7 to 5.5 V 400 ns
(vs. SCK ↑) 600 ns
SCK ↓ → SO
delay time CL = 100 pF 0 1000 ns

Note 1

output tKSO2 RL = 1 kΩ

Note 2

VDD = 2.7 to 5.5 V 0 3 00 ns

A = –40 to +85 °C, VDD = 1.8 to 5.5 V)

3200 ns

ns
ns

Notes 1. Read as SB0 or SB1 when using the 2-wire serial I/O mode.

2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.

38

µ

PD75P0116

SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85 °C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY3 VDD = 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-, low-level widths tKL3 VDD = 2.7 to 5.5 V

tKH3
SB0, 1 setup time tSIK3 VDD = 2.7 to 5.5 V 150 ns
(vs. SCK ↑) 500 ns
SB0, 1 hold time (vs. SCK ↑)tKSI3 tKCY3/2 ns
SCK ↓ → SB0, 1 output tKSO3 RL = 1 kΩ
delay time CL = 100 pF 0 1000 ns
SCK ↑ → SB0, 1 ↓ tKSB tKCY3 ns
SB0, 1 ↓ → SCK ↓ tSBK tKCY3 ns
SB0, 1 low-level width tSBL tKCY3 ns
SB0, 1 high-level width tSBH tKCY3 ns

Note

VDD = 2.7 to 5.5 V 0 2 50 ns

tKCY3/2–50

tKCY3/2–150

ns
ns

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.

SBI mode (SCK ··· external clock input (slave)): (T

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY4 VDD = 2.7 to 5.5 V 800 ns

SCK high-, low-level widths tKL4 VDD = 2.7 to 5.5 V 400 ns

tKH4 1600 ns
SB0, 1 setup time tSIK4 VDD = 2.7 to 5.5 V 100 ns
(vs. SCK ↑) 150 ns
SB0, 1 hold time (vs. SCK ↑)tKSI4 tKCY4/2 ns
SCK ↓ → SB0, 1 output tKSO4 RL = 1 kΩ
delay time CL = 100 pF 0 1000 ns
SCK ↑ → SB0, 1 ↓ tKSB tKCY4 ns
SB0, 1 ↓ → SCK ↓ tSBK tKCY4 ns
SB0, 1 low-level width tSBL tKCY4 ns
SB0, 1 high-level width tSBH tKCY4 ns

A = –40 to +85 °C, VDD = 1.8 to 5.5 V)

3200 ns

Note

VDD = 2.7 to 5.5 V 0 3 00 ns

Note RL and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.

39

AC Timing Test Points (except XT1 input)

µ

PD75P0116

Clock timing

TI0 timing

XT1 input

VIH (MIN.)
VIL (MAX.)

VOH (MIN.)
VOL (MAX.)

VIH (MIN.)
VIL (MAX.)

VOH (MIN.)
VOL (MAX.)

1/f

XT

t

XTL

t

XTH

VDD – 0.1 V

0.1 V

1/f

TI

TI0

t

TIL

t

TIH

40

Serial Transfer Timing

3-wire serial I/O mode

SCK

t

KL1, 2

t

SIK1, 2

t

KCY1, 2

t

KSI1, 2

t

KH1, 2

µ

PD75P0116

SI

SO

2-wire serial I/O mode

SCK

SB0, 1

t

KSO1, 2

t

KSO1, 2

Input data

t

KL1, 2

t

SIK1, 2

Output data

t

KCY1, 2

t

KH1, 2

t

KSI1, 2

41

Serial Transfer Timing

Bus release signal transfer

SCK

t

KSB

SB0, 1

Command signal transfer

µ

PD75P0116

t

KCY3, 4

t

t

KL3, 4

t

t

t

SBL

SBH

SBK

t

KCY3, 4

KH3, 4

t

KSO3, 4

t

SIK3, 4

t

KSI3, 4

SCK

SB0, 1

Interrupt input timing

INT0, 1, 2, 4
KR0-7

RESET input timing

t

KSB

t

KL3, 4

t

SBK

tINTL tINTH

t

RSL

t

KH3, 4

t

KSO3, 4

t

SIK3, 4

t

KSI3, 4

42

RESET

µ

PD75P0116

Data Retention Characteristics of Data Memory in STOP Mode and at Low Supply Voltage
(TA = –40 to +85 ˚C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Release signal setup time tSREL 0
Oscillation stabilization tWAIT Released by RESET 56/fCC
wait time

Note 1

Released by interrupt request 512/fCC

µ

s

µ

s

µ

s

Note The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable

operation when oscillation is started.

Data retention timing (when STOP mode released by RESET)

Internal reset operation

HALT mode

STOP mode

Data retention mode

Operation mode

V

DD

STOP instruction execution

RESET

t

SREL

t

WAIT

Data retention timing (standby release signal: when STOP mode released by interrupt signal)

HALT mode

DD

V

STOP instruction execution

Standby release signal

(interrupt request)

STOP mode

Data retention mode

t

SREL

Operation mode

t

WAIT

43

µ

PD75P0116

DC Programming Characteristics (TA = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input voltage, high VIH1 Other than CL1 pin 0.7 VDD VDD V

VIH2 CL1

Input voltage, low VIL1 Other than CL1 pin 0 0.3 VDD V

VIL2 CL1 0 0.4 V
Input leakage current ILI VIN = VIL or VIH 10
Output voltage, high VOH IOH = – 1 mA
Output voltage, low VOL IOL = 1.6 mA 0.4 V
VDD supply current IDD 30 mA
VPP supply current IPP MD0 = VIL, MD1 = VIH 30 mA

VDD – 0.5

VDD – 1.0

VDD V

Cautions 1. Keep VPP to within +13.5 V, including overshoot.

2. Apply VDD before VPP and turn it off after VPP.

µ

A

V

AC Programming Characteristics (T

Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit

Address setup time
(vs. MD0 ↓)

MD1 setup time (vs. MD0 ↓)tM1S tOES 2
Data setup time (vs. MD0 ↓)tDS tDS 2
Address hold time

(vs. MD0 ↑)
Data hold time (vs. MD0 ↑)tDH tDH 2
MD0 ↑ → data output float tDF tDF 0 130 ns

delay time
VPP setup time (vs. MD3 ↑)tVPS tVPS 2
VDD setup time (vs. MD3 ↑)tVDS tVCS 2
Initial program pulse width tPW tPW 0.95 1.0 1.05 ms
Additional program pulse width
MD0 setup time (vs. MD1 ↑)tM0S tCES 2
MD0 ↓ → data output delay time
MD1 hold time (vs. MD0 ↑)tM1H tOEH tM1H + tM1R ≥ 50 µs2
MD1 recovery time (vs. MD0 ↓)
Program counter reset time tPCR —10
CL1 input high-, low-level width
CL1 input frequency fCC — 4.19 MHz
Initial mode set time tI —2
MD3 setup time (vs. MD1 ↑)tM3S —2
MD3 hold time (vs. MD1 ↓)tM3H —2
MD3 setup time (vs. MD0 ↓)tM3SR — When program memory is read 2
Address

delay time
Address

hold time
MD3 hold time (vs. MD0 ↑)tM3HR — When program memory is read 2
MD3 ↓ → data output float tDFR — When program memory is read 2

delay time

Note 2

Note 2

Note 2

Note 2

→ data output tDAD tACC When program memory is read 2

→ data output tHAD tOH When program memory is read 0 130 ns

tAS tAS 2

tAH tAH 2

tOPW tOPW 0.95 21.0 ms

tDV tDV MD0 = MD1 = VIL 1

tM1R tOR 2

tXH, tXL — 0.125

A = 25 ± 5 °C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

Notes 1. Symbol of corresponding µPD27C256A

2. The internal address signal is incremented by one at the rising edge of the fourth CL1 input and is not

connected to a pin.

44

Program Memory Write Timing

t

VPS

V

PP

V

VDD+1

DD

V

CL1

MD0/P30

MD1/P31

MD2/P32

PP

DD

t

VDS

DD

t

I

t

PCR

t

M3S

V

V

D0/P40-D3/P43
D4/P50-D7/P53

Data input

t

DS

t

PW

t

M1S

t

t

DH

M1H

t

M1R

Data output



t

DV

t

DF

t

M0S

Data input Data input

t

DS

t

OPW

µ

PD75P0116

t

XH

t

XL



t

DH

t

AH

t

AS

t

M3H

MD3/P33

Program Memory Read Timing

V

PP

V

VDD+1

DD

V

CL1

MD0/P30

MD1/P31

PP

DD

DD

t

I

V

V

D0/P40-D3/P43
D4/P50-D7/P53

t

VPS

t

VDS

t

XH

t

XL

Data output

t

DV

t

HAD

t

DAD

Data output



t

M3HR

t

DFR

MD2/P32

MD3/P33

t

PCR

t

M3SR

45

10. CHARACTERISTICS CURVES (REFERENCE VALUE)

DD

vs VDD (Main system clock : 1.0 MHz RC oscillation)

I

10

5.0

µ

PD75P0116

(T

A

= 25 °C)

1.0

0.5

(mA)

DD

0.1

Supply Current I

0.05

PCC = 0011

PCC = 0010
PCC = 0001
PCC = 0000

Main system clock HALT mode
+32-kHz oscillation

Subsystem clock operation mode
(Low voltage)

Subsystem clock HALT mode
(SOS.1 = 0) and main system
clock STOP mode +32-kHz
oscillation (SOS.1 = 0)

Subsystem clock HALT mode
(SOS.1 = 1) and main system
clock STOP mode +32-kHz
oscillation (SOS.1 = 1)

46

0.01

0.005

0.001
01234

Supply Voltage V

CL1

CL2 XT1 XT2

RC
oscillation

22 kΩ

Crystal
resontor

32.768 kHz

220 kΩ

22 pF 33 pF 33 pF

5678

DD

(V)

µ

PD75P0116

11. RC OSCILLATION FREQUENCY CHARACTERISTICS EXAMPLES (REFERENCE VALUE)

CC

vs VDD (RC oscillation, R = 22kΩ, C = 22 pF)

f

A

= –40 °C)

2.0

(MHz)

CC

1.0

CL1 CL2

22 kΩ

22 pF

Sample A

(T

Main system clock frequency f

0.5
0

Sample B
Sample C

1234

2.0

CL1 CL2

(MHz)

CC

22 pF

22 kΩ

1.0

Sample A

Sample B
Sample C

Main system clock frequency f

0.5
0

1234

2.0

Supply voltage VDD (V)

Supply voltage VDD (V)

5678

(T

A

= 25 °C)

5678

(T

A

= 85 °C)

CL1 CL2

(MHz)

CC

1.0

22 pF

22 kΩ

Sample A

Sample B
or Sample C

Main system clock frequency f

0.5
0

1234

Supply voltage VDD (V)

5678

47

fCC vs TA (RC oscillation, R = 22kΩ, C = 22 pF)

µ

PD75P0116

2.0

(MHz)

CC

CL1

22 pF

CL2

22 kΩ

1.0

Main system clock frequency f

0.5
–60

–40 –20 0 +20

2.0

CL1 CL2

(MHz)

CC

22 pF

22 kΩ

+40 +60 +80 +100

Operating ambient temperature TA (°C)

(Sample A)

VDD = 5.0 V
V

DD

= 3.0 V

DD

= 2.2 V

V

DD

= 1.8 V

V

(Sample B)

1.0

Main system clock frequency f

0.5
–60

–40 –20 0 +20

2.0

CL1 CL2

(MHz)

CC

22 pF

22 kΩ

1.0

+40 +60 +80 +100

Operating ambient temperature TA (°C)

DD

= 5.0 V

V

DD

= 3.0 V

V

DD

= 2.2 V

V

VDD = 1.8 V

(Sample C)

DD

= 5.0 V

V

DD

= 3.0 V

V
VDD = 2.2 V

VDD = 1.8 V

48

Main system clock frequency f

0.5
–60

–40 –20 0 +20

+40 +60 +80 +100

Operating ambient temperature TA (°C)

12. PACKAGE DRAWINGS

42PIN PLASTIC SHRINK DIP (600 mil)

µ

PD75P0116

42

1

22

21

A

K

L

I

J

H

G

F

D

M

N

B

C

M

R

NOTES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

2) Item "K" to center of leads when formed parallel.

ITEM MILLIMETERS INCHES

A

39.13 MAX.

B

1.78 MAX.

C

1.778 (T.P.)
D 0.50±0.10 0.020
F

G
H

I

J
K
L 13.2 0.520

M 0.25 0.010
N

R



0.9 MIN.

3.2±0.3

0.51 MIN.

4.31 MAX.

5.08 MAX.

15.24 (T.P.)

+0.10
–0.05

0.17
0~15° 0~15°

1.541 MAX.

0.070 MAX.

0.070 (T.P.)
+0.004

–0.005

0.035 MIN.

0.126±0.012

0.020 MIN.



0.170 MAX.

0.200 MAX.

0.600 (T.P.)

+0.004
–0.003

0.007

P42C-70-600A-1

49

44 PIN PLASTIC QFP ( 10)

A
B

µ

PD75P0116

34

33

23

22

CD

44

1

11

12

F

J

G

H

M

I

K

P

N

NOTE

Each lead centerline is located within 0.16 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

L

detail of lead end

S

R

Q

M

ITEM MILLIMETERS INCHES

A 13.2±0.2 0.520

B 10.0±0.2

C 10.0±0.2

D 13.2±0.2

F

1.0

G

1.0

H

I

J
K

L 0.8±0.2

M 0.17 0.007
N

P

Q 0.125±0.075
R3° 3°

S

+0.08

0.37

–0.07

0.16

0.8 (T.P.)

1.6±0.2

+0.06
–0.05

0.10

2.7

+7°

–3°



3.0 MAX.

+0.008
–0.009

+0.008

0.394

–0.009
+0.008

0.394

–0.009
+0.008

0.520

–0.009

0.039

0.039
+0.003

0.015

–0.004

0.007

0.031 (T.P.)

0.063±0.008

+0.009

0.031

–0.008

+0.002

–0.003

0.004

0.106

0.005±0.003

+7°
–3°

0.119 MAX.

S44GB-80-3BS

50

µ

PD75P0116

13. RECOMMENDED SOLDERING CONDITIONS

Solder the µPD75P0116 under the following recommended conditions.
For the details on the recommended soldering conditions, refer to Information Document Semiconductor

Device Mounting Technology Manual (C10535E).

For the soldering methods and conditions other than those recommended, consult NEC.

Table 13-1. Soldering Conditions of Surface Mount Type

µ

PD75P0116GB-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)

Soldering method Soldering conditions recommended

Infrared reflow Package peak temperature: 235 ˚C, Time: 30 seconds max. (210 ˚C min.), IR35-00-3

Number of times: 3 max.

VPS Package peak temperature: 215 ˚C, Time: 40 seconds max. (200 ˚C min.), VP15-00-3

Number of times: 3 max.

Wave soldering Soldering bath temperature: 260 ˚C max., Time: 10 seconds max., WS60-00-1

Number of times: 1
Preheating temperature: 120 ˚C max. (package surface temperature)

Partial heating Pin temperature: 300 ˚C max., Time: 3 seconds max. (per side of device) –

Symbol of

condition

Caution Do not use two or more soldering methods in combination (except the partial heating method).

Table 13-2. Soldering Conditions of Insertion Type

µ

PD75P0116CU: 42-pin plastic Shrink DIP (600 mil, 1.778-mm pitch)

Soldering method Soldering conditions

Wave soldering (pin only) Soldering bath temperature: 260 ˚C max., Time: 10 seconds max.
Partial heating Pin temperature: 300 ˚C max., Time: 3 seconds max. (per pin)

Caution Apply wave soldering to the pins only. Be careful not to allow solder jet to come into direct

contact with the body of the chip.

51

µ

PD75P0116

APPENDIX A. FUNCTION LIST OF µPD750008, 750108, AND 75P0116

Parameter

Program memory Mask ROM One-time PROM

Data memory 000H-1FFH

CPU 75XL CPU
General register (4 bits × 8 or 8 bits × 4) × 4 banks
Main system clock oscillation circuit Crystal/ceramic oscillation RC oscillation circuit (external resistor and capacitor)

Start-up time after reset 217/fX, 215/fX 56/fCC fixed

Wait time after releasing STOP 220/fX, 217/fX, 215/fX, 213/fX 29/fCC, no wait 29/fCC fixed
mode due to interrupt occurrence (Selected by setting BTM) (Selected by mask option)

Subsystem clock oscillation circuit Crystal oscillation circuit
Instruction When main system • 0.95, 1.91, 3.81, 15.3 µs • 4, 8, 16, 64 µs (at fCC = 1.0 MHz operation)

execution clock is selected (at fX = 4.19-MHz operation) • 2, 4, 8, 32 µs (at fCC = 2.0 MHz operation)
time • 0.67, 1.33, 2.67, 10.7 µs

When subsystem 122 µs (at 32.768 kHz operation)
clock is selected

I/O port CMOS input 8 (on-chip pull-up resistors can be specified in software: 7)

CMOS input/output 18 (on-chip pull-up resistors can be specified in software)
N-ch open drain 8 (on-chip pull-up resistors can be specified in 8 (no mask option)

input/output software), Withstand voltage is 13 V Withstand voltage is 13 V.
Total 34

Timer 4 channels 4 channels

Serial interface 3 modes are available

Clock output (PCL) • Φ, 524, 262, 65.5 kHz • Φ, 125, 62.5, 15.6 kHz

Buzzer output (BUZ) • 2, 4, 32 kHz • 2, 4, 32 kHz

µ

PD750008

0000H-1FFFH 0000H-3FFFH
(8192 × 8 bits) (16384 × 8 bits)

(512 × 4 bits)

circuit

(Selected by mask option)

(at fX = 6.0-MHz operation)

• 8-bit timer counter: • 8-bit timer counter (with watch timer output function):
1 channel 1 channel

• 8-bit timer/event counter: • 8-bit timer/event counter: 1 channel
1 channel • Basic interval timer/watchdog timer: 1 channel

• Basic interval timer/ • Watch timer: 1 channel
watchdog timer: 1 channel

• Watch timer: 1 channel

• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit

• 2-wire serial I/O mode

• SBI mode

(Main system clock: (main system clock: at 1.0-MHz operation)
at 4.19-MHz operation) • Φ, 250, 125, 31.3 kHz

• Φ, 750, 375, 93.8 kHz (main system clock: at 2.0-MHz operation)
(Main system clock:
at 6.0-MHz operation)

(Main system clock: (Subsystem clock: at 32.768-kHz operation)
at 4.19-MHz operation • 0.488, 0.977, 7.813 kHz
or subsystem clock: (Main system clock: at 1.0-MHz operation)
at 32.768-kHz operation) • 0.977, 1.953, 15.625 kHz

• 2.93, 5.86, 46.9 kHz (Main system clock: at 2.0-MHz operation)
(Main system clock:
at 6.0-MHz operation)

µ

PD750108

µ

PD75P0116

(1/2)

52

Parameter
Vectored interrupt External: 3, internal: 4
Test input External: 1, internal: 1
Operation supply voltage VDD = 2.2 to 5.5 V VDD = 1.8 to 5.5 V
Operating ambient temperature TA = –40 to +85 ˚C
Package • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

µ

PD750008

• 44-pin plastic shrink QFP (10 × 10 mm, 0.8-mm pitch)

µ

PD750108

µ

PD75P0116

µ

PD75P0116

(2/2)

53

µ

PD75P0116

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are provided for system development using the µPD75P0116. The 75XL series uses

a common relocatable assembler, in combination with a device file matching each machine.

RA75X relocatable assembler Host machine Part number

OS Supply medium (product name)

PC-9800 series MS-DOS

IBM PC/AT
or compatible IBM PCs 5" 2HC

Device file Host machine Part number

PC-9800 series MS-DOS 3.5" 2HD

IBM PC/AT Refer to OS for 3.5" 2HC
or compatible IBM PCs 5" 2HC

TM

Refer to OS for 3.5" 2HC

TM

Ver.3.30 to 5" 2HD

Note

Ver.6.2

OS Supply medium (product name)

Ver.3.30 to 5" 2HD

Note

Ver.6.2

3.5" 2HD

µ

S5A13RA75X

µ

S5A10RA75X

µ

S7B13RA75X

µ

S7B10RA75X

µ

S5A13DF750008

µ

S5A10DF750008

µ

S7B13DF750008

µ

S7B10DF750008

Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swap function, but it does not work with this

software.

Remark The operation of the assembler and device file is guaranteed only on the above host machines and OSs.

54

µ

PD75P0116

PROM Write Tools

Hardware PG-1500 A stand-alone system can be configured of a single-chip microcomputer with on-chip PROM

when connected to an auxiliary board (companion product) and a programmer adapter
(separately sold). Alternatively, a PROM programmer can be operated on a host machine for
programming.
In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed.

PA-75P008CU This is a PROM programmer adapter for the µPD75P0116CU/GB. It can be used when

connected to a PG-1500.

Software PG-1500 controller Establishes serial and parallel connections between the PG-1500 and a host machine for host-

machine control of the PG-1500.
Host machine Part number

OS Supply medium (product name)

PC-9800 Series MS-DOS 3.5" 2HD

Ver.3.30 to 5" 2HD

Note

Ver.6.2
IBM PC/AT Refer to OS for 3.5" 2HD
or compatible IBM PCs 5" 2HC

Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work with

this software.

µ

S5A13PG1500

µ

S5A10PG1500

µ

S7B13PG1500

µ

S7B10PG1500

Remark Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.

55

µ

PD75P0116

Debugging Tools

In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P0116.

Various system configurations using these in-circuit emulators are listed below.

Hardware IE-75000-R

IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during

IE-75300-R-EM This is an emulation board for evaluating application systems that use the µPD750108

EP-75008CU-R This is an emulation probe for the µPD75P0116CU.

EP-75008GB-R This is an emulation probe for the µPD75P0116GB.
EV-9200G-44 When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

Software IE control program This program can control the IE-75000-R or IE-75001-R on a host machine when connected to

Note 1

The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems that use 75X or 75XL Series products. For development
of the µPD750108 subseries, the IE-75000-R is used with a separately sold emulation board IE­75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.
The IE-75000-R can include a connected emulation board (IE-75000-R-EM).

development of application systems that use 75X or 75XL Series products. The IE-75001-R is
used with a separately sold emulation board IE-75300-R-EM and emulation probe EP­75008CU-R or EP-75008GB-R.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.

subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator.

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

It includes a 44-pin conversion socket EV-9200G-44 to facilitate connections with various target
systems.

the IE-75000-R or IE-75001-R via an RS-232-C or Centronics I/F.
Host machine Part number

OS Supply medium (product name)

PC-9800 series MS-DOS 3.5" 2HD

Ver.3.30 to 5" 2HD

Note 2

Ver.6.2
IBM PC/AT Refer to OS for 3.5" 2HC
or compatible IBM PCs 5" 2HC

µ

S5A13IE75X

µ

S5A10IE75X

µ

S7B13IE75X

µ

S7B10IE75X

Notes 1. This is a service part provided for maintenance purpose only.

2. Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work

with this software.

Remarks 1. Operation of the IE control program is guaranteed only on the above host machine and OSs.

µ

2. The

PD750108 subseries consists of the µPD750104, 750106, 750108 and 75P0116.

56

µ

PD75P0116

OS for IBM PCs

The following operating systems for the IBM PC are supported.

OS Version

PC DOS

MS-DOS Ver.5.0 to Ver.6.22

IBM DOS

Note Supports English version only.

Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function.

TM

TM

Ver.3.1 to Ver.6.3

Note

J6.1/V

5.0/V
J5.02/V

Note

Note

to J6.3/V

to J6.2/V

Note

Note

57

µ

PD75P0116

APPENDIX C. RELATED DOCUMENTS

Some of the following related documents are preliminary. This document, however, is not indicated as

preliminary.

Device Related Documents

Document name

µ

PD750104, 750106, 750108, 750104(A), 750106(A), 750108(A) U12301J Planned

Data Sheet

µ

PD75P0116 Data Sheet U12603J This document

µ

PD750108 User’s Manual U11330J U11330E

µ

PD750008, 750108 Instruction List U11456J –

75XL Series Selection Guide U10453J U10453E

Japanese English

Document No.

Development Tool Related Documents

Document No.

Hardware

Software

Document name

IE-75000 R/IE-75001-R User’s Manual EEU-846 EEU-1416
IE-75300-R-EM User’s Manual U11354J U11354E
EP-750008CU-R User’s Manual EEU-699 EEU-1317
EP-750008GB-R User’s Manual EEU-698 EEU-1305
PG-1500 User’s Manual U11940J EEU-1335
RA75X Assembler Package Operation EEU-731 EEU-1346
User’s Manual Language EEU-730 EEU-1363
PG-1500 Controller User’s Manual PC-9800 Series EEU-704 EEU-1291

(MS-DOS) Base
IBM PC Series EEU-5008 U10540E

(PC DOS) Base

Japanese English

Other Documents

Document name

IC Package Manual C10943X
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grades on NEC Semiconductor Devices C11531J C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E
Static Electricity Discharge (ESD) Test MEM-539 –
Semiconductor Devices Quality Guarantee Guide C11893J MEI-1202
Guide for Products Related to Microcomputer : Other Companies C11416J –

Japanese English

Document No.

Caution The above related documents are subject to change without notice. For design purpose, etc.,

be sure to use the latest documents.

58

[MEMO]

µ

PD75P0116

59

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools includ­ing work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with
bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.

µ

PD75P0116

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry.
Each unused pin should be connected to VDD or GND with a resistor, if it is
considered to have a possibility of being an output pin. All handling related
to the unused pins must be judged device by device and related specifications
governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immedi­ately after power-on for devices having reset function.

60

µ

PD75P0116

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel:[phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: [phone]
Fax: [phone]

J96. 8

61

µ

PD75P0116

[MEMO]

MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

62

M4 96.5