Datasheet UPD75P0076GT, UPD75P0076CU Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD75P0076

4-BIT SINGLE-CHIP MICROCONTROLLER

The µPD75P0076 replaces the µPD750068’s internal mask ROM with a one-time PROM and features expanded ROM
capacity.

µ

Because the
development using the µPD750064, 750066, and 750068 products, and for use in small-lot production.

PD75P0076 supports programming by users, it is suitable for use in prototype testing for system

Detailed information about function is provided in the following user’s manual.

Be sure to read it before designing:

µ

PD750068 User’s Manual: U10670E

FEATURES

Compatible with µPD750068
Memory capacity:

• PROM : 16384 x 8 bits

• RAM : 512 x 4 bits
Can operate with same power supply voltage as the mask ROM version µPD750068
VDD = 1.8 to 5.5 V
On-chip A/D converter capable of low-voltage operation (AVREF = 1.8 to 5.5 V)
8-bit resolution x 8 channels

Small shrink SOP package

ORDERING INFORMATION

Part Number Package

µ

PD75P0076CU 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

µ

PD75P0076GT 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)

Caution On-chip pull-up resistors by mask option cannot be provided.

Document No. U10232EJ1V0DS00 (1st edition)
Date Published December 1996 N
Printed in Japan

The information in this document is subject to change without notice.

The mark shows major revised points.

©

1995

µ

PD75P0076

Functional Outline

Parameter Function

Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock)

• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock)

• 122 µs (@ 32.768 kHz with subsystem clock)

On-chip memory PROM 16384 x 8 bits

RAM 512 x 4 bits

General-purpose register • 4-bit operation: 8 x 4 banks

• 8-bit operation: 4 x 4 banks

Input/ CMOS input 12 Connections of on-chip pull-up resistors can be specified by software: 7
output Also used for analog input pins: 4
port

Timer 4 channels

Serial interface • 3-wire serial I/O mode ··· MSB or LSB can be selected for transferring first bit

A/D converter 8-bit resolution x 8 channels (1.8 V ≤ AVREF ≤ VDD)
Bit sequential buffer 16 bits
Clock output (PCL) • Φ, 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19 MHz with main system clock)

Buzzer output (BUZ) • 2, 4, 32 kHz (@ 4.19 MHz with main system clock or

Vectored interrupts External: 3, Internal: 4
Test input External: 1, Internal: 1
System clock oscillator • Ceramic or crystal oscillator for main system clock oscillation

Standby function STOP/HALT mode
Operating ambient temperature
Power supply voltage VDD = 1.8 to 5.5 V
Package • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

CMOS input/output 12 Connections of on-chip pull-up resistors can be specified by software: 12

Also used for analog input pins: 4

N-ch open-drain 8 13-V withstand voltage
input/output pins

Total 32

•

8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter)

• 8-bit basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

• 2-wire serial I/O mode

• Φ, 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0 MHz with main system clock)

@ 32.768 kHz with subsystem clock)

• 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock)

• Crystal oscillator for subsystem clock oscillation

TA = –40 to +85 ˚C

• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)

2

µ

PD75P0076

CONTENTS

1. PIN CONFIGURATION (Top View) ................................................................................................... 4

2. BLOCK DIAGRAM ............................................................................................................................ 5

3. PIN FUNCTIONS ............................................................................................................................... 6

3.1 Port Pins ................................................................................................................................................... 6

3.2 Non-port Pins ........................................................................................................................................... 7

3.3 Equivalent Circuits for Pins .................................................................................................................... 9

3.4 Handling of Unused Pins......................................................................................................................... 12

4. SWITCHING BETWEEN Mk I AND Mk II MODES ............................................................................ 13

4.1 Difference betweens Mk I Mode and Mk II Mode .................................................................................... 13

4.2 Setting of Stack Bank Selection (SBS) Register .................................................................................... 14

5. DIFFERENCES BETWEEN µPD75P0076 AND µPD750064, 750066 AND 750068........................ 15

6. MEMORY CONFIGURATION ............................................................................................................ 16

7. INSTRUCTION SET ........................................................................................................................... 18

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................... 29

8.1 Operation Modes for Program Memory Write/Verify ............................................................................. 29

8.2 Steps in Program Memory Write Operation............................................................................................ 30

8.3 Steps in Program Memory Read Operation............................................................................................ 31

8.4 One-time PROM Screening ..................................................................................................................... 32

9. ELECTRICAL SPECIFICATIONS...................................................................................................... 33

10. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................ 49

11. PACKAGE DRAWINGS .................................................................................................................... 51

12. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 53

APPENDIX A DIFFERENCES AMONG µPD75068, 750068 AND 75P0076......................................... 54

APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 55

APPENDIX C RELATED DOCUMENTS ................................................................................................. 58

3

1. PIN CONFIGURATION (Top View)

• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

µ

PD75P0076CU

• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)

µ

PD75P0076GT

µ

PD75P0076

XT1
XT2

RESET

X1

X2
P33/MD3
P32/MD2
P31/MD1
P30/MD0

AV
P63/KR3/AN7
P62/KR2/AN6
P61/KR1/AN5
P60/KR0/AN4

P113/AN3
P112/AN2
P111/AN1
P110/AN0

AV

REF

V
V

1
2
3
4
5
6
7
8
9

SS

PP
DD

10
11
12
13
14
15
16
17
18
19
20
21

42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22

V

SS

P40/D0
P41/D1
P42/D2
P43/D3
P50/D4
P51/D5
P52/D6
P53/D7
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0
P11/INT1
P12/TI1/INT2
P13/TI0
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ

In normal operation mode, make sure to connect VPP directly to VDD.

Pin Identification

AN0 to AN7 : Analog Input 0 to 7 P110 to P113 : Port 11
AVREF : Analog Reference PCL : Programmable Clock
AV

SS : Analog Ground PTO0, PTO1 : Programmable Timer Output 0, 1

BUZ : Buzzer Clock RESET : Reset Input
D0 to D7 : Data Bus 0 to 7 SB0, SB1 : Serial Data Bus 0, 1
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 SCK : Serial Clock
INT2 : External Test Input 2 SI : Serial Input
KR0 to KR3 : Key Return SO : Serial Output
MD0 to MD3 : Mode Selection 0 to 3 TI0, TI1 : Timer Input 0, 1
P00 to P03 : Port 0 V
P10 to P13 : Port 1 VPP : Programmable Power Supply
P20 to P23 : Port 2 V
P30 to P33 : Port 3 X1, X2 : Main System Clock Oscillation 1, 2
P40 to P43 : Port 4 XT1, XT2 : Subsystem Clock Oscillation 1, 2
P50 to P53 : Port 5
P60 to P63 : Port 6

DD : Positive Power Supply

SS : Ground

4

2. BLOCK DIAGRAM

µ

PD75P0076

BUZ/P23

TI0/P13

PTO0/P20

TI1/P12/INT2

PTO1/P21

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT0/P10
INT1/P11
INT4/P00

INT2/P12/TI1

KR0/P60 to
KR3/P63

AN0/P110 to
AN3/P113

AN4/P60 to
AN7/P63

BASIC INTERVAL
TIMER/WATCHDOG
TIMER

WATCH TIMER

INTW

8-BIT
TIMER/
EVENT
COUNTER#0

8-BIT
TIMER/
EVENT
COUNTER#1

CLOCKED SERIAL

INTERFACE

INTERRUPT

CONTROL

4

4

4

A/D CONVERTER

INTBT

INTW

INTT0

CASCADED
16-BIT
TIMER/
EVENT
COUNTER

INTT1

TOUT0INTCSI

SP (8)

ALU

PROGRAM COUNTER

CY

SBS

BANK

GENERAL REG.

PROGRAM

MEMORY

(PROM)

16384 x 8 BITS

DECODE

AND

CONTROL

CLOCK
OUTPUT
CONTROL

CLOCK
DIVIDER

DATA MEMORY

(RAM)

512 x 4BITS

N

fx/2

SYSTEM CLOCK
GENERATOR

SUB MAIN

CPU CLOCK Φ

PCL/P22 XT1 XT2 X1 X2

STAND BY
CONTROL

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

PORT11

P00 to P034

P10 to P13

4

P20 to P23

4

P30/MD0 to

4

P33/MD3

P40/D0 to

4

P43/D3

P50/D4 to

4

P53/D7

P60 to P63

4

P110 to P113

4

BIT SEQ. BUFFER (16)

PP VDD VSS RESET

V

AV

AVSS

REF

5

3. PIN FUNCTIONS

3.1 Port Pins

µ

PD75P0076

Pin name I/O Alternate function Function

8-bit After I/O circuit

accessible reset type

Note 1

P00 I INT4 This is a 4-bit input port (PORT0). Not Input <B>

For P01 to P03, on-chip pull-up resistors are available

P01 I/O SCK software-specifiable in 3-bit units. <F>-A
P02 I/O SO/SB0 <F>-B
P03 I/O SI/SB1 <M>-C
P10 I INT0 This is a 4-bit input port (PORT1). Not Input <B>-C

Connections of on-chip pull-up resistors are available

P11 INT1 software-specifiable in 4-bit units. P10/INT0

can select a noise elimination circuit.

P12 TI1/INT2
P13 TI0
P20 I/O PTO0 This is a 4-bit I/O port (PORT2). Not Input E-B

Connections of on-chip pull-up resistors are available

P21 PTO1 software-specifiable in 4-bit units.
P22 PCL
P23 BUZ
P30 I/O MD0 This is a programmable 4-bit I/O port (PORT3). Not Input E-B

Input and output can be specified in single-bit available

P31 MD1 units. Connections of on-chip pull-up resistors

are software-specifiable in 4-bit units.

P32 MD2
P33 MD3

Note 2

P40
P41
P42
P43
P50
P51
P52
P53

Note 2

Note 2

Note 2

Note 2

Note 2

Note 2

Note 2

I/O D0 This is an N-ch open-drain 4-bit I/O port Available High

(PORT4). In the open-drain mode, withstands impedance M-E

D1 up to 13 V. Also used as data I/O pin

(lower 4 bits) for program memory (PROM)

D2 write/verify.
D3

I/O D4 This is an N-ch open-drain 4-bit I/O port High

(PORT5). In the open-drain mode, withstands impedance M-E

D5 up to 13 V. Also used as data I/O pin

(upper 4 bits) for program memory (PROM)

D6 write/verify.
D7

P60 I/O KR0/AN4 This is a programmable 4-bit I/O port (PORT6). Not Input <Y>-D

Input and output can be specified in single-bit available

P61 KR1/AN5 units. Connections of on-chip pull-up resistors

are software-specifiable in 4-bit units.

P62 KR2/AN6
P63 KR3/AN7
P110 I AN0 This is a 4-bit input port (PORT11). Not Input Y-A

available

P111 AN1
P112 AN2
P113 AN3

Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.

2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.

6

3.2 Non-port Pins (1/2)

µ

PD75P0076

Pin name I/O

TI0 I P13 Inputs external event pulses to the timer/event Input <B>-C
TI1 P12/INT2
PTO0 O P20 Timer/event counter output Input E-B
PTO1 P21
PCL P22 Clock output
BUZ P23 Optional frequency output (for buzzer output or

SCK I/O P01 Serial clock I/O Input <F>-A
SO/SB0 P02 Serial data output <F>-B

SI/SB1 P03 Serial data input <M>-C

INT4 I P00 Edge detection vectored interrupt input (both rising <B>

INT0 I P10 Edge detection vectored Noise eliminator/ Input <B>-C

INT1 P11 edge can be selected). Asynchronous

INT2 P12/TI1 Rising edge detection Asynchronous

KR0 to KR3 I P60/AN4 to Falling edge detection testable input Input <Y>-D

AN0 to AN3 I
AN4 to AN7 P60/KR0 to <Y>-D

AVREF — — A/D converter reference voltage — Z-N
AVSS — — A/D converter reference GND potential — Z-N
X1 I — Crystal/ceramic connection pin for the main system — —

X2 — clock oscillator. When inputting the external clock,

XT1 I — Crystal connection pin for the subsystem clock — —
XT2 — oscillator. When the external clock is used, input the

RESET I — System reset input (low-level active) — <B>

Alternate function

P63/AN7
P110 to P113

P63/KR3

Function

counter.

system clock trimming)

Serial data bus I/O

Serial data bus I/O

edge and falling edge detection)

interrupt input (detection asynchronous selection

INT0/P10 can select a noise
eliminator.

testable input

Analog signal input Input Y-A

input the external clock to pin X1, and the inverted
phase of the external clock to pin X2.

external clock to pin XT1, and the inverted phase of
the external clock to pin XT2. Pin XT1 can be used
as a 1-bit input (test) pin.

After Circuit
reset type

Note

Note Circuit types enclosed in brackets indicate Schmitt triggered inputs.

7

3.2 Non-port Pins (2/2)

µ

PD75P0076

Pin name I/O

MD0 to MD3 I P30 to 33 Mode selection for program memory (PROM) Input E-B

D0 to D3 I/O P40 to 43
D4 to D7 P50 to 53

Note

VPP

VDD — — Positive power supply — —
VSS — — Ground — —

Alternate function

write/verify.
Data bus pin for program memory (PROM) write/verify.

— — Programmable voltage supply in program memory — —

(PROM) write/verify mode.
In normal operation mode, connect directly to VDD.
Apply +12.5 V in PROM write/verify mode.

Function

After Circuit
reset type

Input M-E

Note During normal operation, the VPP pin will not operate normally unless connected to VDD pin.

8

3.3 Equivalent Circuits for Pins

The equivalent circuits for the µPD75P0076’s pin are shown in schematic diagrams below.

TYPE A TYPE D

V

DD

Data

IN

CMOS standard input buffer

P-ch

N-ch

Output

disable

Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).

µ

PD75P0076

V

DD

P-ch

OUT

N-ch

(1/3)

TYPE E-BTYPE B

IN

Schmitt trigger input with hysteresis characteristics.

TYPE B-C TYPE F-A

V

DD

P.U.R.

P-ch

P.U.R.
enable

Data

Output

disable

P.U.R.
enable

Type D

Type A

P.U.R. : Pull-Up Resistor

P.U.R.

enable

V

DD

P-ch

IN/OUT

V

DD

P.U.R.

P.U.R.

P-ch

IN

P.U.R. : Pull-Up Resistor

Schmitt trigger input with hysteresis characteristics.

Data

Output

disable

Type D

IN/OUT

Type B

P.U.R. : Pull-Up Resistor

9

TYPE F-B TYPE Y

V

DD

µ

PD75P0076

(2/3)

Output
disable
(P)

Data
Output
disable

TYPE M-C

Output
disable

Output
disable
(N)

P.U.R. : Pull-Up Resistor

P.U.R.
enable

Data

P.U.R.
enable

N-ch

V

DD

P-ch

N-ch

V

DD

P.U.R.

P-ch

P-ch

IN/OUT

P.U.R.

IN/OUT

IN

V

DD

TYPE Y-A

IN

P-ch
N-ch

AV

SS

Input

enable

Type Y

Sampling C

Reference voltage
(from the voltage tap of
the serial resistor string)

Type A

V

DD

+

–

AV

SS

IN instruction

Input butfer

10

P.U.R. : Pull-Up Resistor

TYPE M-E*

Data

Output
disable

V

DD

Input
instruction

P-ch

P.U.R.

Note

Voltage
control
circuit

Note This is a pull-up resistor which only

operates when an input instruction
is executed (when the pin is low
a current flows from V

N-ch

(+13 V withstand
voltage)

(+13 V withstand
voltage)

DD

to the pin).

IN/OUT

µ

PD75P0076

(3/3)

TYPE Y-D

Data

Output
disable

P.U.R.
enable

Type D

Type B

Type Y

P.U.R.: Pull-Up Resistor

V

DD

P.U.R.

P-ch

IN/OUT

TYPE Z-N

AV

ADEN

REF

N-ch

AV

Reference
voltage

SS

11

3.4 Handling of Unused Pins

P00/INT4 Connect to VSS or VDD
P01/SCK Independently connect to VSS or VDD through
P02/SO/SB0
P03/SI/SB1 Connected to VSS
P10/INT0, P11/INT1 Connect to VSS or VDD
P12/TI1/INT2
P13/TI0
P20/PTO0 Input mode : independently connected to VSS
P21/PTO1 or VDD through resistor
P22/PCL Output mode : open
P23/BUZ
P30/MD0 to P33/MD3
P40/D0 to P43/D3 Connected to VSS
P50/D4 to P53/D7
P60/KR0/AN4 to P63/KR3/AN7 Input mode : independently connected to VSS

P110/AN0 to P113/AN3 Connected to VSS or VDD

Note

XT1

Note

XT2
VPP Make sure to connect directly to VDD
AVREF Connect to VSS
AVSS

Pin Recommended connection

resistor

or VDD through resistor

Output mode : open

Connect to VSS or VDD
Open

µ

PD75P0076

Note When the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback resistor is not used).

12

µ

PD75P0076

4. SWITCHING BETWEEN Mk I AND Mk II MODES

Setting a stack bank selection (SBS) register for the µPD75P0076 enables the program memory to be switched between
the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD750064, 750066, and 750068 using
the µPD75P0076.

µ

When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of
When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD750064, 750066, and 750068)

4.1 Differences between Mk I Mode and Mk II Mode

Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the

Table 4-1. Differences between Mk I Mode and Mk II Mode

Item Mk I Mode Mk II Mode
Program counter PC13 to 0
Program memory (bytes) 16384
Data memory (bits) 512 x 4
Stack Stack bank Selectable from memory banks 0 and 1

Stack bytes 2 bytes 3 bytes

Instruction BRA !addr1 Not provided Provided

CALLA !addr1
Instruction CALL !addr 3 machine cycles 4 machine cycles
execution time CALLF !faddr 2 machine cycles 3 machine cycles
Supported mask ROM versions and Mk I mode of µPD750064, 750066, Mk II mode of µPD750064, 750066,

mode and 750068 and 750068

PD750064, 750066, and 750068)

µ

PD75P0076.

Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This

mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when
a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle.
Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.

13

µ

PD75P0076

4.2 Setting of Stack Bank Selection (SBS) Register

Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format
for doing this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be

Note

sure to initialize the stack bank selection register to 100xB

Note

be sure to initialize it to 000xB

.

at the beginning of the program. When using the Mk II mode,

Note Set the desired value for x.

Figure 4-1. Format of Stack Bank Selection Register

Address 3 2 1 0

SBS3 SBS2 SBS1 SBS0F84H

Symbol

SBS

Stack area specification

0
0
1
1

0 Be sure to enter “0” for bit 2.

Memory bank 0

0

Memory bank 1

1
0

Setting prohibited

1

Mode selection specification

01Mk II mode

Mk I mode

Cautions 1. SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When

using instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the
instructions.

2. When using the Mk II mode, execute a subroutine call instruction and an interrupt instruction after
RESET input and after setting the stack bank selection register.

14

µ

PD75P0076

5. DIFFERENCES BETWEEN µPD75P0076 AND µPD750064, 750066 AND 750068

The µPD75P0076 replaces the internal mask ROM in the µPD750064, 750066, and 750068 with a one-time PROM and
features expanded ROM capacity. The µPD75P0076’s Mk I mode supports the Mk I mode in the µPD750064, 750066,
and 750068 and the µPD75P0076’s Mk II mode supports the Mk II mode in the µPD750064, 750066, and 750068.

µ

Table 5-1 lists differences among the
differences between corresponding versions beforehand, especially when a PROM version is used for debugging or
prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production.
For further description of CPU functions and internal hardware, see the

Information (U10165E).

Table 5-1. Differences between

PD75P0076 and the µPD750064, 750066, 750068. Be sure to check the

µ

PD750064 and 750068 Preliminary Product

µ

PD75P0076 and µPD750064, 750066, 750068

Item
Program counter 12-bit 13-bit 14-bit
Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM

Data memory (x 4 bits) 512
Mask options Pull-up resistor for Yes (on-chip specifiable) No (off chip)

ports 4 and 5
Wait time when Yes (217/fX, 215/fX selectable)

RESET
Feedback resistor of Yes (Use/not use selectable) No (Use)

subsystem clock

Pin configuration Pins 6 to 9 P33 to P30 P33/MD3 to P30/MD0

Pin 20 IC VPP
Pins 34 to 37 P53 to P50 P53/D7 to P53/D4
Pins 38 to 41 P43 to P40 P43/D3 to P40/D0

Other Noise resistance and noise radiation may differ due to different circuit complexities

µ

PD750064

4096 6144 8192 16384

and mask layouts.

µ

PD750066

Note

µ

PD750068

No (fixed at 215/fX)

µ

PD75P0076

Note

Note 217/fX is 21.8 ms in 6.0 MHz operation and 31.3 ms in 4.19 MHz operation.

215/fX is 5.46 ms in 6.0 MHz operation and 7.81 ms in 4.19 MHz operation.

Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using

a mask ROM version instead of the PROM version for processes between prototype development and
full production, be sure to fully evaluate the CS of the mask ROM version (not ES).

15

6. MEMORY CONFIGURATION

76 0

MBE

RBE

0000H

0002H

0004H

0006H

0008H

000AH

000CH

MBE

MBE

MBE

MBE

MBE

MBE

Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)

RBE

INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)

RBE

INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)

RBE

INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)

RBE

INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)

RBE

INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)

RBE

INTT1 start address (upper 6 bits)
INTT1 start address (lower 8 bits)

Figure 6-1. Program Memory Map

CALLF

!faddr instruction

entry address

BRCB

!caddr instruction

branch address

the following instructions

Branch address for

• BR BCDE

• BR BCXA

• BR !addr

• BRA !addr1

• CALLA !addr1

µ

PD75P0076

Note

Note

0020H

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH

Reference table for GETI instruction

!caddr instruction

branch address

!caddr instruction

branch address

!caddr instruction

branch address

CALL !addr instruction

subroutine

entry address

BR $addr instruction

relative branch address

(–15 to –1,
+2 to +16)

BRCB

BRCB

BRCB

Branch destination

address specified by

GETI instruction,

subroutine entry

address

Note Can be used only in Mk II mode.

Remark For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to

branch to addresses with changes in the PC’s lower 8 bits only.

16

Figure 6-2. Data Memory Map

µ

PD75P0076

Data area

static RAM

(512 x 4)

General
register

area

Stack area

Note

000H

01FH
020H

0FFH

100H

1FFH

Data memory

(32 x 4)

256 x 4

(224 x 4)

256 x 4

Memory bank

0

1

Peripheral hardware area

Note Either memory bank 0 or 1 can be selected as the stack area.

F80H

FFFH

Unimplemented

128 x 4

15

17

µ

PD75P0076

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s
operand representations (for further description, see the RA75X Assembler Package User’s Manual–Language (EEU-

1363)). When there are several codes, select and use just one. Uppercase letters, and + and – symbols are key words
that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for further description,

µ

see the

PD750068 User’s Manual (U10670E)). Labels that can be entered for fmem and pmem are restricted.

Representation Coding format
reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L
rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’
rp’1 BC, DE, HL, XA’, BC’, DE’, HL’
rpa HL, HL+, HL–, DE, DL
rpa1 DE, DL
n4 4-bit immediate data or label
n8 8-bit immediate data or label
mem 8-bit immediate data or label
bit 2-bit immediate data or label
fmem FB0H to FBFH, FF0H to FFFH immediate data or label
pmem FC0H to FFFH immediate data or label
addr 0000H to 3FFFH immediate data or label
addr1 000H to 3FFFH immediate data or label (in Mk II mode only)
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label
taddr 20H to 7FH immediate data (however, bit0 = 0) or label
PORTn PORT0 to PORT6, PORT11
IEXXX IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW
RBn RB0 to RB3
MBn MB0, MB1, MB15

Note

18

Note When processing 8-bit data, only even addresses can be specified.

(2) Operation legend

A : A register; 4-bit accumulator
B : B register
C : C register
D : D register
E : E register
H : H register
L : L register
X : X register
XA : Register pair (XA); 8-bit accumulator
BC : Register pair (BC)
DE : Register pair (DE)
HL : Register pair (HL)
XA’ : Expansion register pair (XA’)
BC’ : Expansion register pair (BC’)
DE’ : Expansion register pair (DE’)
HL’ : Expansion register pair (HL’)
PC : Program counter
SP : Stack pointer
CY : Carry flag; bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn : Port n (n = 0 to 6, 11)
IME : Interrupt master enable flag
IPS : Interrupt priority select register
IExxx : Interrupt enable flag
RBS : Register bank select register
MBS : Memory bank select register
PCC : Processor clock control register
. : Delimiter for address and bit
(xx) : Contents of address xx
xxH : Hexadecimal data

µ

PD75P0076

19

(3) Description of symbols used in addressing area

MB = MBE • MBS

*1

MBS = 0, 1, 15

MB = 0

*2

MBE = 0 :

*3

MBE = 1 :

MB = 15, fmem = FB0H to FBFH, FF0H to FFFH

*4

MB = 15, pmem = FC0H to FFFH

*5

addr = 0000H to 3FFFH

*6

addr, addr1 =*7 (Current PC) –15 to (Current PC) –1

*8 caddr =0000H to 0FFFH (PC

MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
MB = MBS
MBS = 0, 1, 15

(Current PC) +2 to (Current PC) +16

13, 12

= 00B) or

13, 12

13, 12

= 01B) or
= 10B) or

1000H to 1FFFH (PC
2000H to 2FFFH (PC

µ

PD75P0076

Data memory

addressing

Program memory

addressing

13, 12

3000H to 3FFFH (PC

faddr = 0000H to 07FFH

*9

taddr = 0020H to 007FH

*10

addr1 = 0000H to 3FFFH (Mk II mode only)

*11

= 11B)

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

20

µ

PD75P0076

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as
shown below.

• No skip .......................................................................... S = 0

• Skipped instruction is 1-byte or 2-byte instruction......... S = 1

Note

• Skipped instruction is 3-byte instruction

Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1

Caution The GETI instruction is skipped for one machine cycle.

................... S = 2

One machine cycle equals one cycle (= t

CY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.

21

µ

PD75P0076

Group Mnemonic Operand

Transfer MOV A, #n4 1 1 A ← n4 String-effect A

reg1, #n4 2 2 reg1 ← n4
XA, #n8 2 2 XA ← n8 String-effect A
HL, #n8 2 2 HL ← n8 String-effect B
rp2, #n8 2 2 rp2 ← n8
A, @HL 1 1 A ← (HL) *1
A, @HL+ 1 2 + S A ← (HL), then L ← L + 1 *1 L = 0
A, @HL– 1 2 + S A ← (HL), then L ← L – 1 *1 L = FH
A, @rpa1 1 1 A ← (rpa1) *2
XA, @HL 2 2 XA ← (HL) *1
@HL, A 1 1 (HL) ← A*1
@HL, XA 2 2 (HL) ← XA *1
A, mem 2 2 A ← (mem) *3
XA, mem 2 2 XA ← (mem) *3
mem, A 2 2 (mem) ← A*3
mem, XA 2 2 (mem) ← XA *3
A, reg1 2 2 A ← reg1
XA, rp’ 2 2 XA ← rp’
reg1, A 2 2 reg1 ← A
rp’1, XA 2 2 rp’1 ← XA

XCH A, @HL 1 1 A ↔ (HL) *1

A, @HL+ 1 2 + S A ↔ (HL), then L ← L + 1 *1 L = 0
A, @HL– 1 2 + S A ↔ (HL), then L ← L – 1 *1 L = FH
A, @rpa1 1 1 A ↔ (rpa1) *2
XA, @HL 2 2 XA ↔ (HL) *1
A, mem 2 2 A ↔ (mem) *3
XA, mem 2 2 XA ↔ (mem) *3
A, reg1 1 1 A ↔ reg1

XA, rp’ 2 2 XA ↔ rp’
Table MOVT XA, @PCDE 1 3 XA ← (PC13-8 + DE)ROM
reference XA, @PCXA 1 3 XA ← (PC13-8 + XA)ROM

XA, @BCDE 1 3 XA ← (BCDE)ROM

XA, @BCXA 1 3 XA ← (BCXA)ROM

No. of Machine

bytes cycle area

Operation

Note

Note

Addressing

*11
*11

Skip

condition

Note As for the B register, only the lower 2 bits are valid.

22

µ

PD75P0076

Group Mnemonic Operand

Bit transfer MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4

CY, pmem.@L 2 2 CY ← (pmem7-2 + L3-2.bit(L1-0)) *5
CY, @H + mem.bit
fmem.bit, CY 2 2 (fmem.bit) ← CY *4
pmem.@L, CY 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← CY *5
@H + mem.bit, CY

Operation ADDS A, #n4 1 1 + S A ← A + n4 carry

XA, #n8 2 2 + S XA ← XA + n8 carry
A, @HL 1 1 + S A ← A + (HL) *1 carry
XA, rp’ 2 2 + S XA ← XA + rp’ carry
rp’1, XA 2 2 + S rp’1 ← rp’1 + XA carry

ADDC A, @HL 1 1 A, CY ← A + (HL) + CY *1

XA, rp’ 2 2 XA, CY ← XA + rp’ + CY
rp’1, XA 2 2 rp’1, CY ← rp’1 + XA + CY

SUBS A, @HL 1 1 + S A ← A – (HL) *1 borrow

XA, rp’ 2 2 + S XA ← XA – rp’ borrow
rp’1, XA 2 2 + S rp’1 ← rp’1 – XA borrow

SUBC A, @HL 1 1 A, CY ← A – (HL) – CY *1

XA, rp’ 2 2 XA, CY ← XA – rp’ – CY
rp’1, XA 2 2 rp’1, CY ← rp’1 – XA – CY

AND A, #n4 2 2 A ← A^n4

A, @HL 1 1 A ← A^(HL) *1
XA, rp’ 2 2 XA ← XA^rp’
rp’1, XA 2 2 rp’1 ← rp’1^XA

OR A, #n4 2 2 A ← Avn4

A, @HL 1 1 A ← Av(HL) *1
XA, rp’ 2 2 XA ← XAvrp’
rp’1, XA 2 2 rp’1 ← rp’1vXA

XOR A, #n4 2 2 A ← Avn4

A, @HL 1 1 A ← Av(HL) *1
XA, rp’ 2 2 XA ← XAvrp’
rp’1, XA 2 2 rp’1 ← rp’1vXA

No. of Machine

bytes cycle area

2 2 CY ← (H + mem3-0.bit) *1

2 2 (H + mem3-0.bit) ← CY *1

Operation

Addressing

Skip

condition

23

µ

PD75P0076

Group Mnemonic Operand

Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An
manipulate NOT A 2 2 A ← A
Increment/ INCS reg 1 1 + S reg ← reg + 1 reg = 0
decrement rp1 1 1 + S rp1 ← rp1 + 1 rp1 = 00H

@HL 2 2 + S (HL) ← (HL) + 1 *1 (HL) = 0

mem 2 2 + S (mem) ← (mem) + 1 *3 (mem) = 0

DECS reg 1 1 + S reg ← reg – 1 reg = FH

rp’ 2 2 + S rp’ ← rp’ – 1 rp’ = FFH
Compare SKE reg, #n4 2 2 + S Skip if reg = n4 reg = n4

@HL, #n4 2 2 + S Skip if (HL) = n4 *1 (HL) = n4

A, @HL 1 1 + S Skip if A = (HL) *1 A = (HL)

XA, @HL 2 2 + S Skip if XA = (HL) *1 XA = (HL)

A, reg 2 2 + S Skip if A = reg A = reg

XA, rp’ 2 2 + S Skip if XA = rp’ XA = rp’
Carry flag SET1 CY 1 1 CY ← 1
manipulate CLR1 CY 1 1 CY ← 0

SKT CY 1 1 + S Skip if CY = 1 CY = 1
NOT1 CY 1 1 CY ← CY

No. of Machine

bytes cycle area

Operation

Addressing

Skip

condition

24

µ

PD75P0076

Group Mnemonic Operand

Memory bit SET1 mem.bit 2 2 (mem.bit) ← 1*3
manipulate fmem.bit 2 2 (fmem.bit) ← 1*4

pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 1*5
@H + mem.bit 2 2 (H + mem3-0.bit) ← 1*1

CLR1 mem.bit 2 2 (mem.bit) ← 0*3

fmem.bit 2 2 (fmem.bit) ← 0*4
pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 0*5
@H + mem.bit 2 2 (H + mem3-0.bit) ← 0*1

SKT mem.bit 2 2 + S Skip if(mem.bit) = 1 *3 (mem.bit) = 1

fmem.bit 2 2 + S Skip if(fmem.bit) = 1 *4 (fmem.bit) = 1
pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 *5 (pmem.@L) = 1
@H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 1 *1

SKF mem.bit 2 2 + S Skip if(mem.bit) = 0 *3 (mem.bit) = 0

fmem.bit 2 2 + S Skip if(fmem.bit) = 0 *4 (fmem.bit) = 0
pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 0 *5 (pmem.@L) = 0
@H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 0 *1

SKTCLR fmem.bit 2 2 + S Skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1

pmem.@L 2 2 + S
@H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 1 and clear *1

AND1 CY, fmem.bit 2 2 CY ← CY^(fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY^(pmem7-2 + L3-2.bit(L1-0)) *5
CY, @H + mem.bit 2 2 CY ← CY^(H + mem3-0.bit) *1

OR1 CY, fmem.bit 2 2 CY ← CYv(fmem.bit) *4

CY, pmem.@L 2 2 CY ← CYv(pmem7-2 + L3-2.bit(L1-0)) *5
CY, @H + mem.bit 2 2 CY ← CYv(H + mem3-0.bit) *1

XOR1 CY, fmem.bit 2 2 CY ← CYv(fmem.bit) *4

CY, pmem.@L 2 2 CY ← CYv(pmem7-2 + L3-2.bit(L1-0)) *5
CY, @H + mem.bit 2 2 CY ← CYv(H + mem3-0.bit) *1

No. of Machine

bytes cycle area

Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 and clear

Operation

Addressing

*5 (pmem.@L) = 1

Skip

condition

(@H+mem.bit) = 1

(@H+mem.bit) = 0

(@H+mem.bit) = 1

25

µ

PD75P0076

Group Mnemonic Operand

Branch BR

Note 1

BRA
BRCB !caddr 2 2 PC13-0 ← PC13, 12 + caddr11-0 *8

addr — — PC13-0 ← addr *6

addr1 — — PC13-0 ← addr1 *11

!addr 3 3 PC13-0 ← addr *6

$addr 1 2 PC13-0 ← addr *7

$addr1 1 2 PC13-0 ← addr1

PCDE 2 3 PC13-0 ← PC13-8 + DE

PCXA 2 3 PC13-0 ← PC13-8 + XA

BCDE 2 3 PC13-0 ← BCDE

BCXA 2 3 PC13-0 ← BCXA

Note 1

!addr1 3 3 PC13-0 ← addr1 *11

No. of Machine

bytes cycle area

Assembler selects the most
appropriate instruction among
the following:

• BR !addr

• BRCB !caddr

• BR $addr

Assembler selects the most
appropriate instruction among
the following:

• BRA !addr1

• BR !addr

• BRCB !caddr

• BR $addr1

Operation

Note 2

Note 2

Addressing

*6
*6

Skip

condition

Notes 1. Double boxes indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

2. As for the B register, only the lower 2 bits are valid.

26

µ

PD75P0076

Group Mnemonic Operand

Subroutine CALLA

Note

!addr1 3 3 (SP – 6)(SP – 3)(SP – 4) ← PC11-0 *11

No. of Machine

bytes cycle area

Operation

stack control (SP – 5) ← 0, 0, PC13,12

(SP – 2) ← X, X, MBE, RBE
PC13-0 ← addr1, SP ← SP – 6

Note

CALL

!addr 3 3 (SP – 4)(SP – 1)(SP – 2) ← PC11-0 *6

(SP – 3) ← MBE, RBE, PC13, 12
PC13-0 ← addr, SP ← SP – 4

4 (SP – 6)(SP – 3)(SP – 4) ← PC11-0

(SP – 5) ← 0, 0, PC13, 12
(SP – 2) ← X, X, MBE, RBE
PC13-0 ← addr, SP ← SP – 6

Note

CALLF

!faddr 2 2 (SP – 4)(SP – 1)(SP – 2) ← PC11-0 *9

(SP – 3) ← MBE, RBE, PC13, 12
PC13-0 ← 000 + faddr, SP ← SP – 4

3 (SP – 6)(SP – 3)(SP – 4) ← PC11-0

(SP – 5) ← 0, 0, PC13, 12
(SP – 2) ← X, X, MBE, RBE
PC13-0 ← 000 + faddr, SP ← SP – 6

Note

RET

1 3 MBE, RBE, PC13, 12 ← (SP + 1)

PC11-0 → (SP)(SP + 3)(SP + 2)
SP ← SP + 4
X, X, MBE, RBE ← (SP + 4)
PC11-0 ← (SP)(SP + 3)(SP + 2)
0, 0, PC13, 12 ← (SP + 1)
SP ← SP + 6

Note

RETS

1 3 + S MBE, RBE, PC13, 12 ← (SP + 1) Unconditional

PC11-0 ← (SP)(SP + 3)(SP + 2)
SP ← SP + 4
then skip unconditionally
X, X, MBE, RBE ← (SP + 4)
PC11-0 ← (SP)(SP + 3)(SP + 2)
0, 0, PC13, 12 ← (SP + 1)
SP ← SP + 6
then skip unconditionally

RETI 1 3 MBE, RBE, PC13, 12 ← (SP + 1)

PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6
0, 0, PC13, 12 ← SP + 1
PC11-0 ← (SP)(SP + 3)(SP + 2)
PSW ← (SP + 4)(SP + 5), SP ← SP + 6

Addressing

Skip

condition

Note Double boxes indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

27

µ

PD75P0076

Group Mnemonic Operand

No. of Machine

bytes cycle area

Operation

Subroutine PUSH rp 1 1 (SP – 1)(SP – 2) ← rp, SP ← SP – 2
stack control BS 2 2

(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2

POP rp 1 1 rp ← (SP + 1)(SP), SP ← SP + 2

BS 2 2

MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2
Interrupt EI 2 2 IME(IPS.3) ← 1
control IEXXX 2 2 IEXXX ← 1

DI 2 2 IME(IPS.3) ← 0

IEXXX 2 2 IEXXX ← 0

I/O IN

Note 1

A, PORTn 2 2 A ← PORTn (n = 0 to 6, 11)
XA, PORTn 2 2 XA ← PORTn + 1, PORTn(n = 4)

Note 1

OUT

PORTn, A 2 2 PORTn ← A (n = 2 to 6)
PORTn, XA 2 2 PORTn + 1, PORTn ← XA(n = 4)

CPU control HALT 2 2 Set HALT Mode (PCC.2 ← 1)

STOP 2 2 Set STOP Mode (PCC.3 ← 1)
NOP 1 1 No Operation

Special SEL RBn 2 2 RBS ← n (n = 0 to 3)

MBn 2 2 MBS ← n (n = 0, 1, 15)

Note 2, 3

GETI

taddr 1 3 • When using TBR instruction *10

PC13-0 ← (taddr)5-0 + (taddr + 1)

- - - - - - - - - - - - - - - - - - - - - - - - -

• When using TCALL instruction

(SP – 4)(SP – 1)(SP – 2) ← PC11-0

(SP – 3) ← MBE, RBE, PC13, 12

PC13-0 ← (taddr)5-0 + (taddr + 1)

SP ← SP – 4

- - - - - - - - - - - - - - - - - - - - - - - - -

• When using instruction other than Determined by

TBR or TCALL referenced

Execute (taddr)(taddr + 1) instructions instruction

1 3 • When using TBR instruction *10

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

PC13-0 ← (taddr)5-0 + (taddr + 1)

4 • When using TCALL instruction

(SP – 6)(SP – 3)(SP – 4) ← PC11-0

(SP – 5) ← 0, 0, PC13, 12

(SP – 2) ← X, X, MBE, RBE

PC13-0 ← (taddr)5-0 + (taddr + 1)

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

SP ← SP – 6

3 • When using instruction other than Determined by

TBR or TCALL referenced

Execute (taddr)(taddr + 1) instructions instruction

Addressing

Skip

condition

- - - - - - - - - - -

- - - - - - - - - - -

- - - - - - - - - - -

- - - - - - - - - - -

Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.

2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction’s table definitions.

3. Double box indicates support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

28

µ

PD75P0076

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory in the µPD75P0076 is a 16384 x 8-bit electronic write-enabled one-time PROM. The pins listed
in the table below are used for this PROM’s write/verify operations. Clock input from the X1 pins is used instead of address
input as a method for updating addresses.

Pin name Function

VPP Pin (usually VDD) where programming voltage is applied during

X1, X2 Clock input pin for address updating during program memory

MD0 to MD3 Operation mode selection pin for program memory write/verify
D0/P40 to D3/P43 (lower 4)

D4/P50 to D7/P53 (upper 4)
VDD Pin where power supply voltage is applied. Power voltage

Caution Pins not used for program memory write/verify should be handled as follows.

• All unused pins except XT2 ......Connect to Vss via a pull-down resistor

• XT2 pin ........................................Leave open

program memory write/verify

write/verify. Input the X1 pin’s inverted signal to the X2 pin.

8-bit data I/O pin for program memory write/verify

range for normal operation is 1.8 to 5.5 V. Apply 6 V for program
memory write/verify.

8.1 Operation Modes for Program Memory Write/Verify

µ

When +6 V is applied to the

PD75P0076’s VDD pin and +12.5 V is applied to its VPP pin, program memory write/verify
modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3
as shown below.

Operation mode specification Operation mode
VPP VDD MD0 MD1 MD2 MD3
+12.5 V +6 V H L H L Zero-clear program memory address

L H H H Write mode
L L H H Verify mode
H X H H Program inhibit mode

X: L or H

29

8.2 Steps in Program Memory Write Operation

High-speed program memory write can be executed via the following steps.

SS

(1) Pull down unused pins to V

via resistors. Set the X1 pin to low.
(2) Apply +5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Zero-clear mode for program memory addresses.
(5) Apply +6 V to V

DD and +12.5 V to VPP.

(6) Write data using 1-ms write mode.
(7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) to (7).
(8) X [= number of write operations from steps (6) to (7)] x 1 ms additional write
(9) 4 pulse inputs to the X1 pin updates (increments +1) the program memory address.
(10) Repeat steps (6) to (9) until the last address is completed.
(11) Zero-clear mode for program memory addresses.
(12) Apply +5 V to the V

DD and VPP pins.

(13) Power supply OFF

The following diagram illustrates steps (2) to (9).

µ

PD75P0076

VPP

VPP

VDD

VDD + 1

VDD

V

X1

D0/P40-D3/P43
D4/P50-D7/P53

MD0/P30

MD1/P31

DD

X repetitions

Write Verify

Data input

Data output

Additional

write

Data input

Address

increment

30

MD2/P32

MD3/P33

µ

PD75P0076

8.3 Steps in Program Memory Read Operation

The µPD75P0076 can read out the program memory contents via the following steps.

SS

(1) Pull down unused pins to V

via resistors. Set the X1 pin to low.
(2) Apply +5 V to the VDD and VPP pins.
(3) Wait 10 µs.
(4) Zero-clear mode for program memory addresses.
(5) Apply +6 V to V

DD and +12.5 V to VPP.

(6) Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based

on a cycle of four pulse inputs.
(7) Zero-clear mode for program memory addresses.
(8) Apply +5 V to the V

DD and VPP pins.

(9) Power supply OFF

The following diagram illustrates steps (2) to (7).

VPP

VPP

VDD

VDD + 1

VDD

V

DD

X1

D0/P40-D3/P43
D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

Data output Data output

“L”

MD3/P33

31

µ

PD75P0076

8.4 One-Time PROM Screening

Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
the screening process, that is, after the required data is written to the PROM and the PROM is stored under the high­temperature conditions shown below, the PROM should be verified.

Storage temperature Storage time

125 ˚C 24 hours

32

µ

PD75P0076

9. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (TA = 25˚C)

Parameter Symbol Test Conditions Rating Unit
Power supply voltage VDD –0.3 to +7.0 V
PROM power supply VPP –0.3 to +13.5 V

voltage
Input voltage VI1 Except ports 4, 5 –0.3 to VDD +0.3 V

VI2 Ports 4, 5 (N-ch open drain) –0.3 to +14 V
Output voltage VO –0.3 to VDD +0.3 V
Output current high IOH Per pin –10 mA

Total of all pins –30 mA

Output current low IOL Per pin 30 mA

Total of all pins 220 mA

Operating ambient TA –40 to +85 ˚ C
temperature

Storage temperature Tstg –65 to +150 ˚ C

Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the reliability of the

product may be impaired. The absolute maximum ratings are values that may physically damage the
products. Be sure to use the products within the ratings.

CAPACITANCE (T

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input capacitance CIN f = 1 MHz 15 pF
Output capacitance COUT
I/O capacitance CIO 15 pF

A = 25˚C,VDD = 0 V)

Unmeasured pins returned to 0 V.

15 pF

33

µ

PD75P0076

MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator Recommended constant Parameter Test conditions MIN. TYP. MAX. Unit
Ceramic Oscillation 1.0

X1

resonator frequency (fx)

C1

Crystal Oscillation 1.0

X1

resonator frequency (fx)

C1

X2

X2

C2

C2

Note 1

Oscillation After VDD reaches oscil- 4 ms

Note 1

Note 3

lation voltage range MIN.

stabilization time

Oscillation VDD = 4.5 to 5.5 V 10 ms
stabilization time

Note 3

External X1 input 1.0
clock frequency (fx)

X1

X2

Note 1

X1 input 83.3 500 ns
high-/low-level width
(tXH, tXL)

6.0

6.0

6.0

Note 2

Note 2

30

Note 2

MHz

MHz

MHz

Notes 1. The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For the

instruction execution time, refer to AC Characteristics.

2. When the power supply voltage is 1.8 V ≤ V

DD < 2.7 V and the oscillation frequency is 4.19 MHz < fx ≤ 6.0 MHz,

setting the processor clock control register (PCC) to 0011 results in 1 machine cycle being less than the required

µ

s. Therefore, set PCC to a value other than 0011.

0.95

3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP
mode.

Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line should

be carried out as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

SS.

• Do not ground it to the ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

34

µ

PD75P0076

SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Resonator Recommended constant Parameter Test conditions MIN. TYP. MAX. Unit
Crystal Oscillation 32 32.768 35 kHz
resonator frequency (fXT)

External XT1 input frequency 32 100 kHz
clock (fXT)

XT1

C3

XT1

XT2

XT2

R

C4

Oscillation VDD = 4.5 to 5.5 V 1.0 2 s
stabilization time

Note 1

XT1 input high-/low-level
width (tXTH, tXTL)

Note 1

Note 2

515

10

µ

s

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. The oscillation stabilization time is necessary for oscillation to stabilize after applying V

DD.

Caution When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should

be carried out as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

SS.

• Do not ground it to the ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption

current, causing misoperation by noise more frequently than the main system clock oscillation
circuit. Special care should therefore be taken for wiring method when the subsystem clock is used.

35

RECOMMENDED OSCILLATION CIRCUIT CONSTANTS

µ

PD75P0076

CERAMIC RESONATOR (T

Manufacturer Product Name

Murata Mfg. CSB1000J
Co., Ltd. CSA2.00MG040 2.0 100 100 2.0 —

CST2.00MG040 — — With on-chip capacitor
CSA4.00MG 4.0 30 30 1.8 —
CST4.00MGW — — With on-chip capacitor
CSA4.19MG 4.19 30 30 —
CST4.19MGW — — With on-chip capacitor
CSA6.00MG 6.0 30 30 2.6 —
CST6.00MGW — — With on-chip capacitor
CSA6.00MGU 30 30 1.8 —
CST6.00MGWU — — With on-chip capacitor

A = –20 to +80 ˚C)

Frequency

(MHz)

Note

1.0 100 100 2.2 5.5 Rd = 5.6 KΩ

Oscillation Circuit Oscillation Voltage
Constants (pF) Range (VDD)

C1 C2 MIN. MAX.

Remarks

Note When the CSB1000J (1.0 MHz) manufactured by Murata Mfg. is used as a ceramic resonator, a limiting resistor

(Rd = 5.6 kΩ) is required (see the figure below). Other recommended resonators do not require such a limiting
resistor.

X1

CSB1000J

C1

X2

Rd

C2

Caution The oscillation circuit constants and oscillation voltage range only indicate the conditions under which

the circuit can oscillate stably, and do not guarantee the oscillation frequency accuracy. If oscillation
frequency accuracy is required in the actual circuit, it is necessary to adjust oscillation frequencies in
the actual circuit, and you should consult directly with the manufacturer of the resonator used.

36

µ

PD75P0076

DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Output current low IOL Per pin 15 mA

Total of all pins 150 mA

Input voltage high VIH1 Ports 2, 3, and 11 2.7 ≤ VDD ≤ 5.5 V 0.7VDD VDD V

1.8 ≤ VDD < 2.7 V 0.9VDD VDD V

VIH2 Ports 0, 1, 6, RESET 2.7 ≤ VDD ≤ 5.5 V 0.8VDD VDD V

1.8 ≤ VDD < 2.7 V 0.9VDD VDD V

VIH3 Ports 4, 5 2.7 ≤ VDD ≤ 5.5 V 0.7VDD 13 V

(N-ch open-drain) 1.8 ≤ VDD < 2.7 V 0.9VDD 13 V

VIH4 X1, XT1

Input voltage low VIL1 Ports 2-5, 11 2.7 ≤ VDD ≤ 5.5 V 0 0.3VDD V

1.8 ≤ VDD < 2.7 V 0 0.1VDD V

VIL2 Ports 0, 1, 6, RESET 2.7 ≤ VDD ≤ 5.5 V 0 0.2VDD V

1.8 ≤ VDD < 2.7 V 0 0.1VDD V

VIL3 X1, XT1 0 0.1 V
Output voltage high VOH
Output voltage low VOL1

VOL2 SB0, SB1 When N-ch open-drain 0.2VDD V

Input leakage ILIH1 VIN = VDD Pins other than X1, XT1 3
current high ILIH2 X1, XT1 20

ILIH3 VIN = 13 V Ports 4, 5 (N-ch open-drain) 20
Input leakage ILIL1 VIN = 0 V Ports 4, 5, pins other than X1, XT1 –3
current low ILIL2 X1, XT1 –20

SCK, SO, Ports 2, 3, 6 IOH = –1.0 mA
SCK, SO, Ports 2-6

pull-up resistor ≥ 1 kΩ

Ports 4, 5 (N-ch open-drain) –3
When input instruction is not executed

IOL = 15 mA, 0.2 2.0 V
VDD =

4.5 to 5.5 V

IOL = 1.6 mA 0.4 V

VDD – 0.1

VDD – 0.5

VDD V

V

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

ILIL3 Ports 4, 5 (N-ch open- –30

drain) When input VDD =

instruction is executed VDD =
Output leakage ILOH1 VOUT = VDD SCK, SO/SB0, SB1, Ports 2, 3, 6 3
current high ILOH2 VOUT = 13 V Ports 4, 5 (N-ch open-drain) 20
Output leakage ILOL VOUT = 0 V –3

current low
On-chip pull-up resistor RL VIN = 0 V Ports 0-3, 6 (Excluding P00 pin) 50 100 200 kΩ

5.0 V

3.0 V

–10 –27

–3 –8

µ
µ
µ
µ
µ
µ

A
A
A
A
A
A

37

DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Supply current

Note 1

IDD1 6.0 MHz

Crystal oscillation

Note 2

VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%

Note 3

Note 4

µ

PD75P0076

3.4 10.2 mA

0.8 2.4 mA

IDD2

IDD1 4.19 MHz

IDD2

IDD3 32.768 kHz

C1 = C2 = 22 pF

Note 2

Crystal oscillation
C1 = C2 = 22 pF

Note 5

Crystal oscillation

HALT mode VDD = 5.0 V ± 10% 0.9 2.7 mA

VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
HALT mode VDD = 5.0 V ± 10% 0.8 2.4 mA

Low-voltage VDD = 3.0 V ± 10% 42 126

Note 6

mode

Low current con­sumption mode

Note 7

IDD4 HALT mode Low-

VDD = 3.0 V ± 10% 0.5 1.5 mA

Note 3

Note 4

2.7 7.4 mA

0.6 1.8 mA

VDD = 3.0 V ± 10% 0.4 1.2 mA

VDD = 2.0 V ± 10% 23 69
VDD = 3.0 V, TA = 25˚C

42 84
VDD = 3.0 V ± 10% 40 120
VDD = 3.0 V, TA = 25˚C

VDD = 3.0 V ± 10%
voltage
mode
Low current
consumption
mode

VDD = 2.0 V ± 10%

Note 6

VDD = 3.0 V, T

VDD = 3.0 V ± 10%

VDD = 3.0 V,

Note 7

TA = 25˚C

A

= 25˚C

40 80

824
412
816
721
714

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

IDD5 XT1 = 0 V VDD = 5.0 V ± 10% 0.05 10

STOP mode

Note 8

VDD = 3.0 V 0.02 5.0
± 10% TA = 25˚C 0.02 3.0

Notes 1. Not including currents flowing in on-chip pull-up resistors.

2. Including oscillation of the subsystem clock.

3. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-speed

mode.

4. When PCC is set to 0000 and the device is operated in the low-speed mode.

5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock,

with main system clock oscillation stopped.

6. When the sub-oscillation circuit control register (SOS) is set to 0000.

7. When SOS is set to 0010.

8. When SOS is set to 00×1, the feedback resistors of the sub-oscillation circuit is cutoff. (×: don’t care)

µ

A

µ

A

µ

A

38

µ

PD75P0076

AC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

CPU clock cycle tCY Operating on VDD = 2.7 to 5.5 V 0.67 64

Note 1

time
(Minimum instruction execution
time = 1 machine cycle) subsystem clock
TI0, TI1 input fTI VDD = 2.7 to 5.5 V 0 1.0 MHz
frequency 0 275 kHz
TI0, TI1 input tTIH, tTIL VDD = 2.7 to 5.5 V 0.48
high-/low-level width 1.8
Interrupt input high-/
low-level width IM02 = 1 10

RESET low-level width tRSL 10

tINTH, tINTL

Notes 1. The cycle time (minimum instruction

execution time) of the CPU clock (Φ)
is determined by the oscillation
frequency of the connected resonator

main system clock 0.95 64
Operating on 114 122 125

INT0 IM02 = 0 Note 2

INT1, 2, 4 10
KR0 to KR3 10

t

CY vs VDD

(At main system clock operation)

64
60

(and external clock), the system clock
control register (SCC) and the
processor clock control register
(PCC). The figure at the right
indicates the cycle time t
supply voltage V

DD characteristic with

CY versus

the main system clock operating.

2. 2tCY or 128/fx is set by setting the

6
5

µ

4
3

2

Cycle Time tCY [ s]

Guaranteed Operation
Range

interrupt mode register (IM0).

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

0.5

1

1023456

Supply Voltage V

DD [V]

39

SERIAL TRANSFER OPERATION

µ

PD75P0076

2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (T

A = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY1 VDD = 2.7 to 5.5 V 1300 ns

3800 ns
SCK high-/low-level tKL1, tKH1 VDD = 2.7 to 5.5 V
width

Note 1

SI

setup time t SIK1 VDD = 2.7 to 5.5 V 150 ns

tKCY1/2–50

tKCY1/2–150

(to SCK↑) 500 ns

Note 1

SI

hold time tKSI1 VDD = 2.7 to 5.5 V 400 ns
(from SCK↑) 600 ns
SCK↓→SO
delay time CL = 100 pF

Note 1

output tKSO1 RL = 1 kΩ,VDD = 2.7 to 5.5 V 0 250 ns

Note 2

0 1000 ns

Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.

L and CL are the load resistance and load capacitance of the SO output lines.

2. R

2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (T

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY2 VDD = 2.7 to 5.5 V 800 ns

A = –40 to +85˚C, VDD = 1.8 to 5.5 V)

ns
ns

3200 ns
SCK high-/low-level tKL2, tKH2 VDD = 2.7 to 5.5 V 400 ns
width 1600 ns

Note 1

SI

setup time t SIK2 VDD = 2.7 to 5.5 V 100 ns

(to SCK↑) 150 ns

Note 1

SI

hold time tKSI2 VDD = 2.7 to 5.5 V 400 ns
(from SCK↑) 600 ns
SCK↓→SO
delay time CL = 100 pF

Note 1

output tKSO2 RL = 1 kΩ,VDD = 2.7 to 5.5 V 0 300 ns

Note 2

0 1000 ns

Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.

2. RL and CL are the load resistance and load capacitance of the SO output lines.

40

µ

PD75P0076

A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V, 1.8 V ≤ AVREF ≤ VDD)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Resolution 8 8 8 bit

Note 3

Note 2

Note 1

VDD = AVREF 2.7 ≤ VDD 1.5 LSB

1.8 V ≤ VDD < 2.7 V 3 LSB

VDD ≠ AVREF 3 LSB
tCONV 168/fXµs
tSAMP 44/fXµs

Absolute accuracy

Conversion time
Sampling time
Analog input voltage VIAN AVSS AVREF V
Analog input impedance RAN 1000 MΩ
AVREF current IREF 0.25 2.0 mA

Notes 1. Absolute accuracy excluding quantization error (±1/2 LSB).

µ

2. Time after execution of conversion start instruction until completion of conversion (EOC = 1) (40.1

s: in fX =

4.19 MHz operation)

3. Time after conversion start instruction until completion of sampling (10.5 µs: in fX = 4.19 MHz operation)

41

AC Timing Test Point (Excluding X1, XT1 Input)

µ

PD75P0076

Clock Timing

X1 Input

V

IH
IL

V

V

OH
OL

V

(MIN.)
(MAX.)

(MIN.)

(MAX.)

V

IH

(MIN.)

IL

(MAX.)

V

V

OH

(MIN.)

OL

(MAX.)

V

1/f

X

t

XL

t

XH

V

DD

–0.1 V

0.1 V

XT

1/f

XT1 Input

TI0, TI1 Timing

TI0, TI1

tXTL

tTIL

1/fTI

tXTH

tTIH

V

DD–0.1 V

0.1 V

42

Serial Transfer Timing

3-wire serial I/O mode

SCK

t

KL1, 2

t

SIK1, 2

t

KCY1, 2

t

KSI1, 2

t

KH1, 2

µ

PD75P0076

SI

SO

2-wire serial I/O mode

SCK

SB0, 1

t

KSO1, 2

Input Data

t

KL1, 2

t

SIK1, 2

Output Data

t

KCY1, 2

t

KH1, 2

t

KSI1, 2

t

KSO1, 2

43

Interrupt input timing

INT0, 1, 2, 4

KR0 to 3

RESET input timing

RESET

t

INTL

t

RSL

t

INTH

µ

PD75P0076

44

µ

PD75P0076

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS

(TA = –40 to +85˚C)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit
Release signal set time tSREL 0
Oscillation stabilization tWAIT Release by RESET
wait time

Note 1

Release by interrupt request

215/f

Note 2

X

µ

ms
ms

s

Notes 1. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable

operation at the oscillation start.

2. Depends on the basic interval timer mode register (BTM) settings (See the table below).

BTM3 BTM2 BTM1 BTM0 Wait time

fx = at 4.19 MHz fx = at 6.0 MHz
—0002
—0112
—1012
—1112

20

/fx (approx. 250 ms) 220/fx (approx. 175 ms)

17

/fx (approx. 31.3 ms) 217/fx (approx. 21.8 ms)

15

/fx (approx. 7.81 ms) 215/fx (approx. 5.46 ms)

13

/fx (approx. 1.95 ms) 213/fx (approx. 1.37 ms)

45

Data Retention Timing (STOP Mode Release by RESET)

Internal Reset Operation

HALT Mode

STOP Mode

Data Retention Mode

V

DD

V

DDDR

t

SREL

STOP Instruction Execution

RESET

t

WAIT

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

µ

PD75P0076

Operating Mode

V

DD

STOP Instruction Execution

Standby Release Signal
(Interrupt Request)

STOP Mode

Data Retention Mode

V

DDDR

t

SREL

HALT Mode

t

WAIT

Operating Mode

46

µ

PD75P0076

DC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5˚C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Input voltage high VIH1 Except X1, X2 0.7VDD VDD V

VIH2 X1, X2 VDD–0.5 VDD V

Input voltage low VIL1 Except X1, X2 0 0.3VDD V

VIL2 X1, X2 0 0.4 V
Input leakage current ILI VIN = VIL or VIH 10
Output voltage high VOH IOH = –1 mA VDD–1.0 V
Output voltage low VOL IOL = 1.6 mA 0.4 V
VDD power supply current IDD 30 mA
VPP power supply current IPP MD0 = VIL, MD1 = VIH 30 mA

µ

A

Cautions 1. Avoid exceeding +13.5 V for VPP including the overshoot.

DD must be applied before VPP, and cut after VPP.

2. V

AC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5˚C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)

Parameter Symbol Note 1 Test conditions MIN. TYP. MAX. Unit
Address setup time
MD1 setup time (to MD0↓)tM1S tOES 2
Data setup time (to MD0↓)tDS tDS 2
Address hold time
Data hold time (from MD0↑)tDH tDH 2
MD0↑→data output float delay time tDF tDF 0 130 ns
VPP setup time (to MD3↑)tVPS tVPS 2
VDD setup time (to MD3↑)tVDS tVCS 2
Initial program pulse width tPW tPW 0.95 1.0 1.05 ms
Additional program pulse width tOPW tOPW 0.95 21.0 ms
MD0 setup time (to MD1↑)tM0S tCES 2
MD0↓→data output delay time tDV tDV MD0 = MD1 = VIL 1
MD1 hold time (from MD0↑)tM1H tOEH tM1H + tM1R ≥ 50 µs2
MD1 recovery time (from MD0↓)tM1R tOR 2
Program counter reset time tPCR –10
X1 input high-/low-level width tXH, tXL – 0.125
X1 input frequency fX – 4.19 MHz
Initial mode set time tI –2
MD3 setup time (to MD1↑)tM3S –2
MD3 hold time (from MD1↓)tM3H –2
MD3 setup time (to MD0↓)tM3SR –
Address
Address
MD3 hold time (from MD0↑)tM3HR –
MD3↓→data output float delay time tDFR –

Note 2

Note 2

Note 2

(to MD0↓)tAS tAS 2

Note 2

(from MD0↑)tAH tAH 2

→data output delay time

→data output hold time

tDAD tACC
tHAD tOH

During program memory read
During program memory read
During program memory read
During program memory read
During program memory read

2

0 130 ns
2

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

2

2

µ

s

µ

s

µ

s

Notes1. Corresponding symbol of µPD27C256A

2. The internal address signal is incremented by 1 at the rising edge of the fourth X1 input and is not

connected to the pin.

47

Program Memory Write Timing

t

VPS

V

PP

V

PP

V

DD

t

VDS

VDD+1

V

DD

V

DD

X1

D0/P40-D3/P43
D4/P50-D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

t

I

t

PCR

t

M3S

Data input

t

DS

t

t

M1S

µ

PD75P0076

t

XH

t

Data output

t

DH

PW

t

M1H

t

DVtDF

t

M1R

t

M0S

Data input

t

DS

t

OPW

XL

t

DH

t

AH

Data input

t

AS

t

M3H

Program Memory Read Timing

V

PP

V

PP

V

DD

VDD+1

V

DD

V

DD

X1

D0/P40-D3/P43
D4/P50-D7/P53

t

I

MD0/P30

MD1/P31

t

PCR

MD2/P32

t

VPS

t

VDS

t

XH

t

t

XL

t

HAD

DAD

Data output Data output

t

DV

t

M3HR

t

DFR

48

MD3/P33

t

M3SR

10. CHARACTERISTICS CURVES (REFERENCE VALUES)

IDD vs VDD(Main System Clock: 6.0-MHz Crystal Resonator)

10

5.0

1.0

0.5

µ

PD75P0076

(T

A

= 25°C)

PCC = 0011

PCC = 0010
PCC = 0001
PCC = 0000

Main system clock
HALT mode + 32-kHz oscillation

(mA)

DD

0.1

Supply Current I

0.05

0.01

0.005

Subsystem clock operation
mode (SOS.1 = 0)

Subsystem clock HALT
mode (SOS.1 = 0) and
main system clock STOP mode
+ 32-kHz oscillation
(SOS.1 = 0)

Subsystem clock HALT mode
(SOS.1 = 1) and main
system clock STOP mode
+ 32-kHz oscillation
(SOS.1 = 1)

XT1 XT2X1 X2

Crystal resonator

6.0 MHz

Crystal resonator

32.768 kHz

330 kΩ

22 pF 22 pF 33 pF 33 pF

0.001
012345678

DD

Supply Voltage V

(V)

49

10

5.0

IDD vs VDD (Main System Clock: 4.19-MHz Crystal Resonator)

PCC = 0011

PCC = 0010

µ

PD75P0076

(T

A

= 25°C)

1.0

0.5

(mA)

DD

0.1

Supply Current I

0.05

0.01

PCC = 0001
PCC = 0000

Main system clock
HALT mode + 32-kHz oscillation

Subsystem clock operation
mode (SOS.1 = 0)

Subsystem clock HALT mode
(SOS.1 = 0) and main sysyem
clock STOP mode + 32-kHz
oscillation (SOS.1 = 0)

Subsystem clock HALT
mode (SOS.1 = 1) and

main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 1)

50

0.005

XT1 XT2X1 X2

Crystal resonator

4.19 MHz

22 pF 22 pF 33 pF 33 pF

0.001
012345678

Supply Voltage VDD (V)

Crystal resonator

32.768 kHz

330 kΩ

11. PACKAGE DRAWINGS

42PIN PLASTIC SHRINK DIP (600 mil)

µ

PD75P0076

42

1

22

21

A

K

L

I

J

H

G

F

D

M

N

B

C

M

R

NOTES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

2) Item "K" to center of leads when formed parallel.

ITEM MILLIMETERS INCHES

A

39.13 MAX.

B

1.78 MAX.

C

1.778 (T.P.)
D 0.50±0.10 0.020
F

0.9 MIN.
G

3.2±0.3
H

0.51 MIN.

I

4.31 MAX.
J

5.08 MAX.
K

15.24 (T.P.)
L 13.2 0.520

M 0.25
N

R

+0.10
–0.05

0.17
0~15° 0~15°

1.541 MAX.

0.070 MAX.

0.070 (T.P.)
+0.004

–0.005

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.600 (T.P.)

+0.004

0.010

–0.003

0.007

P42C-70-600A-1

51

42 PIN PLASTIC SHRINK SOP (375 mil)

42 22

detail of lead end

–3°

+7°

3°

µ

PD75P0076

121

A

G

F

E

C

D

M

M

N

NOTE

Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.

H

I

K

B

L

S42GT-80-375B-1

ITEM MILLIMETERS INCHES

A

B
C
D

E

F
G
H

I

J
K

L
M
N

18.16 MAX.

1.13 MAX.

0.8 (T.P.)

+0.10

0.35

–0.05

0.125±0.075

2.9 MAX.

2.5±0.2

10.3±0.3

7.15±0.2

1.6±0.2

+0.10

0.15

–0.05

0.8±0.2

0.10

0.10 0.004

0.715 MAX.

0.044 MAX.

0.031 (T.P.)

+0.004

0.014

–0.003

0.005±0.003

0.115 MAX.

+0.009

0.098

–0.008
+0.012

0.406

–0.013
+0.009

0.281

–0.008

0.063±0.008

+0.004

0.006

–0.002
+0.009

0.031

–0.008

0.004

J

52

µ

PD75P0076

12. RECOMMENDED SOLDERING CONDITIONS

The µPD75P0076 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document “Semiconductor Device

Mounting Technology Manual” (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC Sales representative.

Table 12-1. Surface Mounting Type Soldering Conditions

µ

PD75P0076GT: 42-pin plastic shrink SOP (375 mil, 0.8 mm pitch)

Soldering

Method

Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds or less (at 210˚C or higher), IR35-00-2

Number of reflow processes: Twice or less

VPS Package peak temperature: 215˚C, Time: 40 seconds or less (at 200˚C or higher), VP15-00-2

Number of reflow processes: Twice or less

Wave soldering Solder temperature: 260˚C or below, Time: 10 seconds or less, Number of flow WS60-00-1

process: 1, Preheating temperature: 120˚C or below (Package surface temperature)

Partial heating Pin temperature: 300˚C or below, Time : 3 seconds or less (per device side) —

Soldering Conditions Symbol

Caution Use of more than one soldering method should be avoided (except for partial heating).

Table 12-2. Insertion Type Soldering Conditions

µ

PD75P0076CU: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)

Soldering Method Soldering Conditions
Wave soldering (pins only) Solder bath temperature: 260 ˚C or less, Time: 10 seconds or less
Partial heating Pin temperature: 300 ˚C or below, Time: 3 seconds or less (per device side)

Caution Ensure that the application of wave soldering is limited to the pins and no solder touches the

main unit directly.

53

APPENDIX A DIFFERENCES AMONG µPD75068, 750068 AND 75P0076

µ

PD75P0076

Parameter

Program memory Mask ROM Mask ROM One-time PROM

Data memory 000H to 1FFH

(512 x 4 bits)

CPU 75X Standard CPU 75XL CPU

General-purpose register 4 bits x 8 or 8 bits x 4 (4 bits x 8 or 8 bits x 4) x 4 banks

Instruction When main system 0.95, 1.91, 15.3
execution clock is selected (during 4.19-MHz operation) • 0.95, 1.91, 3.81, 15.3
time

When subsystem 122
clock is selected

I/O port CMOS input 12 (Connections of on-chip pull-up resistor specified by software: 7)

CMOS input/output 12 (Connections of on-chip pull-up resistor specified by software)

N-ch open-drain 8 (on-chip pull-up resistor 8 (on-chip pull-up resistor 8 (no mask option)
input/output specified by mask option) specified by mask option) Withstand voltage is 13 V

Withstand voltage is 10 V Withstand voltage is 13 V

Total 32

Timer 3 channels 4 channels

• 8-bit timer/event counter • 8-bit timer/event counter 0 (watch timer output added)

• 8-bit basic interval timer • 8-bit timer/event counter 1 (can be used as a 16-bit timer/

• Watch timer event counter)

µ

PD75068

0000H to 1F7FH 0000H to 1FFFH 0000H to 3FFFH

(8064 x 8 bits) (8192 x 8 bits) (16384 x 8 bits)

µ

s • 0.67, 1.33, 2.67, 10.7 µs (during 6.0-MHz operation)

µ

s (during 32.768-kHz operation)

µ

PD750068

µ

s (during 4.19-MHz operation)

• 8-bit basic interval timer/watchdog timer

• Watch timer

µ

PD75P0076

A/D converter •

Clock output (PCL) Φ, 524, 262, 65.5 kHz • Φ, 1.05 MHz, 262 kHz, 65.5 kHz

Buzzer output (BUZ) 2, 4, 32 kHz • 2, 4, 32 kHz

Serial interface 3 modes supported 2 modes supported

Vectored interrupt 3 external, 3 internal 3 external, 4 internal

Test inputs 1 external, 1 internal

Power supply voltage V

Operating ambient temperature T

Package • 42-pin plastic shrink DIP • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)

8-bit resolution x 8 channels
(successive approximation) (successive approximation)

• Can operate at the voltage • Can operate at the voltage from V

DD = 2.7 V

from V

(Main system clock: (Main system clock: during 4.19-MHz operation)
during 4.19-MHz operation) • Φ, 1.5 MHz, 375 kHz, 93.8 kHz

(Main system clock: (Main system clock: during 4.19-MHz operation or
during 4.19-MHz operation subsystem clock: during 32.768-kHz operation)
or subsystem clock: during • 2.93, 5.86, 46.9 kHz

32.768-kHz operation) (Main system clock: during 6.0-MHz operation)

• 3-wire serial I/O mode • 3-wire serial I/O mode...MSB/LSB first selectable
...MSB/LSB first selectable • 2-wire serial I/O mode

• 2-wire serial I/O mode

• SBI mode

DD = 2.7 to 6.0 V VDD = 1.8 to 5.5 V

A = –40 to +85 ˚C

(600 mil)

• 44-pin plastic QFP • 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
(10 x 10 mm)

• 8-bit resolution x 8 channels

DD = 1.8 V

(Main system clock: during 6.0-MHz operation)

Note Under development

54

µ

PD75P0076

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for system development using the µPD75P0076. In the 75XL series, the
common relocatable assembler of the series is used together with device files according to the product.

RA75X relocatable assembler Host machine Order code (Part No.)

OS Supply Medium

PC-9800 Series MS-DOS

IBM PC/AT
or compatible IBM PCs 5" 2HC

Device file Host machine Order code (Part No.)

PC-9800 Series MS-DOS 3.5" 2HD

IBM PC/AT Refer to OS for 3.5" 2HC
or compatible IBM PCs 5" 2HC

TM

Refer to OS for 3.5" 2HC

OS Supply Medium

TM

Ver.3.30 to 5" 2HD

Note

Ver.6.2

Ver.3.30 to 5" 2HD

Note

Ver.6.2

3.5" 2HD

µ

S5A13RA75X

µ

S5A10RA75X

µ

S7B13RA75X

µ

S7B10RA75X

µ

S5A13DF750068

µ

S5A10DF750068

µ

S7B13DF750068

µ

S7B10DF750068

Note Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.

Remark Operation of the assembler and device file is guaranteed only when using the host machine and OS described

above.

PROM Write Tools

Hardware PG-1500 This is a PROM programmer which enables you to program a single-chip microcontroller with

on-chip PROM by stand-alone or host machine operation by connecting an attached board and
a programmer adapter (sold separately).
In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed.

PA-75P0076CU This is a PROM programmer adapter dedicated for the µPD75P0076CU and 75P0076GT. It

Software PG-1500 controller PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is

can be used when connected to a PG-1500.

controlled on the host machine.
Host machine Order code (Part No.)

OS Supply medium

PC-9800 Series MS-DOS 3.5" 2HD

Ver.3.30 to 5" 2HD

Note

Ver.6.2
IBM PC/AT Refer to OS for 3.5" 2HD
or compatible IBM PCs 5" 2HC

µ

S5A13PG1500

µ

S5A10PG1500

µ

S7B13PG1500

µ

S7B10PG1500

Note Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.

Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.

55

µ

PD75P0076

Debugging Tools

In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P0076.
Various system configurations using these in-circuit emulators are listed below.

Hardware IE-75000-R

IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during

IE-75300-R-EM This is an emulation board for evaluating application systems that use the µPD750068

EP-750068CU-R This is an emulation probe for the µPD75P0076CU.

EP-750068GT-R This is an emulation probe for the µPD75P0076GT.

Software IE control program This program can control the IE-75000-R or IE-75001-R on a host machine when connected to

Note 1

EV-9500GT-42 When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems that use 75X or 75XL Series products. For development
of the µPD750068 subseries, the IE-75000-R is used with a separately sold emulation board (IE­75300-R-EM) and emulation probe.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.
The IE-75000-R can include a connected emulation board (IE-75000-R-EM).

development of application systems that use 75X or 75XL Series products. The IE-75001-R is
used with a separately sold emulation board (IE-75300-R-EM) and emulation probe.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.

subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator.

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

It includes a flexible board (EV-9500GT-42) to facilitate connections with target systems.

the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.
Host machine Order code (Part No.)

OS Supply Medium

PC-9800 Series MS-DOS 3.5" 2HD

Ver.3.30 to 5" 2HD

Note 2

Ver.6.2
IBM PC/AT Refer to OS for 3.5" 2HC
or compatible IBM PCs 5" 2HC

µ

S5A13IE75X

µ

S5A10IE75X

µ

S7B13IE75X

µ

S7B10IE75X

Notes 1. This is a service part provided for maintenance purpose only.

2. Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.

Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described

above.

µ

2. The generic name for the

PD750064, 750066, 750068, and 75P0076 is the µPD750068 subseries.

56

µ

PD75P0076

OS for IBM PCs

The following operating systems for the IBM PC are supported.

OS Version

PC DOS

MS-DOS Ver.5.0 to Ver.6.22

IBM DOS

Note Only the English mode is supported.

Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function.

TM

TM

Ver.5.02 to Ver.6.3

Note

J6.1/V

5.0/V
J5.02/V

Note

to 6.2/V

Note

to J6.3/V

Note

Note

57

µ

PD75P0076

APPENDIX C RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.

Documents related to device

Document Name

µ

PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet U10165E

µ

PD75P0076 Data Sheet This document U10232J

µ

PD750068 User’s Manual U10670E U10670J

µ

PD750068 Instruction Table — IEM-5606

75XL Series Selection Guide U10453E U10453J

Document No.

English Japanese

Note

U10165J

Note Preliminary product information

Documents related to development tool

Document Name

Hardware IE-75000-R/IE-75001-R User’s Manual EEU-1416 EEU-846

IE-75300-R-EM User’s Manual U11345E U11354J
EP-750068GT-R User’s Manual U10950E U10950J
PG-1500 User’s Manual EEU-1335 EEU-651

Software RA75X Assembler Package User’s Manual Operation EEU-1346 EEU-731

Language EEU-1363 EEU-730

PG-1500 Controller User’s Manual PC-9800 Series EEU-1291 EEU-704

(MS-DOS) base
IBM PC Series U10540E EEU-5008

(PC DOS) base

Document No.

English Japanese

Other related documents

Document Name

IC Package Manual C10943X
Semiconductor Device Mounting Technology Manual C10535E C10535J
NEC Semiconductor Device Quality Grades C11531E C11531J
NEC Semiconductor Device Reliability and Quality Control C10983E C10983J
Electrostatic Discharge (ESD) Test — MEM-539
Semiconductor Device Quality Assurance Guide MEI-1202 MEI-603
Microcontroller-related Product Guide —Third Party Products— — U11416J

Caution The contents of the documents listed above are subject to change without prior notice to users. Make

sure to use the latest edition when starting design.

Document No.

English Japanese

58

[MEMO]

µ

PD75P0076

59

NOTES FOR CMOS DEVICES

(1)PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.

µ

PD75P0076

(2)HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.

(3)STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme­diately after power-on for devices having reset function.

60

µ

PD75P0076

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel:[phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: [phone]
Fax: [phone]

J96. 8

61

µ

PD75P0076

MS-DOS is a trademark of Microsoft Corporation.
PC DOS, PC/AT, and IBM DOS are trademarks of IBM Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without
governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country
other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5