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UPD75P0016CU
Datasheet (NEC)
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Datasheet UPD75P0016GB-3BS-MTX, UPD75P0016CU Datasheet (NEC)

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Page 1
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75P0016
4-BIT SINGLE-CHIP MICROCONTROLLER
The µPD75P0016 replaces the µPD750008’s internal mask ROM with a one-time PROM and features expanded
ROM capacity.
µ
Because the
development using the µPD750004, 750006, or 750008 products, and for use in small-lot production.
Detailed information about product features and specifications can be found in the following document
PD75P0016 supports programming by users, it is suitable for use in prototype testing for system
µ
PD750008 User's Manual: U10740E

FEATURES

• Compatible with µPD750008
• Memory capacity:
• PROM : 16384 × 8 bits
• RAM : 512 × 4 bits
µ
• Can operate in same power supply voltage as the mask ROM version
DD = 2.2 to 5.5 V
• V
• Supports QTOP™ microcontroller
Remark QTOP Microcontroller is the general name for a total support service that includes imprinting, marking,
screening, and verifying one-time PROM single-chip microcontrollers offered by NEC.

ORDERING INFORMATION

Part number Package ROM (× 8 bits)
µ
PD75P0016CU 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch) 16384
µ
PD75P0016GB-3BS-MTX 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch) 16384
Caution On-chip pull-up resistors by mask option cannot be provided.
PD750008
Document No. U10328EJ3V1DS00 (3rd edition) Date Published August 2000 N CP(K) Printed in Japan
The information in this document is subject to change without notice.
The mark shows major revised points.
©
1995
Page 2
µ
PD75P0016

FUNCTION LIST

Item Function
Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation)
• 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation)
• 122 µs (subsystem clock: at 32.768 kHz operation)
On-chip memory PROM 16384 × 8 bits
RAM 512 × 4 bits
General register • In 4-bit operation: 8 × 4 banks
• In 8-bit operation: 4 × 4 banks
I/O port CMOS input 8 Connection of on-chip pull-up resistor specifiable by software: 7
CMOS I/O 18 Direct LED drive capability
Connection of on-chip pull-up resistor specifiable by software: 18
N-ch open drain I/O 8 Direct LED drive capability
13 V withstand voltage
Total 34
Timer 4 channels
• 8-bit timer/event counter: 1 channel
• 8-bit timer counter: 1 channel
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface • 3-wire serial I/O mode ... Switching of MSB/LSB-first
• 2-wire serial I/O mode
• SBI mode Bit sequential buffer (BSB) 16 bits Clock output (PCL) • Φ, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)
• Φ, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) Buzzer output (BUZ) • 2, 4, 32 kHz (main system clock: at 4.19 MHz operation or subsystem clock:
at 32.768 kHz operation)
• 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) Vectored interrupt External: 3 Internal: 4 Test input External: 1 Internal: 1 System clock oscillation circuit • Main system clock oscillation ceramic/crystal oscillation circuit
• Subsystem clock oscillation crystal oscillation circuit Standby function STOP/HALT mode Operating ambient temperature TA = –40 to +85˚C Supply voltage VDD = 2.2 to 5.5 V Package 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
2
Data Sheet U10328EJ3V1DS00
Page 3
µ
PD75P0016
TABLE OF CONTENTS
1. PIN CONFIGURATION........................................................................................................................ 4
2. BLOCK DIAGRAM............................................................................................................................. 6
3. PIN FUNCTIONS................................................................................................................................ 7
3.1 Port Pins ..................................................................................................................................................... 7
3.2 Non-port Pins .............................................................................................................................................8
3.3 I/O Circuits for Pins ................................................................................................................................... 9
3.4 Handling of Unused Pins ........................................................................................................................ 11
4. SWITCHING BETWEEN MK I AND MK II MODES .......................................................................... 12
4.1 Differences between Mk I Mode and Mk II Mode................................................................................... 12
4.2 Setting of Stack Bank Selection (SBS) Register................................................................................... 13
5. DIFFERENCES BETWEEN µPD75P0016 AND µPD750004, 750006, AND 750008 ...................... 14
6. MEMORY CONFIGURATION ........................................................................................................... 15
7. INSTRUCTION SET .......................................................................................................................... 17
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY................................................... 28
8.1 Operation Modes for Program Memory Write/Verify ............................................................................ 28
8.2 Steps in Program Memory Write Operation .......................................................................................... 29
8.3 Steps in Program Memory Read Operation........................................................................................... 30
8.4 One-Time PROM Screening ..................................................................................................... ............... 31
9. ELECTRICAL SPECIFICATIONS.....................................................................................................32
10. CHARACTERISTIC CURVES (REFERENCE VALUE) .................................................................... 46
11. PACKAGE DRAWINGS .................................................................................................................... 48
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50
APPENDIX A. FUNCTION LIST OF µPD75008, 750008, 75P0016 ....................................................... 51
APPENDIX B. DEVELOPMENT TOOLS................................................................................................. 53
APPENDIX C. RELATED DOCUMENTS ................................................................................................ 57
Data Sheet U10328EJ3V1DS00
3
Page 4

1. PIN CONFIGURATION (Top View)

•42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µ
PD75P0016CU
µ
PD75P0016
XT1 XT2
RESET
X1
X2 P33/MD3 P32/MD2 P31/MD1 P30/MD0
P81 P80
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
P13/TI0 P12/INT2 P11/INT1 P10/INT0
Note
V
PP
V
DD
Note Directly connect V
V
1 2
3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21
PP to VDD in the normal operation mode.
42 41
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
SS
P40/D0 P41/D1 P42/D2 P43/D3 P50/D4 P51/D5 P52/D6 P53/D7 P60/KR0 P61/KR1
P62/KR2 P63/KR3 P70/KR4 P71/KR5 P72/KR6 P73/KR7 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ
• 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
µ
PD75P0016GB-3BS-MTX
P73/KR7
P20/PTO0
44
10 11
43
1 2 3 4 5 6 7 8 9
12
13
NC
P43/D3
P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0
P53/D7 P52/D6 P51/D5 P50/D4
P21/PTO1
P22/PCL
42
41
14
15
P42/D2
P41/D1
P23/BUZ
40
39
16
17
P40/D0
DD
V
SS
V
Note
38
18
PP
V
P10/INT0
37
19
XT1
XT2
P11/INT1
36
35
20
21
RESET
P12/INT2
NC
34
33 32 31 30 29 28 27 26 25 24 23
22
X1
X2
P13/TI0 P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P80 P81 P30/MD0 P31/MD1 P32/MD2 P33/MD3
Note Directly connect V
4
Data Sheet U10328EJ3V1DS00
PP to VDD in the normal operation mode.
Page 5
µ
PD75P0016
PIN IDENTIFICATIONS
P00-P03 : Port0 SCK : Serial Clock P10-P13 : Port1 SI : Serial Input P20-P23 : Port2 SO : Serial Output P30-P33 : Port3 SB0, SB1 : Serial Data Bus 0,1 P40-P43 : Port4 RESET : Reset P50-P53 : Port5 TI0 : Timer Input 0 P60-P63 : Port6 PTO0, PTO1 : Programmable Timer Output 0, 1 P70-P73 : Port7 BUZ : Buzzer Clock P80, P81 : Port8 PCL : Programmable Clock KR0-KR7 : Key Return 0-7 INT0, 1, 4 : External Vectored Interrupt 0, 1, 4
DD : Positive Power Supply INT2 : External Test Input 2
V VSS : Ground X1, X2 : Main System Clock Oscillation 1, 2
PP : Programming Power Supply XT1, XT2 : Subsystem Clock Oscillation 1, 2
V NC : No Connection MD0-MD3 : Mode Selection 0-3
D0-D7 : Data Bus 0-7
Data Sheet U10328EJ3V1DS00
5
Page 6

2. BLOCK DIAGRAM

µ
PD75P0016
TI0/P13
PTO0/P20
PTO1/P21
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT0/P10 INT1/P11 INT2/P12 INT4/P00
KR0/P60­KR7/P73
BUZ/P23
BASIC INTERVAL TIMER/ WATCHDOG TIMER
8-BIT TIMER/EVENT COUNTER #0
INTT0
8-BIT TIMER
COUNTER
CLOCKED SERIAL INTERFACE
INTCSI
INTERRUPT
CONTROL
8
INTBT
#1
INTT1
WATCH
TIMER
INTW
TOUT0
TOUT0
PROGRAM
COUNTER (14)
PROGRAM
MEMORY
(PROM)
16384 × 8 BITS
CLOCK OUTPUT CONTROL
fx/2
CLOCK
DIVIDER
N
SYSTEM CLOCK
GENERATOR
ALU
DECODE
AND
CONTROL
CPU CLOCK
Φ
MAINSUB
CY
STAND BY CONTROL
SP (8)
SBS
BANK
GENERAL REGISTER
DATA
MEMORY
(RAM)
512 × 4 BITS
BIT SEQ.
BUFFER (16)
PORT0 P00-P034
PORT1
PORT2 4
PORT3 P30/MD0-P33/MD34
PORT4 P40/D0-P43/D34
PORT5 P50/D4-P53/D74
PORT6 P60-P634
PORT7 P70-P734
PORT8 P80, P812
P10-P134
P20-P23
PCL/P22
X2X1XT2XT1
VSSVDD RESETVPP
6
Data Sheet U10328EJ3V1DS00
Page 7

3. PIN FUNCTIONS

3.1 Port Pins

µ
PD75P0016
Pin name I/O Shared by Function 8-bit When I/O circuit
P00 I INT4 This is a 4-bit input port (PORT0). × Input <B> P01 I/O SCK are software-specifiable in 3-bit units. <F>-A P02 I/O SO/SB0 <F>-B P03 I/O SI/SB1 <M>-C P10 I INT0 This is a 4-bit input port (PORT1). × Input <B>-C P11 INT1 specifiable in 4-bit units. P12 INT2 P13 TI0 P20 I/O PTO0 This is a 4-bit I/O port (PORT2). × Input E-B P21 PTO1 specifiable in 4-bit units. P22 PCL P23 BUZ P30 I/O MD0 This is a programmable 4-bit I/O port (PORT3). × Input E-B P31 MD1 units. On-chip pull-up resistor connections are P32 MD2 P33 MD3
Note 2
P40
Note 2
P41
Note 2
P42
Note 2
P43
Note 2
P50
Note 2
P51
Note 2
P52
Note 2
P53 P60 I/O KR0 This is a programmable 4-bit I/O port (PORT6). Input <F>-A P61 KR1 On-chip pull-up resistor connections are software­P62 KR2 P63 KR3
I/O D0 This is an N-ch open-drain 4-bit I/O port (PORT4). High
D1 D2 D3
I/O D4 This is an N-ch open-drain 4-bit I/O port (PORT5). High
D5 D6 D7
For P01 to P03, on-chip pull-up resistor connections
On-chip pull-up resistor connections are software­P10/INT0 can select noise elimination circuit.
On-chip pull-up resistor connections are software-
Input and output can be specified in single-bit software-specifiable in 4-bit units.
In the open-drain mode, withstands up to 13 V. impedance M-E
In the open-drain mode, withstands up to 13 V. impedance M-E
Input and output can be specified in single-bit units. specifiable in 4-bit units.
I/O reset type
Note 1
P70 I/O KR4 This is a 4-bit I/O port (PORT7). Input <F>-A
On-chip pull-up resistor connections are software-
P71 KR5 specifiable in 4-bit units. P72 KR6 P73 KR7 P80 I/O — This is a 2-bit I/O port (PORT8). × Input E-B
On-chip pull-up resistor connections are software-
P81 — specifiable in 2-bit units.
Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.
2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.
Data Sheet U10328EJ3V1DS00
7
Page 8

3.2 Non-port Pins

µ
PD75P0016
Pin name I/O Shared by Function When I/O circuit
TI0 I P13 External event pulse input to timer/event counter Input <B>-C PTO0 O P20 Timer/event counter output Input E-B PTO1 P21 Timer counter output PCL P22 Clock output BUZ P23 Outputs any frequency (for buzzer or system clock trimming) SCK I/O P01 Serial clock I/O Input <F>-A SO/SB0 P02 Serial data output <F>-B
SI/SB1 P03 Serial data input <M>-C
INT4 I P00 Edge-triggered vectored interrupt input <B>
INT0 I P10 Edge-triggered vectored interrupt input With noise eliminator Input <B>-C
INT1 P11 circuit. Asynch INT2 P12 Rising edge-triggered testable input Asynch KR0-KR3 I P60-P63 Falling edge-triggered testable input Input <F>-A KR4-KR7 I P70-P73 Falling edge-triggered testable input Input <F>-A X1 I — Ceramic/crystal resonator connection for main system clock. — —
X2 — inverted clock to X2. XT1 I — Crystal resonator connection for subsystem clock. — —
XT2 — ed clock to X2. XT1 can be used as a 1-bit (test) input. RESET I — System reset input (low level active) — <B> MD0-MD3 I P30-P33 Mode selection for program memory (PROM) write/verify. Input E-B D0-D3 I/O P40-P43 Data bus pin for program memory (PROM) write/verify. Input M-E D4-D7 P50-P53
Note 2
VPP
VDD — — Positive power supply — — VSS — — Ground potential — —
— — Programmable voltage supply in program memory (PROM) — —
Serial data bus I/O
Serial data bus I/O
(Detects both rising and falling edges).
(detected edge is selectable). /asynch selectable INT0/P10 can select noise elimination
If using an external clock, input it to X1 and input the
If using an external clock, input it to XT1 and input the invert-
write/verify mode. In normal operation mode, connect directly to VDD. Apply +12.5 V in PROM write/verify mode.
reset type
Note 1
Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.
2. During normal operation, the VPP pin will not operate normally unless connected to VDD pin.
8
Data Sheet U10328EJ3V1DS00
Page 9

3.3 I/O Circuits for Pins

(
)
The I/O circuits for the µPD75P0016’s pin are shown in schematic diagrams below.
TYPE A TYPE D
V
DD
Data
IN
CMOS standard input buffer
P-ch
N-ch
Output
disable
Push-pull output that can be set to high impedance output (with both P-ch and N-ch OFF).
µ
PD75P0016
V
DD
P-ch
OUT
N-ch
TYPE E-BTYPE B
IN
Output
disable
Schmitt trigger input with hysteresis characteristics.
TYPE B-C TYPE F-A
V
DD
P.U.R.
P-ch
P.U.R. enable
Data
P.U.R. enable
Type D
P.U.R. : Pull-Up Resistor
P.U.R. enable
Type A
V
DD
P-ch
IN/OUT
V
DD
P.U.R.
P.U.R.
P-ch
IN
P.U.R. : Pull-Up Resistor
Data
Output
disable
Data Sheet U10328EJ3V1DS00
Type D
Type B
P.U.R. : Pull-Up Resistor
IN/OUT
Continued
9
Page 10
µ
PD75P0016
TYPE F-B
output disable (P)
data
output disable
TYPE M-C
output disable (N)
P.U.R. enable
V
DD
P.U.R. : Pull-Up Resistor
P-ch
N-ch
V
TYPE M-E
V
DD
IN/OUT
P.U.R. P-ch
IN/OUT
data
output disable
Input instruction
V
DD
P-ch
P.U.R.
N-ch (+13 V)
Note
Voltage
limitation
circuit
(+13 V)
Note Pull-up resistor that operates only when an input instruction has been executed. (Current flows from V
DD
DD
to the pins when at low level)
data
output disable
P.U.R. enable
N-ch
P.U.R. : Pull-Up Resistor
P.U.R. P-ch
IN/OUT
10
Data Sheet U10328EJ3V1DS00
Page 11

3.4 Handling of Unused Pins

P00/INT4 Connect to VSS or VDD P01/SCK Individually connect to VSS or VDD via resistor P02/SO/SB0 P03/SI/SB1 Connect to VSS P10/INT0-P12/INT2 Connect to VSS or VDD P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ P30/MD0-P33/MD3 P40/D0-P43/D3 Connect to VSS P50/D4-P53/D7 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P80, P81
Note
XT1
Note
XT2 VPP Make sure to connect directly to VDD
Table 3-1. Handling of Unused Pins
Pin Recommended connection
Input mode : individually connect to VSS or VDD
via resistor
Output mode : open
Input mode : individually connect to VSS or VDD
via resistor
Output mode : open
Connect to VSS Open
µ
PD75P0016
Note When the subsystem clock is not used, set SOS. 0 to 1 (not to use the internal feedback resistor).
Data Sheet U10328EJ3V1DS00
11
Page 12
µ
PD75P0016

4. SWITCHING BETWEEN MK I AND MK II MODES

Setting a stack bank selection (SBS) register for the µPD75P0016 enables the program memory to be switched between the Mk I mode and the Mk II mode. This capability enables the evaluation of the µPD750004, 750006, or 750008 using the µPD75P0016.
µ
When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of
When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of µPD750004, 750006, and 750008)

4.1 Differences between Mk I Mode and Mk II Mode

Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the
Table 4-1. Differences between Mk I Mode and Mk II Mode
Item Mk I mode Mk II mode Program counter PC13-0 Program memory (bytes) 16384 Data memory (bits) 512 × 4 Stack Stack bank Selectable from memory banks 0 and 1
Stack bytes 2 bytes 3 bytes
Instruction BRA !addr1 None Provided
CALLA !addr1 Instruction CALL !addr 3 machine cycles 4 machine cycles execution time CALLF !faddr 2 machine cycles 3 machine cycles Supported mask ROM versions and Mk I mode of µPD750004, 750006, and Mk II mode of µPD750004, 750006, and
mode 750008 750008
PD750004, 750006, and 750008)
µ
PD75P0016.
Caution The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes. When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle. Therefore, when more importance is attached to RAM utilization or throughput than software compatibility, use the Mk I mode.
12
Data Sheet U10328EJ3V1DS00
Page 13
µ
PD75P0016

4.2 Setting of Stack Bank Selection (SBS) Register

Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format
for doing this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode,
Note
be sure to initialize the stack bank selection register to 100×B
Note
II mode, be sure to initialize it to 000×B
.
at the beginning of the program. When using the Mk
Note Set the desired value for ×.
Figure 4-1. Format of Stack Bank Selection Register
Address 3 2 1 0
SBS3 SBS2 SBS1 SBS0F84H
Symbol
SBS
Stack area specification
0 0 1 1
0 Be sure to set 0 for bit 2.
Memory bank 0
0
Memory bank 1
1 0
Setting prohibited
1
Mode selection specification
01Mk II mode
Mk I mode
Caution SBS3 is set to “1” after RESET input, and consequently the CPU operates in the Mk I mode. When using
instructions for the Mk II mode, set SBS3 to “0” to enter the Mk II mode before using the instructions.
Data Sheet U10328EJ3V1DS00
13
Page 14
µ
PD75P0016
5. DIFFERENCES BETWEEN µPD75P0016 AND µPD750004, 750006, AND 750008
The µPD75P0016 replaces the internal mask ROM in the µPD750004, 750006, and 750008 with a one-time PROM and features expanded ROM capacity. The µPD75P0016’s Mk I mode supports the Mk I mode in the µPD750004, 750006, and 750008 and the µPD75P0016’s Mk II mode supports the Mk II mode in the µPD750004, 750006, and 750008.
µ
Table 5-2 lists differences among the differences between corresponding versions beforehand, especially when a PROM version is used for debugging or prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production.
µ
Please refer to the
PD750008 User's Manual (U10740E) for details on CPU functions and on-chip hardware.
Table 5-1. Differences between
PD75P0016 and the µPD750004, 750006, and 750008. Be sure to check the
µ
PD75P0016 and µPD750004, 750006, and 750008
Item Program counter 12-bit 13-bit 14-bit Program memory (bytes) Mask ROM Mask ROM Mask ROM One-time PROM
Data memory (× 4 bits) 512 Mask options Pull-up resistor for Yes (On-chip/not on-chip can be specified.) No (On-chip not
port 4 and port 5 possible) Wait time when Yes (217/fx or 215/fx)
RESET Feedback resistor Yes (can select usable or unusable.) No (usable)
for subsystem clock
Pin connection Pins 6-9 (CU) P33-P30 P33/MD3-P30/MD0
Pins 23-26 (GB) Pin 20 (CU) IC VPP Pin 38 (GB) Pins 34-37 (CU) P53-P50 P53/D7-P50/D4 Pins 8-11 (GB) Pins 38-41 (CU) P43-P40 P43/D3-P40/D0 Pins 13-16 (GB)
Other Noise resistance and noise radiation may differ due to the different circuit complexities and
µ
PD750004
4096 6144 8192 16384
mask layouts.
Note
µ
PD750006
µ
PD750008
µ
No (fixed at 215/fx)
PD75P0016
Note
Note 217/fx : 21.8 ms @ 6.0 MHz, 31.3 ms @ 4.19 MHz
15
/fx : 5.46 ms @ 6.0 MHz, 7.81 ms @ 4.19 MHz
2
Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using
a mask ROM version instead of the PROM version for processes between prototype development and full production, be sure to fully evaluate the CS of the mask ROM version (not ES).
14
Data Sheet U10328EJ3V1DS00
Page 15

6. MEMORY CONFIGURATION

76 0
MBE
RBE
0000H
0002H
0004H
0006H
0008H
000AH
000CH
MBE
MBE
MBE
MBE
MBE
MBE
Internal reset start address (higher 6 bits) Internal reset start address (lower 8 bits)
RBE
INTBT/INT4 start address (higher 6 bits) INTBT/INT4 start address (lower 8 bits)
RBE
INT0 start address (higher 6 bits) INT0 start address (lower 8 bits)
RBE
INT1 start address (higher 6 bits) INT1 start address (lower 8 bits)
RBE
INTCSI start address (higher 6 bits) INTCSI start address (lower 8 bits)
RBE
INTT0 start address (higher 6 bits) INTT0 start address (lower 8 bits)
RBE
INTT1 start address (higher 6 bits) INTT1 start address (lower 8 bits)
Figure 6-1. Program Memory Map
CALLF
!faddr instruction
entry address
BRCB
!caddr instruction
branch address
Branch address for
the following instructions
µ
PD75P0016
• BR BCDE
• BR BCXA
• BR !addr
• CALL !addr
• BRA !addr1
• CALLA !addr1
Note
Note
0020H
007FH 0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
Reference table for GETI instruction
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
Branch/call
address by GETI
BR $addr instruction
relative branch address
(–15 to –1,
+2 to +16)
Note Can be used only at Mk II mode.
Remark For instructions other than those noted above, the “BR PCDE” and “BR PCXA” instructions can be used to
branch to addresses with changes in the PC’s lower 8 bits only.
Data Sheet U10328EJ3V1DS00
15
Page 16
Figure 6-2. Data Memory Map
µ
PD75P0016
Data area
static RAM
(512 × 4)
General
register
Stack area
area
Note
000H
01FH
020H
0FFH
100H
1FFH
Data memory
(32 × 4)
256 × 4
(224 × 4)
256 × 4
Memory bank
0
1
Unimplemented
F80H
Peripheral hardware area
FFFH
128 × 4
Note For the stack area, one memory bank can be selected from memory bank 0 or 1.
15
16
Data Sheet U10328EJ3V1DS00
Page 17
µ
PD75P0016

7. INSTRUCTION SET

(1) Representation and coding formats for operands
In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, refer to the RA75X Assembler Package User’s Manual [EEU-1363]). When there are several codes, select and use just one. Upper-case letters, and + and – symbols are key words that should be entered as they are. For immediate data, enter an appropriate numerical value or label. Instead of mem, fmem, pmem, bit, etc, a register flag symbol can be described as a label descriptor. (For further
µ
description, refer to the restricted.
reg X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 BC, DE, HL rp2 BC, DE rp’ XA, BC, DE, HL, XA’, BC’, DE’, HL’ rp’1 BC, DE, HL, XA’, BC’, DE’, HL’ rpa HL, HL+, HL–, DE, DL rpa1 DE, DL n4 4-bit immediate data or label n8 8-bit immediate data or label mem 8-bit immediate data or label bit 2-bit immediate data or label fmem FB0H-FBFH, FF0H-FFFH immediate data or label pmem FC0H-FFFH immediate data or label addr 0000H-3FFFH immediate data or label addr1 0000H-3FFFH immediate data or label (in Mk II mode only) caddr 12-bit immediate data or label faddr 11-bit immediate data or label taddr 20H-7FH immediate data (however, bit0 = 0) or label PORTn PORT0-PORT8 IEXXX IEBT, IECSI, IET0, IET1, IE0-IE2, IE4, IEW RBn RB0-RB3 MBn MB0, MB1, MB15
PD750008 User's Manual [U10740E]) Labels that can be entered for fmem and pmem are
Representation Coding format
Note
Note When processing 8-bit data, only even addresses can be specified.
Data Sheet U10328EJ3V1DS00
17
Page 18
(2) Operation legend
A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : Register pair (XA); 8-bit accumulator BC : Register pair (BC) DE : Register pair (DE) HL : Register pair (HL) XA’ : Expansion register pair (XA’) BC’ : Expansion register pair (BC’) DE’ : Expansion register pair (DE’) HL’ : Expansion register pair (HL’) PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0 to 8) IME : Interrupt master enable flag IPS : Interrupt priority select register IE××× : Interrupt enable flag RBS : Register bank select register MBS : Memory bank select register PCC : Processor clock control register . : Delimiter for address and bit (××) : Contents of address ××
××H : Hexadecimal data
µ
PD75P0016
18
Data Sheet U10328EJ3V1DS00
Page 19
(3) Description of symbols used in addressing area
MB = MBE • MBS
*1
MB = 0
*2
MBE = 0 :
*3
MBE = 1 :
MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
*4
MB = 15, pmem = FC0H-FFFH
*5
addr = 0000H-3FFFH
*6
addr, addr1 =*7(Current PC) –15 to (Current PC) –1
caddr =0000H-0FFFH (PC
*8
MBS = 0, 1, 15
MB = 0 (000H-07FH) MB = 15 (F80H-FFFH) MB = MBS MBS = 0, 1, 15
(Current PC) +2 to (Current PC) +16
13, 12
= 00B) or 1000H-1FFFH (PC13, 12 = 01B) or 2000H-2FFFH (PC13, 12 = 10B) or 3000H-3FFFH (PC13, 12 = 11B)
µ
PD75P0016
Data memory
addressing
Program memory
addressing
faddr = 0000H-07FFH
*9
taddr = 0020H-007FH
*10
addr1 = 0000H-3FFFH (Mk II mode only)
*11
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
Data Sheet U10328EJ3V1DS00
19
Page 20
µ
PD75P0016
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as shown below.
• No skip .......................................................................... S = 0
• Skipped instruction is 1-byte or 2-byte instruction......... S = 1
Note
• Skipped instruction is 3-byte instruction
Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1
Caution The GETI instruction is skipped for one machine cycle.
................. S = 2
One machine cycle equals one cycle (= t
CY) of the CPU clock Φ. Use the PCC setting to select among four cycle times.
20
Data Sheet U10328EJ3V1DS00
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PD75P0016
Group Mnemonic Operand
Transfer MOV A, # n4 1 1 A ← n4 String-effect A
reg1, # n4 2 2 reg1 ← n4 XA, # n8 2 2 XA ← n8 String-effect A HL, # n8 2 2 HL ← n8 String-effect B rp2, # n8 2 2 rp2 ← n8 A, @HL 1 1 A ← (HL) *1 A, @HL+ 1 2 + S A ← (HL), then L ← L + 1 *1 L = 0 A, @HL– 1 2 + S A ← (HL), then L ← L – 1 *1 L = FH A, @rpa1 1 1 A ← (rpa1) *2 XA, @HL 2 2 XA ← (HL) *1 @HL, A 1 1 (HL) ← A*1 @HL, XA 2 2 (HL) ← XA *1 A, mem 2 2 A ← (mem) *3 XA, mem 2 2 XA ← (mem) *3 mem, A 2 2 (mem) ← A*3 mem, XA 2 2 (mem) ← XA *3 A, reg 2 2 A ← reg XA, rp’ 2 2 XA ← rp’ reg1, A 2 2 reg1 ← A rp’1, XA 2 2 rp’1 ← XA
XCH A, @HL 1 1 A ↔ (HL) *1
A, @HL+ 1 2 + S A ↔ (HL), then L ← L + 1 *1 L = 0 A, @HL– 1 2 + S A ↔ (HL), then L ← L – 1 *1 L = FH A, @rpa1 1 1 A ↔ (rpa1) *2 XA, @HL 2 2 XA ↔ (HL) *1 A, mem 2 2 A ↔ (mem) *3 XA, mem 2 2 XA ↔ (mem) *3 A, reg1 1 1 A ↔ reg1
XA, rp’ 2 2 XA ↔ rp’ Table MOVT XA, @PCDE 1 3 XA ← (PC13-8 + DE)ROM reference XA, @PCXA 1 3 XA ← (PC13-8 + XA)ROM
XA, @BCDE 1 3 XA ← (BCDE)ROM
XA, @BCXA 1 3 XA ← (BCXA)ROM
No. of Machine
bytes cycle area
Operation
Note
Note
Addressing
*6 *6
Skip
condition
Note As for the B register, only the lower 2 bits are valid.
Data Sheet U10328EJ3V1DS00
21
Page 22
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PD75P0016
Group Mnemonic Operand
Bit transfer MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4
CY, pmem.@L 2 2 CY ← (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← (H + mem3-0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) ← CY *4 pmem.@L, CY 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← CY *5 @H + mem.bit, CY 2 2 (H + mem3-0.bit) ← CY *1
Operation ADDS A, #n4 1 1 + S A ← A + n4 carry
XA, #n8 2 2 + S XA ← XA + n8 carry A, @HL 1 1 + S A ← A + (HL) *1 carry XA, rp’ 2 2 + S XA ← XA + rp’ carry rp’1, XA 2 2 + S rp’1 ← rp’1 + XA carry
ADDC A, @HL 1 1 A, CY ← A + (HL) + CY *1
XA, rp’ 2 2 XA, CY ← XA + rp’ + CY rp’1, XA 2 2 rp’1, CY ← rp’1 + XA + CY
SUBS A, @HL 1 1 + S A ← A – (HL) *1 borrow
XA, rp’ 2 2 + S XA ← XA – rp’ borrow rp’1, XA 2 2 + S rp’1 ← rp’1 – XA borrow
SUBC A, @HL 1 1 A, CY ← A – (HL) – CY *1
XA, rp’ 2 2 XA, CY ← XA – rp’ – CY rp’1, XA 2 2 rp’1, CY ← rp’1 – XA – CY
AND A, #n4 2 2 A ← A ^ n4
A, @HL 1 1 A ← A ^ (HL) *1 XA, rp’ 2 2 XA ← XA ^ rp’ rp’1, XA 2 2 rp’1 ← rp’1 ^ XA
OR A, #n4 2 2 A ← A v n4
A, @HL 1 1 A ← A v (HL) *1 XA, rp’ 2 2 XA ← XA v rp’ rp’1, XA 2 2 rp’1 ← rp’1 v XA
XOR A, #n4 2 2 A ← A v n4
A, @HL 1 1 A ← A v (HL) *1 XA, rp’ 2 2 XA ← XA v rp’ rp’1, XA 2 2 rp’1 ← rp’1 v XA
No. of Machine
bytes cycle area
Operation
Addressing
Skip
condition
22
Data Sheet U10328EJ3V1DS00
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PD75P0016
Group Mnemonic Operand
Accumulator RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An manipulate NOT A 2 2 A ← A Increment/ INCS reg 1 1 + S reg ← reg + 1 reg = 0 decrement rp1 1 1 + S rp1 ← rp1 + 1 rp1 = 00H
@HL 2 2 + S (HL) ← (HL) + 1 *1 (HL) = 0
mem 2 2 + S (mem) ← (mem) + 1 *3 (mem) = 0
DECS reg 1 1 + S reg ← reg – 1 reg = FH
rp’ 2 2 + S rp’ ← rp’ – 1 rp’ = FFH Compare SKE reg, #n4 2 2 + S Skip if reg = n4 reg = n4
@HL, #n4 2 2 + S Skip if (HL) = n4 *1 (HL) = n4
A, @HL 1 1 + S Skip if A = (HL) *1 A = (HL)
XA, @HL 2 2 + S Skip if XA = (HL) *1 XA = (HL)
A, reg 2 2 + S Skip if A = reg A = reg
XA, rp’ 2 2 +S Skip if XA = rp’ XA = rp’ Carry flag SET1 CY 1 1 CY ← 1 manipulate CLR1 CY 1 1 CY ← 0
SKT CY 1 1 + S Skip if CY = 1 CY = 1 NOT1 CY 1 1 CY ← CY
No. of Machine
bytes cycle area
Operation
Addressing
Skip
condition
Data Sheet U10328EJ3V1DS00
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PD75P0016
Group Mnemonic Operand
Memory bit SET1 mem.bit 2 2 (mem.bit) ← 1*3 manipulate fmem.bit 2 2 (fmem.bit) 1 *4
pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) 1 *5 @H + mem.bit 2 2 (H + mem3-0.bit) ← 1*1
CLR1 mem.bit 2 2 (mem.bit) 0 *3
fmem.bit 2 2 (fmem.bit) 0 *4 pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) 0 *5 @H + mem.bit 2 2 (H + mem3-0.bit) ← 0*1
SKT mem.bit 2 2 + S Skip if(mem.bit) = 1 *3 (mem.bit) = 1
fmem.bit 2 2 + S Skip if(fmem.bit) = 1 *4 (fmem.bit) = 1 pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 1 *5 (pmem.@L) = 1 @H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 1 *1
SKF mem.bit 2 2 + S Skip if(mem.bit) = 0 *3 (mem.bit) = 0
fmem.bit 2 2 + S Skip if(fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2 + S Skip if(pmem7-2 + L3-2.bit(L1-0)) = 0 *5 (pmem.@L) = 0 @H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 0 *1
SKTCLR fmem.bit 2 2 + S Skip if(fmem.bit) = 1 and clear *4 (fmem.bit) = 1
pmem.@L 2 2 + S @H + mem.bit 2 2 + S Skip if(H + mem3-0.bit) = 1 and clear *1
AND1 CY, fmem.bit 2 2 CY ← CY ^ (fmem.bit) *4
CY, pmem.@L 2 2 CY ← CY ^ (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← CY ^ (H + mem3-0.bit) *1
OR1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4
CY, pmem.@L 2 2 CY ← CY v (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← CY v (H + mem3-0.bit) *1
XOR1 CY, fmem.bit 2 2 CY ← CY v (fmem.bit) *4
CY, pmem.@L 2 2 CY ← CY v (pmem7-2 + L3-2.bit(L1-0)) *5 CY, @H + mem.bit 2 2 CY ← CY v (H + mem3-0.bit) *1
No. of Machine
bytes cycle area
Skip if(pmem7-2 + L3-2.bit (L1-0)) = 1 and clear
←
←
←
Operation
Addressing
←
←
*5 (pmem.@L) = 1
Skip
condition
(@H + mem.bit) = 1
(@H + mem.bit) = 0
(@H + mem.bit) = 1
24
Data Sheet U10328EJ3V1DS00
Page 25
µ
PD75P0016
Group Mnemonic Operand
Branch BR
Note 1
addr — — PC13-0 ← addr *6
addr1 — — PC13-0 ← addr1 *11
!addr 3 3 PC13-0 ← addr *6
$addr 1 2 PC13-0 ← addr *7
$addr1 1 2 PC13-0 ← addr1
PCDE 2 3 PC13-0 ← PC13-8 + DE
PCXA 2 3 PC13-0 ← PC13-8 + XA
BCDE 2 3 PC13-0 ← BCDE
BCXA 2 3 PC13-0 ← BCXA
Note 1
BRA
!addr1 3 3 PC13-0 ← addr1 *11
BRCB !caddr 2 2 PC13-0 ← PC13, 12 + caddr11-0 *8
No. of Machine
Operation
Addressing
bytes cycle area
Assembler selects the most appropriate instruction among the following:
• BR !addr
• BRCB !caddr
• BR $addr
Assembler selects the most appropriate instruction among the following:
• BRA !addr1
• BR !addr
• BRCB !caddr
• BR $addr1
Note 2
Note 2
*6 *6
Skip
condition
Notes 1. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
2. As for the B register, only the lower 2 bits are valid.
Data Sheet U10328EJ3V1DS00
25
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µ
PD75P0016
Group Mnemonic Operand
No. of Machine
Operation
bytes cycle area
Subroutine CALLA
Note
!addr1 3 3 (SP – 5) ← 0, 0, PC13,12 *11
stack control (SP – 6)(SP – 3)(SP – 4) ← PC11-0
(SP – 2)
←
×, ×, MBE, RBE
PC13–0
←
CALL
Note
!addr 3 3 (SP
–
(SP
– 3) ←
PC13–0
addr1, SP
4)(SP
←
addr, SP
←
SP – 6
–
1)(SP
– 2) ←
PC11-0 *6
(MBE, RBE, PC13, 12)
←
SP – 4
4 (SP – 5) ← 0, 0, PC13,12
(SP – 6)(SP – 3)(SP – 4) ← PC11-0 (SP
– 2) ←
×, ×, MBE, RBE
PC13-0
←
CALLF
Note
!faddr 2 2 (SP
(SP PC13-0
addr, SP
–
4)(SP
– 3) ←
←
000 + faddr, SP
–
← SP –
1)(SP
6
– 2) ←
PC11-0 *9
(MBE, RBE, PC13, 12)
←
SP – 4
3 (SP – 5) ← 0, 0, PC13,12
(SP – 6)(SP – 3)(SP – 4) ← PC11-0 (SP – 2)
←
×, ×, MBE, RBE
PC13-0
←
000 + faddr,SP ← SP – 6
Note
RET
1 3 (MBE, RBE, PC13, 12) ← (SP + 1)
PC11-0 → (SP)(SP + 3)(SP + 2) SP ← SP + 4 ×, ×, MBE, RBE ← (SP + 4) 0, 0, PC13-12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 6
Note
RETS
1 3 + S (MBE, RBE, PC13, 12) ← (SP + 1) Unconditional
PC11-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 4 then skip unconditionally ×, ×, MBE, RBE ← (SP + 4) 0, 0, PC13-12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) SP ← SP + 6 then skip unconditionally
Note
RETI
1 3 MBE, RBE, PC13, 12 ← (SP + 1)
PC11-0 ← (SP)(SP + 3)(SP + 2) PSW ← (SP + 4)(SP + 5), SP ← SP + 6 0, 0, PC13, 12 ← (SP + 1) PC11-0 ← (SP)(SP + 3)(SP + 2) PSW ← (SP + 4)(SP + 5), SP ← SP + 6
Addressing
Skip
condition
Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
26
Data Sheet U10328EJ3V1DS00
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µ
PD75P0016
Group Mnemonic Operand
No. of Machine
Operation
bytes cycle area Subroutine PUSH rp 1 1 (SP – 1)(SP – 2) ← rp, SP ← SP – 2 stack control BS 2 2
(SP – 1) ← MBS, (SP – 2) ← RBS, SP ← SP – 2
POP rp 1 1 rp ← (SP + 1)(SP), SP ← SP + 2
BS 2 2
MBS ← (SP + 1), RBS ← (SP), SP ← SP + 2 Interrupt EI 2 2 IME(IPS.3) ← 1 control IE××× 22IE××× ← 1
DI 2 2 IME(IPS.3) ← 0
IE××× 22IE××× ← 0
I/O IN
Note 1
A, PORTn 2 2 A ← PORTn (n = 0 - 8) XA, PORTn 2 2 XA ← PORTn+1, PORTn (n = 4, 6)
Note 1
OUT
PORTn, A 2 2 PORTn ← A (n = 2 - 8) PORTn, XA 2 2 PORTn+1, PORTn ← XA (n = 4, 6)
CPU control HALT 2 2 Set HALT Mode(PCC.2 ← 1)
STOP 2 2 Set STOP Mode(PCC.3 ← 1) NOP 1 1 No Operation
Special SEL RBn 2 2 RBS ← n (n = 0 - 3)
MBn 2 2 MBS ← n (n = 0, 1, 15)
Note 2, 3
GETI
taddr 1 3 • When using TBR instruction *10
PC13-0 ← (taddr)5-0 + (taddr + 1)
- - - - - - - - - - - - - - - - - - - - - - - - -
• When using TCALL instruction
(SP – 4)(SP – 1)(SP – 2) ← PC11-0
(SP – 3) ← MBE, RBE, PC13, 12
PC13-0 ← (taddr)5-0 + (taddr + 1)
SP ← SP – 4
- - - - - - - - - - - - - - - - - - - - - - - - -
• When using instruction other than Determined by
TBR or TCALL referenced
Execute (taddr)(taddr + 1) instructions instruction
1 3 • When using TBR instruction *10
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PC13-0 ← (taddr)5-0 + (taddr + 1)
4 • When using TCALL instruction
(SP – 5) ← (SP – 6)(SP – 3)(SP – 4) ←
(SP
– 2) ←
×, ×, MBE, RBE
0, 0, PC13, 12
PC11-0
PC13-0 ← (taddr)5-0 + (taddr + 1)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
SP ← SP – 6
3 • When using instruction other than Determined by
TBR or TCALL referenced
Execute (taddr)(taddr + 1) instructions instruction
Addressing
Skip
condition
- - - - - - - - - - -
- - - - - - - - - - -
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.
2. TBR and TCALL are assembler directives for the GETI instruction’s table definitions.
3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
Data Sheet U10328EJ3V1DS00
27
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µ
PD75P0016

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory in the µPD75P0016 is a 16384 × 8-bit electronic write-enabled one-time PROM. The pins listed in the table below are used for this PROM’s write/verify operations. Clock input from the X1 pins is used instead of address input as a method for updating addresses.
Pin name Function
VPP Pin (usually VDD) where programming voltage is applied during
X1, X2 Clock input pin for address updating during program memory
MD0/P30-MD3/P33 Operation mode selection pin for program memory write/verify D0/P40-D3/P43 (lower 4) 8-bit data I/O pin for program memory write/verify
D4/P50-D7/P53 (higher 4) VDD Pin where power supply voltage is applied. Power voltage
Caution Pins not used for program memory write/verify should be processed as follows.
• All unused pins except XT2 ...... Connect to Vss via a pull-down resistor
• XT2 pin ........................................Leave open
program memory write/verify
write/verify. Input the X1 pin’s inverted signal to the X2 pin.
range for normal operation is 2.2 to 5.5 V. Apply 6.0 V for program memory write/verify.

8.1 Operation Modes for Program Memory Write/Verify

µ
When +6 V is applied to the
PD75P0016’s VDD pin and +12.5 V is applied to its VPP pin, program write/verify modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation mode specification Operation mode VPP VDD MD0 MD1 MD2 MD3 +12.5 V +6 V H L H L Zero-clear program memory address
L H H H Write mode L L H H Verify mode
H × H H Program inhibit mode
Remark ×: L or H
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Data Sheet U10328EJ3V1DS00
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PD75P0016

8.2 Steps in Program Memory Write Operation

High-speed program memory write can be executed via the following steps.
SS
(1) Pull down unused pins to V
via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 µs. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V to V
DD and +12.5 V power to VPP.
(6) Write data using 1-ms write mode. (7) Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7). (8) X [= number of write operations from steps (6) and (7)] × 1 ms additional write (9) 4 pulse inputs to the X1 pin updates (increments +1) the program memory address. (10) Repeat steps (6) to (9) until the last address is completed. (11) Zero-clear mode for program memory addresses. (12) Apply +5 V to the V
DD and VPP pins.
(13) Power supply OFF
The following diagram illustrates steps (2) to (9).
VPP
VPP
VDD
VDD + 1
VDD
V
X1
D0/P40-D3/P43 D4/P50-D7/P53
MD0/P30
MD1/P31
DD
Write
Data input
X repetitions
Verify
Data output
Additional
write
Data input
Address increment
MD2/P32
MD3/P33
Data Sheet U10328EJ3V1DS00
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PD75P0016

8.3 Steps in Program Memory Read Operation

The µPD75P0016 can read out the program memory contents via the following steps.
SS
(1) Pull down unused pins to V
via resistors. Set the X1 pin to low. (2) Apply +5 V to the VDD and VPP pins. (3) Wait 10 µs. (4) Zero-clear mode for program memory addresses. (5) Apply +6 V power to V
DD and +12.5 V to VPP.
(6) Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based
on a cycle of four pulse inputs. (7) Zero-clear mode for program memory addresses. (8) Apply +5 V power to the V
DD and VPP pins.
(9) Power supply OFF
The following diagram illustrates steps (2) to (7).
V
PP
V
PP
V
DD
VDD+ 1
V
DD
V
DD
X1
D0/P40-D3/P43 D4/P50-D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
Data output Data output
“L”
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Data Sheet U10328EJ3V1DS00
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PD75P0016

8.4 One-Time PROM Screening

Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends the screening process, that is, after the required data is written to the PROM and the PROM is stored under the high­temperature conditions shown below, the PROM should be verified.
Storage temperature Storage time
125˚C 24 hours
At present, a fee is charged by NEC for one-time PROM after-programming imprinting, screening, and verify service for the QTOP Microcontroller. For details, contact your sales representative.
Data Sheet U10328EJ3V1DS00
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PD75P0016

9. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25˚C)
Parameter Symbol Conditions Ratings Unit Supply voltage VDD –0.3 to + 7.0 V PROM supply voltage VPP –0.3 to + 13.5 V Input voltage VI1 Other than port 4, 5 –0.3 to VDD + 0.3 V
VI2 Port 4, 5 (N-ch open drain) –0.3 to + 14 V Output voltage VO –0.3 to VDD + 0.3 V High-level output current IOH Per pin –10 mA
Total of all pins –30 mA
Low-level output current IOL Per pin 30 mA
Total of all pins 220 mA
Operating ambient TA –40 to + 85 ˚C temperature
Storage temperature Tstg –65 to + 150 ˚C
Caution If the absolute maximum rating of even one of the parameters is exceeded even momentarily,
the quality of the product may be degraded. The absolute maximum ratings are therefore values which, when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded when using the product.
Capacitance (T
Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Pins other than tested pins: 0 V 15 pF I/O capacitance CIO 15 pF
A = 25˚C, VDD = 0 V)
32
Data Sheet U10328EJ3V1DS00
Page 33
Main System Clock Oscillation Circuit Characteristics (TA = – 40 to +85˚C)
µ
PD75P0016
Resonator
Ceramic Oscillation frequency VDD = 2.2 to 5.5 V 1.0 resonator (fX)
Recommended
constants
X1 X2
C1 C2
Parameter Conditions MIN. TYP. MAX. Unit
Note 2
Note 1
Oscillation After VDD has 4 ms stabilization time
Note 3
reached MIN. value of
6.0
MHz
oscillation voltage range
Crystal Oscillation frequency VDD = 2.2 to 5.5 V 1.0 resonator (fX)
X1 X2
C1 C2
Note 1
Oscillation VDD = 4.5 to 5.5 V 10 ms stabilization time
Note 3
6.0
Note 2
MHz
VDD = 2.2 to 5.5 V 30 ms
External X1 input frequency VDD = 1.8 to 5.5 V 1.0 clock (fX)
Note 1
6.0
Note 4
MHz
X1 X2
X1 input high-, VDD = 1.8 to 5.5 V 83.3 500 ns low-level widths (tXH, tXL)
Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation
circuit only. For the instruction execution time, refer to AC Characteristics.
2. If the oscillation frequency is 4.7 MHz < f
X ≤ 6.0 MHz at 2.2 V ≤ VDD < 2.7 V of the supply voltage, please
do not set processor clock control register (PCC) = 0011. If PCC = 0011, one machine cycle is less than
µ
s, falling short of the rated value of 0.85 µs.
0.85
3. The oscillation stablilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released.
4. If the X1 input frequency is 4.19 MHz < f
x ≤ 6.0 MHz at 1.8 V ≤ VDD < 2.7 V of the supply voltage, please
do not set PCC = 0011. If PCC = 0011, one machine cycle time is less than 0.95 µs, falling short of the rated value of 0.95 µs.
Caution When using the main system clock oscillation circuit, wire the portion enclosed in the dotted
line in the above figure as follows to prevent adverse influences due to wiring capacitance:
· Keep the wiring length as short as possible.
· Do not cross the wiring with other signal lines.
· Do not route the wiring in the vicinity of a line through which a high alternating current flows.
· Always keep the ground point of the capacitor of the oscillation circuit at the same potential
DD.
as V Do not ground to a power supply pattern through which a high current flows.
· Do not extract signals from the oscillation circuit.
Data Sheet U10328EJ3V1DS00
33
Page 34
Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85˚C)
µ
PD75P0016
Resonator
Crystal Oscillation frequency VDD = 2.2 to 5.5 V 32 32.768 35 kHz resonator (fXT)
External XT1 input frequency VDD = 1.8 to 5.5 V 32 100 kHz clock (fXT)
Recommended
constants
XT1 XT2
R
C3 C4
XT1 XT2
Parameter Conditions MIN. TYP. MAX. Unit
Note 1
Oscillation VDD = 4.5 to 5.5 V 1.0 2 s stabilization time
Note 1
XT1 input high-, VDD = 1.8 to 5.5 V 5 15 low-level widths (tXTH, tXTL)
Note 2
VDD = 2.2 to 5.5 V 10 s
µ
s
Notes 1. The oscillation frequency shown above indicate characteristics of the oscillation circuit only. For the
instruction execution time, refer to AC Characteristics.
2. The oscillation stabilization time is the time required for oscillation to be stabilized after V
DD has been
applied.
Caution When using the subsystem clock oscillation circuit, wire the portion enclosed in the dotted line
in the above figure as follows to prevent adverse influences due to wiring capacitance:
· Keep the wiring length as short as possible.
· Do not cross the wiring with other signal lines.
· Do not route the wiring in the vicinity of a line through which a high alternating current flows.
· Always keep the ground point of the capacitor of the oscillation circuit at the same potential
DD.
as V Do not ground to a power supply pattern through which a high current flows.
· Do not extract signals from the oscillation circuit.
The subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and is more susceptible to noise than the main system clock oscillation circuit. Therefore, exercise utmost care in wiring the subsystem clock oscillation circuit.
RECOMMENDED OSCILLATION CIRCUIT CONSTANT
Main System Clock: Ceramic Resonator (T
Manufacturer Part Number Frequency Constant (pF) Range (VDD) Remark
(MHz) C1 C2 MIN. (V) MAX. (V)
TDK Corp. CCR4.0MC32 4.0 10 10 2.3 5.5 —
A = –40 to +85˚C)
Oscillation Circuit Oscillation Voltage
Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable
oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used.
34
Data Sheet U10328EJ3V1DS00
Page 35
µ
PD75P0016
DC Characteristics (TA = –40 to + 85˚C, VDD = 2.2 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit Low-level IOL Per pin 15 mA output current Total of all pins 150 mA High-level input VIH1 Ports 2, 3, 8 2.7 ≤ VDD ≤ 5.5 V 0.7 VDD VDD V voltage 2.2 ≤ VDD ≤ 2.7 V 0.9 VDD VDD V
VIH2 Ports 0, 1, 6, 7, RESET 2.7 ≤ VDD ≤ 5.5 V 0.8 VDD VDD V
2.2 ≤ VDD ≤ 2.7 V 0.9 VDD VDD V
VIH3 Ports 4, 5 (N-ch open drain) 2.7 ≤ VDD ≤ 5.5 V 0.7 VDD 13 V
2.2 ≤ VDD ≤ 2.7 V 0.9 VDD 13 V
VIH4 X1, XT1 VDD–0.1 VDD V Low-level input VIL1 Ports 2-5, 8 2.7 ≤ VDD ≤ 5.5 V 0 0.3 VDD V voltage 2.2 ≤ VDD ≤ 2.7 V 0 0.1 VDD V
VIL2 Ports 0, 1, 6, 7, RESET 2.7 ≤ VDD ≤ 5.5 V 0 0.2 VDD V
2.2 ≤ VDD ≤ 2.7 V 0 0.1 VDD V
VIL3 X1, XT1 0 0.1 V High-level output VOH SCK, SO, ports 2, 3, 6-8 VDD–0.5 V
voltage IOH = –1.0 mA Low-level output VOL1 SCK, SO, IOL = 15 mA, VDD = 4.5 to 5.5 V 0.2 2.0 V voltage ports 2-8 IOL = 1.6 mA 0.4 V
VOL2 SB0, SB1 N-ch open drain 0.2 VDD V
Pull-up resistor ≥ 1 kΩ High-level input ILIH1 VIN = VDD Pins other than X1 and XT1 3 leakage current ILIH2 X1, XT1 20
ILIH3 VIN = 13 V Ports 4, 5 (N-ch open drain) 20 Low-level input ILIL1 VIN = 0 V Pins other than ports 4, 5, X1 and XT1 –3 leakage current ILIL2 X1, XT1 –20
ILIL3 Ports 4, 5 (N-ch open drain) When –3
High-level output ILOH1 VOUT = VDD SCK, SO/SB0, SB1, Ports 2, 3, 6-8 3 leakage current ILOH2 Low-level output ILOL VOUT = 0 V –3 leakage current Internal pull-up RL VIN = 0 V Ports 0-3, 6-8 (except P00 pin) 50 100 200 kΩ resistor
VOUT = 13 V
input instruction is not executed Ports 4, 5 (N-ch open drain) When input VDD = 5.0 V –10 –27 instruction is executed
Ports 4, 5 (N-ch open drain) 20
VDD = 3.0 V –3 –8
–30
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
Data Sheet U10328EJ3V1DS00
35
Page 36
DC Characteristics (TA = –40 to + 85˚C, VDD = 2.2 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current
Note 1
IDD1 VDD = 5.0 V ± 10 %
IDD2 VDD = 5.0 V ± 10 % 0.92 2.6 mA
IDD1 VDD = 5.0 V ± 10 %
IDD2 VDD = 5.0 V ± 10 % 0.9 2.5 mA
IDD3 VDD = 3.0 V ± 10 % 42 126
IDD4
Note 2
6.0 MHz crystal oscillation C1 = C2 = 22 pF
Note 2
4.19 MHz crystal oscillation C1 = C2 = 22 pF
32.768
Note 5
kHz crystal oscillation
VDD = 3.0 V ± 10 % HALT
mode
VDD = 3.0 V ± 10 % 0.3 0.9 mA
VDD = 3.0 V ± 10 % HALT
mode
VDD = 3.0 V ± 10 % 0.28 0.8 mA
Low­voltage mode
Low current dissipation mode
VDD = 2.5 V ± 10 % 23 69
Note 6
VDD = 3.0 V, TA = 25 ˚C 42 84 VDD = 3.0 V ± 10 % 39 117
Note 7
VDD = 3.0 V, TA = 25 ˚C 39 78
HALT mode
Note 8
IDD5 VDD = 5.0 V ± 10 % 0.05 10
XT1 = 0V STOP mode
VDD = 3.0 V ± 10 % 0.02 5
Low­voltage
Note 6
mode
Low current consumption
Note 7
mode
Note 3
Note 4
Note 3
Note 4
VDD = 3.0 V ± 10 % VDD = 2.5 V ± 10 % VDD = 3.0 V, TA = 25 ˚C VDD = 3.0 V ± 10 % VDD = 3.0 V, TA = 25 ˚C
3.7 11.0 mA
0.73 2.2 mA
2.7 8.0 mA
0.57 1.7 mA
8.5 25
5.0 15
8.5 17
3.5 12
3.5 7
TA = 25 ˚C 0.02 3
µ
PD75P0016
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
µ
A
Notes 1. The current flowing through the internal pull-up resistor is not included.
2. Including the case when the subsystem clock oscillates.
3. When the device operates in high-speed mode with the processor clock control register (PCC) set to
0011.
4. When the device operates in low-speed mode with PCC set to 0000.
5. When the device operates on the subsystem clock, with the system clock control register (SCC) set to
1001 and oscillation of the main system clock stopped.
6. When the suboscillation circuit control register (SOS) is set to 0000.
7. When SOS is set to 0010.
8. When SOS is set to 00×1, and the suboscillation circuit feedback resistor is not used (×: don’t care).
36
Data Sheet U10328EJ3V1DS00
Page 37
µ
PD75P0016
AC Characteristics (TA = –40 to + 85˚C, VDD = 2.2 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CPU clock cycle tCY VDD = 2.7 to 5.5 V 0.67 64
Note 1
time (minimum instruction VDD = 2.7 to 5.5 V 0.67 64 execution time = 1 VDD = 1.8 to 5.5 V 0.95 64 machine cycle) Operates with subsystem clock 114 122 125 TI0 input frequency fTI VDD = 2.7 to 5.5 V 0 1.0 MHz
TI0 high-, low-level tTIH, tTIL VDD = 2.7 to 5.5 V 0.48 widths 1.8 Interrupt input high-, tINTH, INT0 IM02 = 0 Note 2 low-level widths tINTL IM02 = 1 10
RESET low-level width
tRSL 10
Operates with main system clock
INT1, 2, 4 10 KR0-KR7 10
with ceramic oscillator or crystal resonator
with external clock
0.85 64
0 275 kHz
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
Notes 1. The cycle time of the CPU clock (Φ) is determined by the oscillation frequency of the connected resonator
(and external clock), the system clock control register (SCC), and processor clock control register (PCC). The figure on the right shows the supply voltage VDD vs. cycle time tCY characteristics when the device operates with the main system clock.
CY or 128/fX depending on the setting of the interrupt mode register (IM0).
2. 2t
64 60
6 5
4
µ
( s)
3
CY
2
Cycle time t
1
0.95
0.85
0.67
0.5 0
CY
vs V
DD
t
(with main system clock)
Operation guaranteed range
12 3456
1.8 2.2 2.7 Supply voltage V
DD
5.5
[V]
Remark Shaded area indicates operation when external clock is used.
Data Sheet U10328EJ3V1DS00
37
Page 38
Serial Transfer Operation
µ
PD75P0016
2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK cycle time tKCY1 VDD = 2.7 to 5.5 V 1300 ns
SCK high-, low-level widths tKL1,VDD = 2.7 to 5.5 V
tKH1
Note 1
SI
setup time tSIK1 VDD = 2.7 to 5.5 V 150 ns
(vs. SCK ↑) 500 ns
Note 1
SI
hold time tKSI1 VDD = 2.7 to 5.5 V 400 ns (vs. SCK ↑) 600 ns SCK ↓ → SO delay time CL = 100 pF 0 1000 ns
Note 1
output tKSO1 RL = 1 kΩ
Note 2
VDD = 2.7 to 5.5 V 0 2 50 n s
A = –40 to +85°C, VDD = 2.2 to 5.5 V)
3800 ns
tKCY1/2–50
tKCY1/2–150
Notes 1. Read as SB0 or SB1 when using the 2-wire serial I/O mode.
2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (T
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK cycle time tKCY2 VDD = 2.7 to 5.5 V 800 ns
SCK high-, low-level widths tKL2,VDD = 2.7 to 5.5 V 400 ns
tKH2 1600 ns
Note 1
SI
setup time tSIK2 VDD = 2.7 to 5.5 V 100 ns (vs. SCK ↑) 150 ns
Note 1
SI
hold time tKSI2 VDD = 2.7 to 5.5 V 400 ns (vs. SCK ↑) 600 ns SCK ↓ → SO delay time CL = 100 pF 0 1000 ns
Note 1
output tKSO2 RL = 1 kΩ
Note 2
VDD = 2.7 to 5.5 V 0 3 00 n s
A = –40 to +85°C, VDD = 2.2 to 5.5 V)
3200 ns
ns ns
Notes 1. Read as SB0 or SB1 when using the 2-wire serial I/O mode.
2. RL and CL respectively indicate the load resistance and load capacitance of the SO output line.
38
Data Sheet U10328EJ3V1DS00
Page 39
µ
PD75P0016
SBI mode (SCK ··· internal clock output (master)): (TA = –40 to +85°C, VDD = 2.2 to 5.5 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK cycle time tKCY3 VDD = 2.7 to 5.5 V 1300 ns
3800 ns
SCK high-, low-level widths tKL3 VDD = 2.7 to 5.5 V
tKH3 SB0, 1 setup time tSIK3 VDD = 2.7 to 5.5 V 150 ns (vs. SCK ↑) 500 ns SB0, 1 hold time (vs. SCK ↑)tKSI3 tKCY3/2 ns SCK ↓ → SB0, 1 output tKSO3 RL = 1 kΩ delay time CL = 100 pF 0 1000 ns SCK ↑ → SB0, 1 ↓ tKSB tKCY3 ns SB0, 1 ↓ → SCK ↓ tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns
Note
VDD = 2.7 to 5.5 V 0 2 50 n s
tKCY3/2–50
tKCY3/2–150
ns ns
Note R L and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.
SBI mode (SCK ··· external clock input (slave)): (T
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK cycle time tKCY4 VDD = 2.7 to 5.5 V 800 ns
SCK high-, low-level widths tKL4 VDD = 2.7 to 5.5 V 400 ns
tKH4 1600 ns SB0, 1 setup time tSIK4 VDD = 2.7 to 5.5 V 100 ns (vs. SCK ↑) 150 ns SB0, 1 hold time (vs. SCK ↑)tKSI4 tKCY4/2 ns SCK ↓ → SB0, 1 output tKSO4 RL = 1 kΩ delay time CL = 100 pF 0 1000 ns SCK ↑ → SB0, 1 ↓ tKSB tKCY4 ns SB0, 1 ↓ → SCK ↓ tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns
A = –40 to +85°C, VDD = 2.2 to 5.5 V)
3200 ns
Note
VDD = 2.7 to 5.5 V 0 3 00 n s
Note R L and CL respectively indicate the load resistance and load capacitance of the SB0 and 1 output lines.
Data Sheet U10328EJ3V1DS00
39
Page 40
AC Timing Test Points (except X1 and XT1 inputs)
µ
PD75P0016
Clock timing
X1 input
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
VIH (MIN.) VIL (MAX.)
VOH (MIN.) VOL (MAX.)
1/f
X
t
XL
t
XH
VDD – 0.1 V
0.1 V
1/f
XT
t
XTL
t
XTH
TI0 timing
XT1 input
TI0
VDD – 0.1 V
0.1 V
1/f
TI
t
TIL
t
TIH
40
Data Sheet U10328EJ3V1DS00
Page 41
Serial Transfer Timing
3-wire serial I/O mode
SCK
t
KL1, 2
t
SIK1, 2
t
KCY1, 2
t
KSI1, 2
t
KH1, 2
µ
PD75P0016
SI
SO
2-wire serial I/O mode
SCK
SB0, 1
t
KSO1, 2
Input data
t
KL1, 2
t
SIK1, 2
Output data
t
KCY1, 2
t
KH1, 2
t
KSI1, 2
t
KSO1, 2
Data Sheet U10328EJ3V1DS00
41
Page 42
Serial Transfer Timing
Bus release signal transfer
SCK
t
KSB
SB0, 1
Command signal transfer
µ
PD75P0016
t
KCY3, 4
t
t
KL3, 4
t
t
t
SBL
SBH
SBK
t
KCY3, 4
KH3, 4
t
KSO3, 4
t
SIK3, 4
t
KSI3, 4
SCK
SB0, 1
Interrupt input timing
INT0, 1, 2, 4 KR0-7
RESET input timing
t
KL3, 4
t
t
KSB
SBK
t
INTL
t
KH3, 4
t
INTH
t
KSO3, 4
t
SIK3, 4
t
KSI3, 4
42
RESET
t
RSL
Data Sheet U10328EJ3V1DS00
Page 43
µ
STOP mode
Data retention mode
Internal reset operation
Operation mode
STOP instruction execution
HALT mode
V
DD
RESET
t
WAIT
t
SREL
PD75P0016
Data Retention Characteristics of Data Memory in STOP Mode and at Low Supply Voltage (TA = –40 to +85˚C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Release signal setup time tSREL 0
µ
s Oscillation stabilization tWAIT Released by RESET 215/fx ms wait time
Note 1
Released by interrupt request Note 2 ms
Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent
unstable operation when oscillation is started.
2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)
BTM3 BTM2 BTM1 BTM0
–0002 –0112 –1012 –1112
fx = 4.19 MHz fx = 6.0 MHz
20
/fx (approx. 250 ms) 220/fx (approx. 175 ms)
17
/fx (approx. 31.3 ms) 217/fx (approx. 21.8 ms)
15
/fx (approx. 7.81 ms) 215/fx (approx. 5.46 ms)
13
/fx (approx. 1.95 ms) 213/fx (approx. 1.37 ms)
Data retention timing (when STOP mode released by RESET)
Wait Time
Data retention timing (standby release signal: when STOP mode released by interrupt signal)
Standby release signal
DD
V
STOP instruction execution
(interrupt request)
STOP mode
Data retention mode
Data Sheet U10328EJ3V1DS00
HALT mode
t
SREL
t
Operation mode
WAIT
43
Page 44
µ
PD75P0016
DC Programming Characteristics (TA = 25 ± 5°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input voltage, high VIH1 Other than X1, X2 pins 0.7 VDD VDD V
VIH2 X1, X2
Input voltage, low VIL1 Other than X1, X2 pins 0 0.3 VDD V
VIL2 X1, X2 0 0.4 V Input leakage current ILI VIN = VIL or VIH 10 Output voltage, high VOH IOH = – 1 mA Output voltage, low VOL IOL = 1.6 mA 0.4 V VDD supply current IDD 30 mA VPP supply current IPP MD0 = VIL, MD1 = VIH 30 mA
VDD – 0.5
VDD – 1.0
VDD V
Cautions 1. Keep VPP to within +13.5 V, including overshoot.
2. Apply VDD before VPP and turn it off after VPP.
µ
A
V
AC Programming Characteristics (T
Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit
Address setup time (vs. MD0 ↓)
MD1 setup time (vs. MD0 ↓)tM1S tOES 2 Data setup time (vs. MD0 ↓)tDS t DS 2 Address hold time
(vs. MD0 ↑) Data hold time (vs. MD0 ↑)tDH tDH 2 MD0 ↑ → data output float tDF tDF 0 130 ns
delay time VPP setup time (vs. MD3 ↑)tVPS tVPS 2 VDD setup time (vs. MD3 ↑)tVDS tVCS 2 Initial program pulse width tPW tPW 0.95 1.0 1.05 ms Additional program pulse width MD0 setup time (vs. MD1 ↑)tM0S tCES 2 MD0 ↓ → data output delay time MD1 hold time (vs. MD0 ↑)tM1H tOEH tM1H + tM1R ≥ 50 µs2 MD1 recovery time (vs. MD0 ↓) Program counter reset time tPCR —10 X1 input high-, low-level width X1 input frequency fX — 4.19 MHz Initial mode set time t1 —2 MD3 setup time (vs. MD1 ↑)tM3S —2 MD3 hold time (vs. MD1 ↓)tM3H —2 MD3 setup time (vs. MD0 ↓)tM3SR — When program memory is read 2 Address
delay time Address
hold time MD3 hold time (vs. MD0 ↑)tM3HR — When program memory is read 2 MD3 ↓ → data output float tDFR — When program memory is read 2
delay time
Note 2
Note 2
Note 2
Note 2
→ data output tDAD tACC When program memory is read 2
→ data output tHAD tOH When program memory is read 0 130 ns
tAS tAS 2
tAH tAH 2
tOPW tOPW 0.95 21.0 ms
tDV tDV MD0 = MD1 = VIL 1
tM1R tOR 2
tXH, tXL — 0.125
A = 25 ± 5°C, VDD = 6.0 ± 0.25 V, VPP = 12.5 ± 0.3 V, VSS = 0 V)
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
Notes 1. Symbol of corresponding µPD27C256A
2. The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not
connected to a pin.
44
Data Sheet U10328EJ3V1DS00
Page 45
Program Memory Write Timing
tVPS
VPP
V
PP
VDD
tVDS
VDD+1
VDD
V
DD
X1
tXH
µ
PD75P0016
D0/P40-D3/P43 D4/P50-D7/P53
tI
Data input
tDS
MD0/P30
tPW
MD1/P31
tPCR
tM1S tM1H
MD2/P32
t
M3S
MD3/P33
Program Memory Read Timing
t
t
VPS
VDS
V
V
PP
PP
V
DD
VDD+1
V
DD
DD
V
tDH
tM1R
t
Data output
tDV tDF
XH
t
M0S
Data input Data input
tXL
tDS
tDH
tAH tAS
tOPW
tM3H
X1
D0/P40-D3/P43 D4/P50-D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
t
XL
Data output
t
t
M3SR
DV
Data Sheet U10328EJ3V1DS00
t
I
t
PCR
t
t
DAD
HAD
Data output
t
t
M3HR
DFR
45
Page 46

10. CHARACTERISTICS CURVES (REFERENCE VALUE)

y
)
IDD vs VDD (Main system clock : 6.0 MHz crystal resonator)
10
5.0
PCC = 0011
PCC = 0010 PCC = 0001 PCC = 0000
µ
PD75P0016
A
= 25°C)
(T
1.0
0.5
(mA)
DD
0.1
Supply Current I
0.05
0.01
Main system clock HALT mode +32-kHz oscillation
Subsystem clock operation mode (SOS.1 = 0)
Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 0)
Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 1)
46
0.005
0.001 01234
Suppl
Voltage VDD (V
Data Sheet U10328EJ3V1DS00
X1
5678
X2 XT1
Crystal resonator
6.0 MHz
XT2
Crystal resonator
32.768 kHz
330 kΩ
22 pF22 pF22 pF 22 pF
Page 47
10
5.0
1.0
0.5
DD
vs VDD (Main system clock : 4.19 MHz crystal resonator)
I
µ
PD75P0016
(TA = 25°C)
PCC = 0011
PCC = 0010 PCC = 0001 PCC = 0000
Main system clock HALT mode +32-kHz oscillation
(mA)
DD
0.1
Supply Current I
0.05
0.01
0.005
Subsystem clock operation mode (SOS.1 = 0)
Subsystem clock HALT mode (SOS.1 = 0) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 0)
Subsystem clock HALT mode (SOS.1 = 1) and main system clock STOP mode +32-kHz oscillation (SOS.1 = 1)
X1 X2 XT1
Crystal resonator
4.19 MHz
Crystal resonator
32.768 kHz
XT2
330 kΩ
22 pF22 pF22 pF 22 pF
0.001 012345678
Supply Voltage V
Data Sheet U10328EJ3V1DS00
DD
(V)
47
Page 48

11. PACKAGE DRAWINGS

42PIN PLASTIC SHRINK DIP (600 mil)
µ
PD75P0016
42
1
22
21
A
K
L
I
J
H
G
F
D
M
N
B
C
M
R
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition.
2) Item "K" to center of leads when formed parallel.
ITEM MILLIMETERS INCHES
A
39.13 MAX.
B
1.78 MAX.
C
1.778 (T.P.) D 0.50±0.10 0.020 F
0.9 MIN. G
3.2±0.3 H
0.51 MIN.
I
4.31 MAX.
J
5.08 MAX. K
15.24 (T.P.)
L 13.2 0.520 M 0.25 N
R
+0.10 –0.05
0.17 0~15° 0~15°
1.541 MAX.
0.070 MAX.
0.070 (T.P.) +0.004
–0.005
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.600 (T.P.)
+0.004
0.010
–0.003
0.007
P42C-70-600A-1
48
Data Sheet U10328EJ3V1DS00
Page 49
44 PIN PLASTIC QFP ( 10)
A B
µ
PD75P0016
34
33
23
22
CD
44
1
11
12
F
J
G
H
M
I
K
P
N
NOTE
Each lead centerline is located within 0.16 mm (0.007 inch) of its true position (T.P.) at maximum material condition.
L
detail of lead end
S
R
Q
M
ITEM MILLIMETERS INCHES
A 13.2±0.2 0.520
B 10.0±0.2
C 10.0±0.2
D 13.2±0.2 F
1.0
G
1.0
H
I
J K
L 0.8±0.2
M 0.17 0.007 N
P Q 0.125±0.075
R3° 3° S 3.0 MAX.
+0.08
0.37
–0.07
0.16
0.8 (T.P.)
1.6±0.2
+0.06 –0.05
0.10
2.7
+7° –3°
+0.008 –0.009
+0.008
0.394
–0.009 +0.008
0.394
–0.009 +0.008
0.520
–0.009
0.039
0.039 +0.003
0.015
–0.004
0.007
0.031 (T.P.)
0.063±0.008
+0.009
0.031
–0.008 +0.002
–0.003
0.004
0.106
0.005±0.003
+7° –3°
0.119 MAX.
S44GB-80-3BS
Data Sheet U10328EJ3V1DS00
49
Page 50
µ
PD75P0016

12. RECOMMENDED SOLDERING CONDITIONS

Solder the µPD75P0016 under the following recommended conditions. For the details on the recommended soldering conditions, refer to Information Document Semiconductor
Device Mounting Technology Manual (C10535E).
For the soldering methods and conditions other than those recommended, consult NEC.
Table 12-1. Soldering Conditions of Surface Mount Type
µ
PD75P0016GB-3BS-MTX: 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
Soldering method Soldering conditions recommended
Infrared reflow Package peak temperature: 235˚C, Time: 30 seconds max. (210˚C min.), IR35-00-3
Number of times: 3 max.
VPS Package peak temperature: 215˚C, Time: 40 seconds max. (200˚C min.), VP15-00-3
Number of times: 3 max.
Wave soldering Soldering bath temperature: 260˚C max., Time: 10 seconds max., WS60-00-1
Number of times: 1 Preheating temperature: 120˚C max. (package surface temperature)
Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per side of device) –
Symbol of
condition
Caution Do not use two or more soldering methods in combination (except the partial heating method).
Table 12-2. Soldering Conditions of Insertion Type
µ
PD75P0016CU: 42-pin plastic Shrink DIP (600 mil, 1.778-mm pitch)
Soldering method Soldering conditions
Wave soldering (pin only) Soldering bath temperature: 260˚C max., Time: 10 seconds max. Partial heating Pin temperature: 300˚C max., Time: 3 seconds max. (per pin)
Caution Apply wave soldering to the pins only. Be careful not to allow solder jet to come into direct
contact with the body of the chip.
50
Data Sheet U10328EJ3V1DS00
Page 51
µ
PD75P0016
APPENDIX A. FUNCTION LIST OF µPD75008, 750008, 75P0016
Item
Program memory Mask ROM Mask ROM One-time PROM
Data memory 000H - 1FFH
CPU 75X Standard CPU 75XL CPU General register 4 bits × 8 or 8 bits × 4 (4 bits × 8 or 8 bits × 4) × 4 banks Instruction When main system • 0.95, 1.91, 15.3 µs • 0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation)
execution clock is selected (at 4.19 MHz operation) • 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation) time
Stack SBS register None Yes SBS.3 = 1: Mk I mode selected
Instructions BRA !addr1 Unusable In Mk I mode: Unusable
Timer 3 channels 4 channels
Clock output (PCL) • Φ, 524, 262, 65.5 kHz • Φ, 524, 262, 65.5 kHz
BUZ output (BUZ) • 2 kHz • 2, 4, 32 kHz
When subsystem 122 µs (at 32.768 kHz operation) clock is selected
Stack area 000H - 0FFH n00H - nFFH (n = 0, 1) Stack operation of 2-byte stack In Mk I mode: 2-byte stack
subroutine call In Mk II mode: 3-byte stack instruction
CALLA !addr1 In Mk II mode: Usable MOVT XA, @BCDE Usable
MOVT XA, @BCXA BR BCDE BR BCXA
CALL !addr 3 machine cycles Mk I mode: 3 machine cycles
CALLF !faddr 2 machine cycles Mk I mode: 2 machine cycles
µ
PD75008
0000H - 1F7FH 0000H - 1FFFH 0000H - 3FFFH (8064 × 8 bits) (8192 × 8 bits) (16384 × 8 bits)
(512 × 4 bits)
• Basic interval timer: • Basic interval timer/watchdog timer: 1 channel 1 channel • 8-bit timer/event counter: 1 channel
• 8-bit timer/event counter: • 8-bit timer counter: 1 channel 1 channel • Watch timer: 1 channel
• Watch timer: 1 channel
(main system clock: (main system clock: at 4.19 MHz operation) at 4.19 MHz operation) • Φ, 750, 375, 93.8 kHz
µ
PD750008
SBS.3 = 0: Mk II mode selected
Mk II mode: 4 machine cycles
Mk II mode: 3 machine cycles
(main system clock: at 6.0 MHz operation)
(main system clock: at 4.19 MHz operation)
• 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation)
µ
PD75P0016
(1/2)
Data Sheet U10328EJ3V1DS00
51
Page 52
Item
Serial interface Compatible with 3 kinds of mode
SOS register Feedback resistor On-chip feedback resistor On chip
cut flag (SOS.0) specifiable by mask option Sub oscillator current None On chip
cut flag (SOS.1)
Register bank selection register None Yes (RBS)
Standby release by INT0 Not possible Possible Vectored interrupt External: 3 Internal: 3 External: 3 Internal: 4 Processor clock control register PCC = 0, 2, 3 can be used PCC = 0 to 3 can be used
(PCC) Supply voltage VDD = 2.7 to 6.0 V VDD = 2.2 to 5.5 V Operating ambient temperature TA = –40 to +85˚C Package • 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µ
PD75008
• 3-wire serial I/O mode ... MSB/LSB-first can be switched
• 2-wire serial I/O mode
• SBI mode
• 44-pin plastic QFP (10 × 10 mm, 0.8-mm pitch)
µ
PD750008
µ
PD75P0016
µ
PD75P0016
(2/2)
52
Data Sheet U10328EJ3V1DS00
Page 53
µ
PD75P0016

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are provided for system development using the µPD75P0016. The 75XL series uses
a common relocatable assembler, in combination with a device file matching each machine.
RA75X relocatable assembler Host machine Part number
OS Supply medium (product name)
PC-9800 series MS-DOS
IBM PC/AT or compatible IBM PCs
Device file Host machine Part number
PC-9800 series MS-DOS 3.5" 2HD
IBM PC/AT Refer to OS for 3.5" 2HC or compatible IBM PCs
TM
Refer to OS for 3.5" 2HC
TM
Ver.3.30 to
Note
Ver.6.2
OS Supply medium (product name)
Ver.3.30 to
Note
Ver.6.2
3.5" 2HD
µ
S5A13RA75X
µ
S7B13RA75X
µ
S5A13DF750008
µ
S7B13DF750008
Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swap function, but it does not work with this
software.
Remark The operation of the assembler and device file is guaranteed only on the above host machines and OSs.
Data Sheet U10328EJ3V1DS00
53
Page 54
PROM Write Tools
µ
PD75P0016
Hardware PG-1500 A stand-alone system can be configured of a single-chip microcomputer with on-chip PROM
PA-75P008CU This is a PROM programmer adapter for the µPD75P0016CU/GB. It can be used when
PA-75P0016GB This is a PROM programmer adapter for the µPD75P0016GB-3BS-MTX. It can be used when
Software PG-1500 controller Establishes serial and parallel connections between the PG-1500 and a host machine for host-
when connected to an auxiliary board (companion product) and a programmer adapter (separately sold). Alternatively, a PROM programmer can be operated on a host machine for programming. In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed.
connected to a PG-1500.
connected to a PG-1500.
machine control of the PG-1500. Host machine Part number
OS Supply medium (product name)
PC-9800 Series MS-DOS 3.5" 2HD
Ver.3.30 to
Note
Ver.6.2 IBM PC/AT Refer to OS for 3.5" 2HD or compatible IBM PCs
µ
S5A13PG1500
µ
S7B13PG1500
Note Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work with
this software.
Remark Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.
54
Data Sheet U10328EJ3V1DS00
Page 55
µ
PD75P0016
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P0016.
Various system configurations using these in-circuit emulators are listed below.
Hardware IE-75000-R
IE-75001-R The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during
IE-75300-R-EM This is an emulation board for evaluating application systems that use the µPD750008
EP-75008CU-R This is an emulation probe for the µPD75P0016CU.
EP-75008GB-R This is an emulation probe for the µPD75P0016GB.
Software IE control program This program can control the IE-75000-R or IE-75001-R on a host machine when connected to
Note 1
EV-9200G-44 When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during development of application systems that use 75X or 75XL Series products. For development of the µPD750008 subseries, the IE-75000-R is used with a separately sold emulation board IE­75300-R-EM and emulation probe EP-75008CU-R or EP-75008GB-R. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer. The IE-75000-R can include a connected emulation board (IE-75000-R-EM).
development of application systems that use 75X or 75XL Series products. The IE-75001-R is used with a separately sold emulation board (IE-75300-R-EM) and emulation probe EP­75008CU-R or EP-75008GB-R. These products can be applied for highly efficient debugging when connected to a host machine and PROM programmer.
subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
It includes a 44-pin conversion socket (EV-9200G-44) to facilitate connections with various target systems.
the IE-75000-R or IE-75001-R via an RS-232-C or Centronics I/F. Host machine Part number
OS Supply medium (product name)
PC-9800 series MS-DOS 3.5" 2HD
Ver.3.30 to
Note 2
Ver.6.2 IBM PC/AT Refer to OS for 3.5" 2HC or compatible IBM PCs
µ
S5A13IE75X
µ
S7B13IE75X
Notes 1. This is a service part provided for maintenance purpose only.
2. Ver. 5.00 and the upper versions of Ver. 5.00 are provided with a task swapping function, but it does not work
with this software.
Remarks 1. Operation of the IE control program is guaranteed only on the above host machine and OSs.
µ
2. The
PD75000 subseries consists of the µPD750004, 750006, 750008 and 75P00016.
Data Sheet U10328EJ3V1DS00
55
Page 56
µ
PD75P0016
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS Version
PC DOS
MS-DOS Ver.5.0 to Ver.6.22
IBM DOS
Note Supports English version only.
Caution Ver 5.0 and above include a task swapping function, but this software is not able to use that function.
TM
TM
Ver.3.1 to Ver.6.3
Note
J6.1/V
5.0/V J5.02/V
Note
Note
to J6.3/V
to J6.2/V
Note
Note
56
Data Sheet U10328EJ3V1DS00
Page 57
µ
PD75P0016

APPENDIX C. RELATED DOCUMENTS

Some of the following related documents are preliminary. This document, however, is not indicated as
preliminary.
Device Related Documents
Document name
µ
PD750004, 750006, 750008, 750004(A), 750006(A), 750008(A) U10738J U10738E
Data Sheet
µ
PD75P0016 Data Sheet U10328J This document
µ
PD750008 User’s Manual U10740J U10740E
µ
PD750008, 750108 Instruction List U11456J –
75XL Series Selection Guide U10453J U10453E
Japanese English
Document No.
Development Tool Related Documents
Document No.
Hardware
Software
Document name
IE-75000 R/IE-75001-R User’s Manual EEU-846 EEU-1416 IE-75300-R-EM User’s Manual U11354J U11354E EP-750008CU-R User’s Manual EEU-699 EEU-1317 EP-750008GB-R User’s Manual EEU-698 EEU-1305 PG-1500 User’s Manual U11940J U11940E RA75X Assembler Package Operation U12622J U12622E User’s Manual Language U12385J U12385E PG-1500 Controller User’s Manual PC-9800 Series EEU-704 EEU-1291
(MS-DOS) Base IBM PC Series EEU-5008 U10540E
(PC DOS) Base
Japanese English
Other Documents
Document name
SEMICONDUCTOR SELECTION GUIDE Products & Package (CD-ROM) Semiconductor Device Mounting Technology Manual C10535J C10535E Quality Grades on NEC Semiconductor Devices C11531J C11531E NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E Guide to Prevent Damage for Semiconductor Devices Electrostatic C11892J C11892E
Discharge (ESD) Guide for Products Related to Microcomputer : Other Companies C11416J –
Japanese English
X13769X
Document No.
Caution The above related documents are subject to change without notice. For design purpose, etc.,
be sure to use the latest documents.
Data Sheet U10328EJ3V1DS00
57
Page 58
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools includ­ing work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
µ
PD75P0016
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immedi­ately after power-on for devices having reset function.
58
Data Sheet U10328EJ3V1DS00
Page 59
µ
PD75P0016
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Madrid Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP Brasil Tel: 55-11-6462-6810 Fax: 55-11-6462-6829
Data Sheet U10328EJ3V1DS00
J00.7
59
Page 60
µ
PD75P0016
QTOP is a trademark of NEC Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
•
The information in this document is current as of August, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.
•
No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
•
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.
•
Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.
•
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features.
•
NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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