Page 1
Document No. IC-2763B
(O. D. No. IC-7628D)
Date Published November 1993 P
Printed in Japan
NEC Corporation 1990
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75328
4-BIT SINGLE-CHIP MICROCOMPUTER
The mark ★ shows the major revised points.
DESCRIPTION
The µPD75328 is one of the 75X Series 4-bit single-chip microcomputer, and has a data processing
capability comparable to that of an 8-bit microcomputer.
In addition to high-speed operation with 0.95
µ
s minimum instruction execution time for the CPU, the
µ
PD75328 can also process data in 1-, 4-, and 8-bit units. Therefore, as a 4-bit single-chip microcomputer
chip having a built-in LCD controller/driver and A/D converter, its data processing capability is the highest
in its class in the world.
The
µ
PD75P328 with one-time PROM, which is replaced with the internal mask ROM for a µPD75328,
is applicable for evaluating systems under development, or for small-scale production of developed
systems.
"Detailed functions are described in the following user's manual. Be sure to read it for designing."
"
µPD75328 User's Manual: IEM-5045"
FEATURES
• Capable of high-speed operation and variable instruction execution time to power save
• 0.95
µ
s, 1.91 µs, 15.3 µs (Main system clock: operating at 4.19 MHz)
• 122
µ
s (Subsystem clock: operating at 32.768 kHz)
• 75X architecture comparable to that for an 8-bit microcomputer is employed
• Built-in programmable LCD controller/driver
• Built-in 8-bit resolution A/D converter:
6 channels
• Clock operation at reduced power dissipation: 5
µ
A TYP. (operating at 3 V)
• Timer function: 3 channels
• Interrupt functions especially enhanced for applications, such as remote control receiver
• Pull-up resistors can be provided for 35 I/O lines
• Built-in NEC standard serial bus interface (SBI)
APPLICATIONS
Cameras, blood pressure gauges, airconditioners, etc.
The information in this document is subject to change without notice.
ORDERING INFORMATION
Part Number Package Quality Grade
µ
PD75328GC-xxx-3B9 80-pin plastic QFP (■■14mm) Standard
Remarks: xxx is ROM code number.
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209)
published by NEC Corporation to know the specification of quality grade on the devices and its
recommended applications.
Page 2
2
µ
PD75328
Including the pins
which also serve
as LCD drive pins.
Excluding the
pins which is
specifically provided for driving
LCD.
FUNCTIONAL OUTLINE (1/2)
Item Function
Number of Basic 41
Instructions
Instruction 0.95, 1.91, and 15.3 µs, (Main system clock: operating at 4.19 MHz)
Execution Time 122 µs (Subsystem clock: operating at 32.768 kHz)
ROM 8064 × 8-bit
RAM 512 × 4-bit
General-Purpose 4-bit manipulation: 8×4 banks, 8-bit manipulation: 4×4 banks
Registers
I/O Line 8 CMOS Input pins Internal pull-up resistor
specification by software
44 20 CMOS input/output pins is possible (except P00).
8 CMOS output pins Also serve as segment pins
8 N-ch open-drain Withstand voltage: 10V
input/output Internal pull-up resistor
specification by mask option
is possible.
LCD Controller/ • LCD drive output pins
Driver • Segment output pins: 20 (CMOS output pins: 8)
• Common output pins: 4
• Capable of driving up to 20 × 4 segments
• Display output mode: Static, 1/2, 1/3, 1/4 duty
A/D Converter 8-bit resolution x 6 channels (successive approximation type)
• Operating voltage VDD = 3.5 to 6.0 V
• A/D conversion speed 40.1 µs (operating at 4.19 MHz)
8-bit timer/event counter
• Clock source: 4 steps
• Event count is possible
8-bit basic interval timer
Timer 3 chs • Reference time generation (1.95, 7.82, 31.3, 250 ms: operating at 4.19
MHz)
• Can be used as watchdog timer
Clock timer
• 0.5 second interval generation
• Count clock source slectable (4.19 MHz/32.768 kHz)
• Clock advance mode (3.9 ms time interval generation)
• Buzzer output (2 kHz)
Clock synchronized serial interface
Serial • Internal NEC standard serial bus interface (SBI mode)
Interface • 3-line serial I/O mode ... MSB/LSB first selectable
• 2-line serial I/O mode
Bit Sequential Special bit manipulation memory: 16 bits
Buffer
Clock Output Φ, 524, 262, 65.5 kHz (Main system clock: 4.19 MHz)
(PCL)
Buzzer Output 2 kHz (with main system clock or subsystem clock operated)
(BUZ)
Vector Interrupt • External: 3
• Internal: 3
Test Input • External: 1
• Internal: 1
Internal
Memory
Page 3
3
µ
PD75328
FUNCTIONAL OUTLINE (2/2)
Item Function
System Clock • Main system clock generation ceramic/crystal oscillator; 4.194304 MHz
Generator • Subsystem clock generation crysal oscillator: 32.768 kHz
Standby STOP/HALT mode
Operating –40 to +85°C
Temperature Range
Operating Supply VDD = 2.7 to 6.0 V
Voltage
Package 80-pin plastic QFP (■■14 mm)
Page 4
4
µ
PD75328
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ........................................................................................ 6
2. BLOCK DIAGRAM ......................................................................................................................7
3. PIN FUNCTIONS ........................................................................................................................8
3.1 PORT PINS ........................................................................................................................................8
3.2 NON PORT PINS ............................................................................................................................ 10
3.3 PIN INPUT/OUTPUT CIRCUITS ................................................................................................... 12
3.4 RECOMMENDED PROCESSING OF UNUSED PINS.................................................................. 14
3.5 SELECTION OF MASK OPTION ................................................................................................... 15
3.6 NOTES ON USING THE P00/INT4, AND RESET PINS .............................................................. 15
4. MEMORY CONFIGURATION ................................................................................................. 16
5. PERIPHERAL HARDWARE FUNCTIONS ............................................................................... 18
5.1 PORTS ............................................................................................................................................. 18
5.2 CLOCK GENERATOR CIRCUIT ..................................................................................................... 19
5.3 CLOCK OUTPUT CIRCUIT............................................................................................................. 20
5.4 BASIC INTERVAL TIMER .............................................................................................................. 21
5.5 WATCH TIMER ............................................................................................................................... 22
5.6 TIMER/EVENT COUNTER............................................................................................................. 22
5.7 SERIAL INTERFACE....................................................................................................................... 24
5.8 LCD CONTROLLER/DRIVER ......................................................................................................... 26
5.9 A/D CONVERTER .......................................................................................................................... 28
5.10 BIT SEQUENTIAL BUFFER .... 16 BITS ....................................................................................... 29
6. INTERRUPT FUNCTIONS ......................................................................................................... 29
7. STANDBY FUNCTIONS............................................................................................................ 31
8. RESET FUNCTION .................................................................................................................... 32
9. INSTRUCTION SET ................................................................................................................. 34
10. ELECTRICAL SPECIFICATIONS ............................................................................................. 40
11. CHARACTERISTIC CURVES (REFERENCE VALUE) ............................................................ 53
12. PACKAGE DRAWINGS ........................................................................................................... 59
13. RECOMMENDED SOLDERING CONDITIONS ...................................................................... 61
Page 5
5
µ
PD75328
APPENDIX A. COMPARISON OF FEATURES BETWEEN PD75328 AND PD75308 ........62
APPENDIX B. DEVELOPMENT TOOLS...................................................................................... 63
APPENDIX C. RELATED DOCUMENTS ..................................................................................... 64
µµ
Page 6
6
µ
PD75328
P00-P03 : Port 0 AVSS : Analog Ground
P10-P13 : Port 1 AN0-AN5 : Analog Input 0-5
P20-P23 : Port 2 S12-S31 : Segment Output 12-31
P30-P33 : Port 3 COM0-COM3 : Command Output 0-3
P40-P43 : Port 4 V
LC0-VLC2 : LCD Power Supply 0-2
P50-P53 : Port 5 BIAS : LCD Power Supply Bias Control
P60-P63 : Port 6 LCDCL : LCD Clock
P70-P73 : Port 7 SYNC : LCD Synchronization
P80-P83 : Port 8 TI0 : Timer Input 0
BP0-BP7 : Bit Port PTO0 : Programmable Timer Output 0
KR0-KR7 : Key Return BUZ : Buzzer Clock
SCK : Serial Clock PCL : Programmable Clock
SI : Serial Input INT0,INT1,INT4 : External Vectored Interrupt 0,1,4
SO : Serial Output INT2 : External Test Input 2
SB0,SB1 : Serial Bus 0,1 X1,X2 : Main System Clock Oscillation 1,2
RESET : Reset Input XT1,XT2 : Subsystem Clock Oscillation 1,2
AV
REF : Analog Reference NC : No Connection
1. PIN CONFIGURATION (Top View)
S31/BP7
COM0
AN2
P73/KR7
PD75328GC– –3B9×××
µ
P72/KR6
P71/KR5
P70/KR4
P63/KR3
P62/KR2
P61/KR1
P60/KR0
RESETX2X1NCXT2
XT1
VDDAVREF
AVSS
AN5
AN4
AN3
COM1
COM2
COM3
BIAS
VLC0
VLC1
VLC2
P40
P41
P42
P43
SSV
P50
P51
P52
P53
P00/INT4
P01/SCK
P02/SO/SB0
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
S30/BP6
S29/BP5
S28/BP4
S27/BP3
S26/BP2
S25/BP1
S24/BP0
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AN1
AN0
P83
P82
P81
P80
P33
P32
P31/SYNC
P30/LCDCL
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
Page 7
7
µ
PD75328
2. BLOCK DIAGRAM
AN0–AN5 6
AV
REF
AV
SS
TI0/P13
A/D
CONVERTER
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
INTT0
PTO0/P20
BUZ/P23
WATCH
TIMER
INTW f
LCD
INTCSI
CLOCKED
SERIAL
INTERFACE
SI/SB1/P03
SO/SB0/P02
SCK/P01
PROGRAM
COUNTER (13)
ALU
CY
SP (8)
BANK
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60
–KR7/P73
8
INTERRUPT
CONTROL
BIT SEQ.
BUFFER (16)
PROGRAM
MEMORY
(ROM)
8064 8 BITS
×
DECODE
AND
CONTROL
GENERAL REG.
DATA
MEMORY
(RAM)
512 4 BITS
×
f /2
X
N
VDDVSSRESET
PCL/P22 XT1 XT2 X1 X2
SUB MAIN
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
STAND BY
CONTROL
CPU
CLOCK
f
LCD
SYNC/P31
LCDCL/P30
BIAS
V -V
LC0 LC2
3
LCD
CONTROLLER
/DRIVER
4
8
12
COM0-COM3
S24/BP0
-S31/BP7
S12-S23
PORT 8
P80-P834
PORT 7
P70-P734
PORT 6
P60-P634
PORT 5
P50-P534
PORT 4
P40-P434
PORT 3
P30-P334
PORT 2
P20-P234
PORT 1
P10-P134
PORT 0
P00-P034
Page 8
8
µ
PD75328
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Input/
Output
Circuit
TYPE*
1
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30*
2
P31*
2
P32*
2
P33*
2
P40-43*
2
P50-53*
2
Pin Name
Input/Output Function 8-Bit I/O When Reset
Also Served
As
INT4
SCK
SO/SB0
SO/SB1
INT0
INT1
INT2
TI0
PTO0
—
PCL
BUZ
LCDCL
SYNC
—
—
—
—
4-bit input port (PORT0)
Pull-up resistors can be specified in 3-bit
units for the P01 to P03 pins by software.
With noise elimination function
4-bit input port (PORT1)
Internal pull-up resistors can be
specified in 4-bit units by software.
4-bit input/output port (PORT2)
Internal pull-up resistors can be
specified in 4-bit units by software.
Programmable 4-bit input/output port
(PORT3)
This port can be specified for input/
output in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.
N-ch open-drain 4-bit input/output port
(PORT4)
Internal pull-up resistors can be
specified in bit units. (mask option)
Resistive voltage is 10 V in the opendrain mode.
N-ch open-drain 4-bit input/output port
(PORT5)
Internal pull-up resistors can be
specified in bit units. (mask option)
Resistive voltage is 10 V in the opendrain mode.
Input
Input
Input
Input
High level
(with internal
pull-up
resistor) or
high impedance
B
B -C
E-B
E-B
M
M
X
X
X
X
*1: Circles indicate Schmitt trigger inputs.
2: Can directly drive LED.
Input
Input/
Output
Input/
Output
Input/
Output
Input
Input/
Output
Input/
Output
Input/
Output
Input/
Output
●●
F -A
M -C
F -B
High level
(with internal
pull-up
resistor) or
high impedance
Page 9
µ
PD75328
P60
P61
P62
P63
P70
P71
P72
P73
P80
P81
P82
P83
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
—
S24
S25
S26
S27
S28
S29
S30
S31
●●
Input/
Output
Input/
Output
Input/
Output
Output
Output
Also Served
As
Programmable 4-bit input/output port
(PORT6)
This port can be specified for input/
output in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.
Input
F -A
4-bit input/output port (PORT7)
Internal pull-up resistors can be
specified in 4-bit units by software.
Input
F -A
Pin Name Input/Output Function 8-Bit I/O When Reset
4-bit input/output port (PORT8)
Internal pull-up resistors can be
specified in 4-bit units by software.
X
Input
E-B
1-bit output port (BIT PORT)
Shared with a segment output pin.
X
*2
G-C
*1: Circles indicate schmidt trigger inputs.
2: For BP0-7, V
LC1 indicated below are selected as the input source. However, the output level is
changed depending on BP0-7 and the V
LC1 external circuits.
Example: Since BP0-7 are connected to each other within the µPD75328 as shown in the diagram below,
the output level of BP0-7 depends on the sizes of R
1, R2 and R3.
PD75328
µ
ON
ON
BP
BP
V
DD
R
2
R
3
V
LC1
R
1
1
0
9
3.1 PORT PINS (2/2)
Input/
Output
Circuit
TYPE*
1
Page 10
10
µ
PD75328
Parallel falling edge detection testable input/output
Parallel falling edge detection testable input/output
Segment signal output
Segment signal output
Common signal output
LCD drive power
Step-down resistor network (mask option)
External expanded driver for disconnect output
Externally expanded driver for clock output
Externally expanded driver sync clock output
6-bit analog input for A/D converter
A/D converter reference voltage input
GND potential for A/D converter reference voltage
input. Connected to VSS.
TI0
PTO0
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0-KR3
KR4-KR7
S12-S23
S24-S31
COM0-
COM3
VLC0-VLC2
BIAS
LCDCL*
3
SYNC*
3
AN0-AN5
AVREF
AVSS
Input
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input
Input
Input
Input/
Output
Input/
Output
Output
Output
Output
—
Output
Input/
Output
Input/
Output
Input
Input
—
P13
P20
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60-P63
P70-P73
—
BP0-7
—
—
—
P30
P31
—
—
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
*4
*4
*4
—
*5
Input
Input
Input
Input
—
B -C
E-B
E-B
E-B
F -A
F -B
M -C
B
B -C
B -C
F -A
F -A
G-A
G-C
G-B
—
E-B
E-B
Y
Z
—
Pin Name Input/Output
Also Served
As
Functon When Reset
Input/
Output
Circuit
TYPE*
1
3.2 NON PORT PINS
Timer/event counter external event pulse Input
Timer/event counter output
Clock output
Fixed frequency output (for buzzer or for trimming the system clock)
Serial clock input/output
Serial data output
Serial bus input/output
Serial data input
Serial bus input/output
Edge detection vector interrupt input (both
rising and falling edge detection are effective)
Edge detection vector
interrupt input (detection
edge can be selected)
Edge detection testable
input (rising edge detection)
Clock synchronous
Asynchronous
Asynchronous
Page 11
µ
PD75328
Also Served
As
To connect the crystal/ceramic oscillator to
the main system clock generator. When
inputting the external clock, input the
external clock to pin X1, and the reverse
phase of the external clock to pin X2.
To connect the crystal oscillator to the
subsystem clock generator.
When the external clock is used, pin XT1
inputs the external clock. In this case, pin
XT2 must be left open.
Pin XT1 can be used as a 1-bit input pin.
System reset input
No connection
Positive power supply
GND
X1, X2
—
——
—
XT1, XT2
—
—
—
—
Input
—
—
—
RESET
NC *
2
VDD
VSS
—
B
—
—
—
—
—
—
—
*1: Circles indicate schmidt trigger inputs.
2: When sharing the printed circut board with the
µ
PD75P328, the NC pin must be connected to
V
DD.
3: These pins are provided for future system expansion. At present, these pins are used only as
pins P30 and P31.
4: For these display output, V
LCX indicated below are selected as the input source.
S12 to S31: V
LC1, COM0 to COM2: VLC2, COM3: VLC0
However, display output level varies depending on the particular display output and VLCX
external circuit.
Example: Since BP0-7 are connected to each other within the µPD75328 as shown in the diagram
below, the output level of BP0-7 depends on the size of R
1, R2 and R3.
5: Step-down resistor network provided : Low level
Step-down resistor network not provided : High impedance
—
—
—
PD75328
µ
ON
ON
BP
BP
V
DD
R
2
R
3
V
LC1
R
1
1
0
11
Pin Name Input/Output Function When Reset
(cont'd)
Input/
Output
Circuit
TYPE*
1
Page 12
12
µ
PD75328
3.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the
µ
PD75328.
TYPE A (for TYPE E–B)
TYPE D (for TYPE E –
B, F
TYPE B
TYPE E–B
IN
V
DD
P–ch
N–ch
Input buffer of CMOS standard
data
output
disable
OUT
P–ch
N–ch
Push–pull output that can be set in a output
high–impedance state (both P–ch and N–ch are off)
IN
Schmitt trigger input with hysteresis characteristics
data
output
disable
Type D
Type A
P.U.R.
enable
V
DD
P.U.R.
P–ch
IN/OUT
P.U.R. : Pull–Up Resistor
P.U.R.
enable
V
DD
P.U.R.
P–ch
TYPE B–C
TYPE F–A
IN
data
output
disable
Type D
Type B
P.U.R.
enable
V
DD
P.U.R.
P–ch
IN/OUT
P.U.R. : Pull–Up ResistorP.U.R. : Pull
–Up Resistor
Schmitt trigger input with hysteresis characteristics
A)
–
VDD
Page 13
13
µ
PD75328
P-ch
TYPE M–C
data
output
disable
P.U.R.
enable
V
DD
P.U.R.
IN/OUT
P–ch
N-ch
TYPE F–B
TYPE M
data
output
disable
P.U.R.
enable
V
DD
IN/OUT
Middle voltage input buffer
(resistive voltage: +10 V)
P.U.R. : Pull–Up Resistor
data
output
disable
P.U.R.
enable
V
DD
P.U.R.
P–ch
N-ch
P-ch
output
disable
(P)
output
disable
(N)
V
DD
(Mask option)
P.U.R. : Pull–Up Resistor
IN/OUT
TYPE G–C
TYPE G–A
P.U.R. : Pull–Up Resistor
TYPE G–B
V
DD
V
LC0
V
LC0
V
LC1
V
LC2
SEG
data/Bit Port data
P-ch
N-ch
OUT
N-ch
V
LC1
V
LC2
P-ch
P-ch
N-ch
OUT
N-ch
V
LC0
V
LC1
V
LC2
P-ch
N-ch
SEG
data
COM
data
OUT
P-ch N-ch
N-ch P-ch
N-ch
Page 14
14
µ
PD75328
Pin Recommended Connections
P00/INT4 Connect to VSS
P01/SCK
P02/SO/SB0 Connect to VSS or VDD
P03/SI/SB1
P10/INT0-P12/INT2
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30-P33 Input : Connect to VSS or VDD
P40-P43 Output: Open
P50-P53
P60-P63
P70-P73
P80-P83
S12-S23
S24/BP0-S31/BP7 Open
COM0-COM3
VLC0-VLC2 Connect to VSS
BIAS Connect to VSS only when All of the VLC0-VLC2
pins are unused, otherwise, open.
XT1 Connect to VSS or VDD
XT2 Open
AVREF Connect to VSS
AVSS Connect to VSS
AN0-AN5 Connect to VSS or VDD
3.4 RECOMMENDED PROCESSING OF UNUSED PINS
Connect to VSS
TYPE Y
N–ch
IN
P–ch
AV
SS
V
DD
V
DD
AV
SS
Sampling
C
+
–
input
enable
Reference voltage
(from a voltage tap of series
resistor string)
TYPE Z
IN
AV
SS
Reference voltage
Page 15
15
µ
PD75328
3.5 SELECTION OF MASK OPTION
The following mask operations are available and can be specified for each pin.
Table 3-1 Mask Option Selection
Pin Mask Option Remarks
P40-P43,
P50-P53
With voltage dividing Without voltage dividing Specification in 4-bit
resistor for LCD drive resistor for LCD drive units
power source power source
With feed back resistor Without feed back resistor
XT1, XT2 (when using the subsystem (when using the subsystem
clock) clock)
With pull-up resistor Without pull-up resistor
Specification in bit units
3.6 NOTES ON USING THE P00/INT4, AND RESET PINS
In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test
mode, in which the internal fuctions of the µPD75328 are tested, is provided to the P00/INT4 and RESET
pins.
If a voltage exceeding VDD is applied to either of these pins, the µPD75328 is put into test mode.
Therefore, even when the
µ
PD75328 is in normal operation, if noise exceeding the VDD is input into any
of these pins, the
µ
PD75328 will enter the test mode, and this will cause problems for normal operation.
As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked
up and the above montioned problem may occur.
Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise
cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below.
• Connect a diode having a low V
F across
P00/INT4 and RESET, and V
DD.
• Connect a capacitor across P00/INT4 and
RESET, and VDD.
VLC0-VLC2
BIAS
VDD
VDD
P00/INT4, RESET
VDD
VDD
P00/INT4, RESET
Low VF
diode
★
Page 16
16
µ
PD75328
Fig. 4-1 Program Memory Map
4. MEMORY CONFIGURATION
• Program memory (ROM) ... 8064 words × 8 bits
• 0000H, 0001H : Vector table to which address from which program is started is written after reset
• 0002H-000BH : Vector table to which address from which program is started is written after interrupt
• 0020H-007FH : Table area referenced by GETI instruction
• Data memory
• Data area .... 512 words × 4 bits (000H–1FFH)
• Peripheral hardware area .... 128 words × 4 bits (F80H–FFFH)
765
MBE 0 0
MBE 0 0
MBE 0 0
MBE 0 0
MBE 0 0
MBE 0 0
Internal reset start address (upper 5 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (upper 5 bits)
INTBT/INT4 start address (lower 8 bits)
INT0 start address (upper 5 bits)
INT0 start address (lower 8 bits)
INT1 start address (upper 5 bits)
INT1 start address (lower 8 bits)
INTCSI start address (upper 5 bits)
INTCSI start address (lower 8 bits)
INTT0 start address (upper 5 bits)
INTT0 start address (lower 8 bits)
0000H
0002H
0004H
0006H
0008H
000AH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1F7FH
GETI instruction reference table
0
BRCB
! caddr
instruction
branch
address
CALLF
!faddr
instruction
entry
address
BR ! addr
instruction
branch address
CALL ! addr
instruction
subroutine
entry address
BR $addr
instruction
relational
branch address
(–15 to –1,
+2 to +16)
Branch destination
address and
subroutine entry
address for
GETI instruction
Address
Page 17
17
µ
PD75328
Data area
Static RAM
(512 x 4)
Stack area
(8 x 4)
000H
007H
256 x 4
(248 x 4)
0FFH
100H
1EBH
Bank 0
256 x 4
(236 x 4)
Not provided
128 x 4
F80H
FFFH
Peripheral hardware area
Bank 15
Bank 1
(20 x 4)
1ECH
1FFH
General-purpose
register
area
Display
data
memory
008H
Fig. 4-2 Data Memory Map
Page 18
18
µ
PD75328
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
I/O ports are classified into the following 4 kinds:
• CMOS input (PORT0, 1) : 8
• CMOS input/output (PORT2, 3, 6, 7, and 8) : 20
• CMOS output (BP0-BP7) : 8
• N-ch open-drain input/output (PORT4, 5) : 8
Total : 44
Table 5-1 Port Function
Remarks
Multiplexed with INT4,
SCK, SO/SB0, and SI/SB1
Multiplexed with INT0INT2 and TI0
Multiplexed with PTO0,
PCL, and BUZ
Multiplexed with KR4-KR7
—
Multiplexed with LCDCL
and SYNC
Multiplexed with KR0-KR3
Can be connected to a
pull-up resistor in 1-bit
units by using mask
option.
—
Port Name
PORT0
PORT1
PORT2
PORT7
PORT8
PORT3
PORT6
PORT4
*
PORT5
*
BP0-BP7
Function
4-bit input
4-bit Input/Output
4-bit Input/Output
(N-ch open-drain,
10 V)
1-bit output
Operation and Feature
Can be always read or tested regardless of
operation mode of multiplexed pin.
Can be set in input or output mode in 4-bit units.
Ports 6 and 7 are used in pairs to input/output data
in 8-bit units.
Can be set in input or output mode in 1-bit units.
Can be set in input or output mode in 4-bit units.
Ports 4 and 5 are used in pairs to input/output data
in 8-bit units.
Output data in 1-bit units. Can be used as LCD drive
segment output pins S24-S31 through software.
*: Can directly drive LED.
Page 19
19
µ
PD75328
5.2 CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control regiser (PPC)
and system clock control register (SCC).
This circuit can generate two types of clocks: main system clock and subsystem clock.
In addition, it can also change the instruction execution time.
• 0.95
µ
s, 1.91 µs, 15.3 µs (main system clock: 4.19 MHz)
• 122
µ
s (subsystem clock: 32.768 kHz)
*: instruction execution.
Remarks 1: f
X = Main system clock frequency
2: f
XT = Subsystem clock frequency
3: Φ= CPU clock
4: PCC: Processor clock control register
5: SCC: System clock control register
6: One clock cysle (t
CY) of Φ is one machine cycle of an instruction. For tCY, refer to AC
characteristics in 10. ELECTRICAL SPECIFICATIONS.
Fig. 5-1 Clock Generator Block Diagram
VDD
VDD
XT1
XT2
X1
X2
f
XT
fX
LCD controller
/driver
Watch timer
Subsystem
clock
oscillator
Main system
clock
oscillator
1/2 1/16
1/8 to 1/4096
Frequency divider
· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· LCD controller/driver
· A/D converter
· INT0 noise rejecter circuit
· Clock output circuit
Internal bus
WM.3
SCC
SCC3
SCC0
PCC
PCC0
PCC1
PCC2
PCC3
HALT*
STOP*
4
PCC2, PCC3
clear signal
STOP F/F
QS
R
Q
S
R
HALT F/F
Oscillator
disable
signal
Frequency
divider
1/4
Selector
Selector
Φ
· CPU
· INT0 noise
rejecter circuit
· Clock output
circuit
Wait release
signal from BT
RESET signal
Standby release
signal from interrupt
control circuit
★
Page 20
20
µ
PD75328
5.3 CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the
remote control output, peripheral LSIs, etc.
Fig. 5-2 Clock Output Circuit Configuration
Remarks:
A measures to prevent outputting narrow width pulse when selecting clock output
enable/disable is taken.
Selector
Output
buffer
PCL/P22
Bit 2 of PMGBPORT2.2
Port 2 input/
output mode
specification
bit
P22 output
latch
Internal bus
CLOM3 0 CLOM1 CLOM0 CLOM
4
Φ
f
X
/2
3
fX/2
4
fX/2
6
From the
clock
generator
Page 21
21
µ
PD75328
5.4 BASIC INTERVAL TIMER
The µPD75328 is provided with the 8-bit basic interval timer. The basic interval timer has these functions:
• Interval timer operation which generates a reference time interrupt
• Watchdog timer application which detects a program runaway
• Selects the wait time for releasing the standby mode and counts the wait time
• Reads out the count value
From the
clock generator
f
X
/2
5
fX/2
7
fX/2
9
fX/2
12
MPX
Clear
Basic interval timer
(8-bit frequency divider circuit)
3
4
8
BT
Clear
Set
signal
BT
interrupt
request flag
IRQBT
Wait release signal
for standby release
Vector
interrupt
request
signal
Internal bus
BTM3 BTM2 BTM1 BTM0 BTM
SET1*
Remarks
: *: Instruction execution
Fig. 5-3 Basic Interval Timer Configuration
Page 22
22
µ
PD75328
5.5 WATCH TIMER
The
µ
PD75328 has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4.
• Sets the test flag (IRQW) with 0.5 sec interval.
The standby mode can be released by IRQW.
• 0.5 second interval can be generated either from the main system clock or subsystem clock.
• Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is
convenient for program debugging, test, etc.
• Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system
clock frequency trimming.
• The frequency divider circuit can be cleared so that zero second watch start is possible.
( ) is for f
X = 4.194304 MHz, fXT = 32.768 kHz.
Fig. 5-4 Watch Timer Block Diagram
5.6 TIMER/EVENT COUNTER
The
µ
PD75328 has a built-in 1-ch timer/event counter. The timer/even counter has these functions:
• Programmable interval timer operation
• Outputs square-wave signal of an arbitrary frequency to the PTO0 pin.
• Event counter operation
• Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation).
• Supplies serial shift clock to the serial interface circuit.
• Count condition read out function
WM7 0 0 0 WM3 WM2 WM1 WM0
Selector Frequency divider
f
W
2
6
(512 Hz: 1.95 ms)
f
W
2
7
(256 Hz: 3.91 ms)
f
LCD
INTW
(IRQW
set signal)
f
W
2
14
(2 Hz
0.5 sec)
Selector
f
W
(32.768
kHz)
f
W
16
(2.048
kHz)
Clear
f
X
128
(32.768 kHz)
f
XT
(32.768 kHz)
From the
clock
generator
WM PORT2.3 Bit 2 of PMGB
Output buffer
P23/BUZ
P23
output
latch
Port 2
input/output
mode
Bit test
instruction
8
Internal bus
Page 23
23
µ
PD75328
Internal bus
88 SET1*
TM07 TM06 TM05 TM04 TM03 TM02 TM01 TM00
TM0
PORT1.3
Input
buffer
P13/TI0
From the
clock
generator
MPX
*:Instruction execution
Timer operation start signal
CP
8
8
Modulo register (8)
Comparator (8)
Count register (8)
Clear
T0
TMOD0
Reset
TOE0 PORT2.0
Bit 2 of PGMB
To serial interface
P20/PTO0
INTT0
IRQT0
set signal
()
RESET
IRQT0
clear signal
Output
buffer
TOUT
F/F
TO
enable
flag
P20
output
latch
Port 2
input/
output
mode
Coincidence
8
Fig. 5-5 Timer/Event Counter Block Diagram
Page 24
24
µ
PD75328
5.7 SERIAL INTERFACE
The
µ
PD75328 is equipped with an 8-bit clocked serial interface that operates in the following four
modes:
• Operation stop mode
• Three-line serial I/O mode
• Two-line serial I/O mode
• SBI mode (serial bus interface mode)
Page 25
25
µ
PD75328
Internal bus
8/4
8
88
CSIM
P03/SI/SB1
P02/SO/SB0
P01/SCK
P01
output
latch
Selector Selector
Bit
test
Slave address register
(SVA)
Address comparator
Shift register (SIO)
SET CLR
Bit manipulation
(8)
(8)
Coincidence
signal
SBIC
RELT
CMDT
SO latch
Bit test
ACKT
ACKE
BSYE
Busy/
acknowledge
output
circuit
Bus release/
command/
acknowledge
detector
circuit
RELD
CMDD
ACKD
Serial clock
counter
Serial clock
control
circuit
INTCSI
control
circuit
Serial clock
selector
I
NTCSI
IRQCSI
set signal
(
)
DQ
f
X
/2
3
fX/2
4
fX/2
6
TOUT F/F
(from timer/
event counter)
External SCK
(8)
Fig. 5-6 Serial Interface Block Diagram
Page 26
26
µ
PD75328
5.8 LCD CONTROLLER/DRIVER
The
µ
PD75328 is provided with a display controller that generates segment and common signals and
a segment driver and a common driver that can directly drive an LCD panel. These LCD controller and
drivers have the following functions:
• Generate segment and common signals by automatically reading the display data memory by
means of DMA
• Five display modes selectable
• Static
• 1/2 duty (divided by 2), 1/2 bias
• 1/3 duty (divided by 3), 1/2 bias
• 1/3 duty (divided by 3), 1/3 bias
• 1/4 duty (divided by 4), 1/3 bias
• Four types of frame frequencies selectable in each display mode
• Up to 20 segment signals (S12-S31) and four common signals (COM0-COM3) can be output.
• Four segment signal output pins (S24-S27, S28-S31) can be used as an output port (BP0-BP3, BP4-
BP7).
• Dividing resistor for LCD driving power source can be provided (by mask option).
• All bias modes and LCD drive voltages can be used.
• Current flowing to dividing resistor can be cut when display is off.
• Display data memory not used for display can be used as ordinary data memory.
• Can also operate on subsystem clock.
Page 27
27
µ
PD75328
Internal bus
1FFH
3210
Display
data
memory
3210
1FEH
3210
3210
1F9H
3210
3210
1F8H
3210
3210
1ECH
3210
3210
Multiplexer
Selector
S31/BP7
Common driver
S30/BP6 S24/BP0 S23 S12 COM3 COM2 COM1COM0 V P31/
SYNC
LC2VLC1VLC0
LCD driving
voltage control
P30/
LCDCL
Timing
controller
f
LCD
Display mode register
Display
control
register
Port 3 output latch
10
Port mode register group A
10
48448
Fig. 5-7 LCD Controller/Driver Block Diagram
Segment driver
Page 28
28
µ
PD75328
5.9 A/D CONVERTER
The
µ
PD75328 is provided with an 8-bit resolution analog-to-digital (A/D) converter with six channels
of analog inputs (AN0-AN5).
This A/D converter is of a successive approximation type.
AN0
AN1
AN2
AN3
AN4
AN5
AV
REF
AV
SS
Multiplexer
Sample hold circuit
+
–
Tap decoder
R/2 R/2RR R
Serial resistor string
8
8
SA register (8)
Control circuit
Internal bus
0
ADM6 ADM5 ADM4 SOC EOC
ADM1 0
ADM
Comparator
8
Fig. 5-8 Block Diagram of A/D Converter
Page 29
29
µ
PD75328
5.10 BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore,
this buffer is very useful for processing long data in bit units.
Remarks:
For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 5-9 Bit Sequential Buffer Format
6. INTERRUPT FUNCTIONS
The µPD75328 has 6 different interrupt sources and multiplexed interrupt with priority order.
In addition to that, the
µ
PD75328 is also provided with two types of test sources, of which INT2 has
two types of edge detection testable inputs.
The interrupt control circuit of the µPD75328 has these functions:
• Hardware controlled vector interrupt function which can control whether or not to accept an
interrupt by using the interrupt flag (IExxx) and interrupt master enable flag (IME).
• The interrupt start address can be arbitrarily set.
• Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means
of software).
• Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
Address bit
Symbol
L register
3210321032103210
L = F L = C L = B L = 8 L = 7 L = 4 L = 3 L = 0
BSB3 BSB2 BSB1 BSB0
DECS L
INCS L
FC3H FC2H FC1H FC0H
Page 30
30
µ
PD75328
Internal bus
213
IM2 IM1 IM0
IRQBT
INT4
/P00
INT0
/P10
INT1
/P11
INT2
/P12
KR0/P60
KR7/P73
Noise
elimination
circuit
INT
BT
INTCSI
INTT0
INTW
Selector
Both edge
detection
circuit
Edge
detection
circuit
Edge
detection
circuit
Rising edge
detection
circuit
Falling edge
detection
circuit
IRQ4
IRQ0
IRQ1
IRQCSI
IRQT0
IRQW
IRQ2
IM2
Interrupt enable flag (IE )×××
IME
VRQn
Decoder
IST0
Priority control
circuit
Vector table
address
generator
Standby
release signal
Fig. 6-1 Interrupt Control Block Diagram
Page 31
31
µ
PD75328
7. STANDBY FUNCTIONS
The µPD75328 has two different standby modes (STOP mode and HALT mode) to reduce the power
consumption while waiting for program execution.
Table 7-1 Each Status in Standby Mode
Setting Instruction STOP instrtuction HALT instruction
Can be set only when operating on
the main system clock
Can be set either with the main
system clock or the subsystem clock
Operation
Status
Clock Generator Only the main system clock stops its
operation.
Only the CPU clock Φ stops its
operation. (oscillation continues)
Basic Interval
Timer
No operation Can operate only when main system
clock oscillates (Sets IRQBT at
reference time interval)
Serial Interface Can operate only when the external
SCK input is selected for the serial
clock
Can operate only when main system
clock oscillates, or when external
SCK input is selected as serial clock
Timer/Event
Counter
Can operate only when the TI0 pin
input is selected for the count clock
Can operate only when main system
clock oscillates, or when TI0 pin
input is selected as count clock
Watch Timer Can operate when fXT is selected as
the count clock
Can operate
Release Signal An interrupt request signal from a
hardware whose operation is
enabled by the interrupt enable flag
or the RESET signal input
An interrupt request signal from a
hardware whose operation is
enabled by the interrupt enable flag
or the RESET signal input
Item
Mode
STOP Mode
HALT Mode
LCD controller Can operate only when fXT is
selected as LCDCL
Can operate
A/D Convertor No operation Can operate only when the main
system clock is operating.
External Interrupt INT1, INT2, and INT4 can operate.
Only INT0 can not operate.
CPU No operation
System Clock for Setting
Page 32
32
µ
PD75328
8. RESET FUNCTION
When the RESET signal is input, the µPD75328 is reset and each hardware is initialized as indicated
in Table 8-1. Fig. 8-1 shows the reset operation timing.
RESET input
Wait
(31.3ms/4.19MHz)
Operation mode
or standby mode
HALT mode Operation mode
Internal reset operation
Fig. 8-1 Reset Operation by RESET Input
Table 8-1 Status of Each Hardware after Reset (1/2)
Hardware RESET Input in Standby Mode RESET Input during Operation
Program Counter (PC) The contents of the lower 5 bits
of address 0000H of the program
memory are set to PC12-8, and
the contents of address 0001H
are set to PC7-0.
The contents of the lower 5 bits
of address 0000H of the program
memory are set to PC12-8, and
the contents of address 0001H
are set to PC7-0.
PSW Carry Flag (CY) Retained Undefined
Skip Flag (SK0-2) 0 0
Interrupt Status Flag (IST0) 0 0
Bank Enable Flag (MBE) The contents of bit 7 of address
0000H of the program memory
are set to MBE.
The contents of bit 7 of address
0000H of the program memory
are set to MBE.
Stack Pointer (SP) Undefined Undefined
Data Memory (RAM) Retained *
1
Undefined
General-Purpose Register
(X, A, H, L, D, E, B, C)
Retained Undefined
Bank Selection Register (MBS) 0 0
Basic Interval
Timer
Counter (BT) Undefined Undefined
Timer/Event
Counter
Counter (T0) 0 0
Module Register
(TMOD0)
FFH
FFH
Mode Register (TM0) 0 0
TOE0, TOUT F/F 0, 0 0, 0
Mode Register (BTM) 0 0
Mode Register (WM) 0
Watch Timer
0
Page 33
33
µ
PD75328
Serial Shift Register (SIO) Retained Undefined
Interface
Operation Mode 0 0
Register (CSIM)
SBI Control Register 0 0
(SBIC)
Slave Address Register Retained Undefined
(SVA)
Clock Processor Clock Control 0 0
Generator, Register (PCC)
Clock Output
System Clock Control 0 0
Circuit
Register (SCC)
Clock Output Mode 0 0
Register (CLOM)
LCD Display Mode Register 0 0
Controller (LCMD)
Display Control 0 0
Register (LCDC)
A/D Converter Mode Regiseter (ADM), 04H (EOC = 1) 04H (EOC = 1)
EOC
SA Register 7FH 7FH
Interrupt Interrupt Request Flag Reset (0) Reset (0)
Function (IRQxxx)
Interrupt Enable Flag 0 0
(IExxx)
Interrupt Master Enable 0 0
Flag (IME)
INT0, INT1, INT2 Mode 0, 0, 0 0, 0, 0
Registers (IM0, 1, 2)
Digital Port Output Buffer Off Off
Output Latch Clear (0) Clear (0)
Input/Output Mode 0 0
Register (PMGA, B, C)
Pull-Up Resistor 0 0
Specification Register
(POGA, B)
Pin States P00-P03, P10-P13, Input Input
P20-P23, P30-P33,
P60-P63, P70-P73,
P80-P83
P40-P43, P50-P53 • Internal pull-up resistors Same as at left
... High level
• Open drain
... High impedance
S12-S23, *2 *2
COM0-COM3
BIAS • Internal step-down resistors Same as at left
... Low level
• External step-down resistors
... High impedance
Bit Sequential Buffer (BSB0-3) Retained Specified
Hardware RESET Input during OperationRESET Input in Standby Mode
Table 8-1 Status of Each Hardware after Reset (2/2)
Page 34
34
µ
PD75328
*1: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is
input.
2: Select VLCX as shown below as the input source for each display output.
S12-31 : V
LC1
COM0-2 :VLC2
COM3 : VLC0
However, the level of each display output varies according to the display output and the external
circuit for V
LCX.
9. INSTRUCTION SET
(1) Operand representation and description
Describe one or more operands in the operand field of each instruction according to the operand
representation and description methods of the instruction (for details, refer to RA75X Assembler
Package User's Manual - Language (EEU-730)). With some instructions, only one operand should
be selected from several operands. The uppercase characters, +, and – are keywords and must be
described as is.
Describe an appropriate numeric value or label as immediate data.
Representation Description
reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L
rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rpa HL, DE, DL
rpa1 DE, DL
n4 4-bit immediate data or label
n8 8-bit immediate data or label
mem 8-bit immediate data or label
bit 2-bit immediate data or label
fmem FB0H to FBFH,FF0H to FFFH immediate data or label
pmem FC0H to FFFH immediate data or label
addr 0000H to 1F7FH immediate data or label
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label
taddr 20H to 7FH immediate data (where bit0 = 0) or label
PORTn PORT0 to PORT8
IExxx IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW
MBn MB0, MB1, MB15
Page 35
35
µ
PD75328
(2) Legend of operation field
A : A register; 4-bit accumulator
B : B register; 4-bit accumulator
C : C register; 4-bit accumulator
D : D register; 4-bit accumulator
E : E register; 4-bit accumulator
H : H register; 4-bit accumulator
L : L register; 4-bit accumulator
X : X register; 4-bit accumulator
XA : Register pair (XA); 8-bit accumulator
BC : Register pair (BC); 8-bit accumulator
DE : Register pair (DE); 8-bit accumulator
HL : Register pair (HL); 8-bit accumulator
PC : Program counter
SP : Stack pointer
CY : Carry flag; or bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
PORTn : Port n (n = 0 to 8)
IME : Interrupt mask enable flag
IExxx : Interrupt enable flag
MBS : Memory bank selector register
PCC : Processor clock control register
.
: Delimiter of address and bit
(xx) : Contents addressed by xx
xxH : Hexadecimal data
Page 36
36
µ
PD75328
(3) Symbols in addressing area field
*1 MB = MBE . MBS
(MBS = 0, 1, 15)
*2 MB = 0
*3 MBE = 0 : MB = 0 (00H-7FH) Data memory
MB = 15 (80H-FFH) addressing
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4 MB = 15, fmem = FB0H-FBFH,
FF0H-FFFH
*5 MB = 15, pmem = FC0H-FFFH
*6 addr = 000H-1F7FH
*7 addr = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
Program
*8 caddr = 0000H-0FFFH (PC12 = 0) or memory
1000H-1F7FH (PC12 = 1) addressing
*9 faddr = 0000H-07FFH
*10 taddr = 0020H-007FH
Remarks 1: MB indicates memory bank that can be accessed.
2: In *2, MB = 0 regardless of MBE and MBS.
3: In *4 and *5, MB = 15 regardless of MBE and MBS.
4: *6 to *10 indicate areas that can be addressed.
(4) Machine cycle field
In this field, S indicates the number of machine cycles required when an instruction having a skip
function skips. The value of S varies as follows:
• When no instruction is skipped .................................................................................. S = 0
• When 1-byte or 2-byte instruction is skipped ........................................................... S = 1
• When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ............................ S = 2
Note
: The GETI instruction is skipped in one machine cycle.
One machine cycle equals to one cycle of the CPU clock Φ, (=tCY), and can be changed in three
steps depending on the setting of the processor clock control register (PCC).
Page 37
37
µ
PD75328
Ma- Ad-
Instruc- Mne-
Operand Bytes
chine
Operation
dress- Skip
tions monics Cyc- ing Conditions
les Area
Transfer MOV A, #n4 1 1 A ← n4 String effect A
reg1, #n4 2 2 reg1 ← n4
XA, #n8 2 2 XA ← n8 String effect A
HL, #n8 2 2 HL ← n8 String effect B
rp2, #n8 2 2 rp2 ← n8
A, @HL 1 1 A ← (HL) *1
A, @rpa1 1 1 A ← (rpa1) *2
XA, @HL 2 2 XA ← (HL) *1
@HL, A 1 1 (HL) ← A*1
@HL, XA 2 2 (HL) ← XA *1
A,mem 2 2 A ← (mem) *3
XA, mem 2 2 XA ← (mem) *3
mem, A 2 2 (mem) ← A*3
mem, XA 2 2 (mem) ← XA *3
A, reg 2 2 A ← reg
XA, rp 2 2 XA ← rp
reg1, A 2 2 reg1 ← A
rp1, XA 2 2 rp1 ← XA
XCH A, @HL 1 1 A ↔ (HL) *1
A, @rpa1 1 1 A ↔ (rpa1) *2
XA, @HL 2 2 XA ↔ (HL) *1
A, mem 2 2 A ↔ (mem) *3
XA, mem 2 2 XA ↔ (mem) *3
A, reg1 1 1 A ↔ reg1
XA, rp 2 2 XA ↔ rp
MOVT XA, @PCDE 1 3 XA ← (PC12-8+DE)ROM
XA, @PCXA 1 3 XA ← (PC12-8+XA)ROM
Arith- ADDS A, #n4 1 1+S A ← A+n4 carry
metic A, @HL 1 1+S A ← A+(HL) *1 carry
Opera- ADDC A, @HL 1 1 A, CY ← A+(HL)+CY *1
tion SUBS A, @HL 1 1+S A ← A-(HL) *1 borrow
SUBC A, @HL 1 1 A, CY ← A-(HL)-CY *1
AND A, #n4 2 2 A ← A ∧ n4
A, @HL 1 1 A ← A ∧ (HL) *1
OR A, #n4 2 2 A ← A ∨ n4
A, @HL 1 1 A ← A ∨ (HL) *1
XOR A, #n4 2 2 A ← A ∨ n4
A, @HL 1 1 A ← A ∨ (HL) *1
Accumu- RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An
lator
Manipu-
NOT A 2 2 A ← A
lation
Page 38
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PD75328
Ma- Ad-
Instruc- Mne-
Operand Bytes
chine
Operation
dress- Skip
tions monics Cyc- ing Conditions
les Area
Incre- INCS reg 1 1+S reg ← reg+1 reg = 0
ment/ @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0
Decre- mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0
ment DECS reg 1 1+S reg ← reg-1 reg = FH
Compare SKE reg, #n4 2 2+S Skip if reg = n4 reg = n4
@HL, #n4 2 2+S Skip if (HL) = n4 *1(HL) = n4
A, @HL 1 1+S Skip if A = (HL) *1 A = (HL)
A, reg 2 2+S Skip if A = reg A = reg
Carry SET1 CY 1 1 CY ← 1
flag CLR1 CY 1 1 CY ← 0
Manipu- SKT CY 1 1+S Skip if CY = 1 CY = 1
lation NOT1 CY 1 1 CY ← CY
Memory/ SET1 mem.bit 2 2 (mem.bit) ← 1*3
Bit fmem.bit 2 2 (fmem.bit) ← 1 *4
Manipu- pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 1*5
lation @H+mem.bit 2 2 (H + mem3-0.bit) ← 1*1
CLR1 mem.bit 2 2 (mem.bit) ← 0 *3
fmem.bit 2 2 (fmem.bit) ← 0 *4
pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 0*5
@H+mem.bit 2 2 (H+mem3-0.bit) ← 0*1
SKT mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1
fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1
pmem.@L 2 2+S
Skip if (pmem
7-2+L3-2
.bit (L
1-0
)) = 1
*5 (pmem.@L) = 1
@H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 1 *1
(@H+mem.bit) = 1
SKF mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0
fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0
pmem.@L 2 2+S
Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0
*5 (pmem.@L) = 0
@H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 0 *1
(@H+mem.bit) = 0
SKTCLR
fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1
pmem.@L 2 2+S Skip if (pmem7-2+L3-2.bit *5 (pmem.@L) = 1
(L1-0)) = 1 and clear
@H+mem.bit 2 2+S
Skip if (H+mem3-0.bit) = 1 and clear
*1
(@H+mem.bit) = 1
AND1 CY,fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4
CY,pmem.@L 2 2
CY ← CY ∧ (pmem7-2+L3-2.bit(L1-0))
*5
CY,@H+mem.bit
2 2 CY ← CY ∧ (H+mem3-0.bit) *1
OR1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4
CY,pmem.@L 2 2
CY ← CY ∨ (pmem7-2+L3-2.bit (L1-0))
*5
CY,@H+mem.bit
2 2 CY ← CY ∨ (H+mem3-0.bit) *1
XOR1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4
CY,pmem.@L 2 2
CY ← CY
∨
(pmem7-2+L3-2.bit (L1-0))
*5
CY,@H+mem.bit
2 2 CY ← CY ∨ (H+mem3-0.bit) *1
Page 39
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PD75328
Ma- Ad-
Instruc- Mne-
Operand Bytes
chine
Operation
dress- Skip
tions monics Cyc- ing Conditions
les Area
Branch BR addr — — PC12-0 ← addr *6
(The most suitable instruction
is selectable from among BR
!addr, BRCB !caddr, and BR
$addr depending on the
assembler.)
!addr 3 3 PC12-0 ← addr *6
$addr 1 2 PC12-0 ← addr *7
BRCB !caddr 2 2 PC11-0 ← caddr11-0 *8
Subrou- CALL !addr 3 3 (SP-4)(SP-1)(SP-2) ← PC11-0 *6
tine/ (SP-3) ← MBE, 0, 0, PC12
Stack
PC12-0 ← addr, SP ← SP-4
Control
CALLF !faddr 2 2 (SP-4)(SP-1)(SP-2) ← PC11-0 *9
(SP-3) ← MBE, 0, 0, PC12
PC12-0 ← 00, faddr, SP ← SP-4
RET 1 3 MBE, x, x, PC12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
SP ← SP+4
RETS 1 3+S MBE, x, x, PC12 ← (SP+1) Undefined
PC11-0 ← (SP)(SP+3)(SP+2)
SP ← SP+4,
then skip unconditionally
RET1 1 3 MBE, x, x, PC12 ← (SP+1)
PC11-0 ← (SP)(SP+3)(SP+2)
PSW ← (SP+4)(SP+5), SP ← SP+6
PUSH rp 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2
BS 2 2
(SP-1) ← MBS, (SP-2) ← 0, SP ← SP-2
POP rp 1 1 rp ← (SP+1)(SP), SP ← SP+2
BS 2 2 MBS ← (SP+1), SP ← SP+2
Inter- EI 2 2 IME ← 1
rupt IExxx 2 2 IExxx ← 1
Control DI 2 2 IME ← 0
IExxx 2 2 IExxx ← 0
I/O IN *1A,PORTn 2 2 A ← PORTn (n = 0-8)
XA,PORTn 2 2
XA
←
PORTn+1,PORTn
(n = 4, 6)
OUT *1PORTn,A 2 2 PORTn ← A (n = 2-8)
PORTn,XA 2 2 PORTn+1,PORTn ← XA (n = 4, 6)
CPU HALT 2 2 Set HALT Mode (PCC.2 ← 1)
Control STOP 2 2 Set STOP Mode (PCC.3 ← 1)
NOP 1 1 No Operation
Special SEL MBn 2 2 MBS ← n (n = 0, 1, 15)
GETI *2taddr 1 3
.
Where TBR instruction, *10
PC12-0 ← (taddr)4-0+(taddr+1)
.
Where TCALL instruction,
(SP-4)(SP-1)(SP-2) ← PC11-0
(SP-3) ← MBE, 0, 0, PC12
PC12-0 ← (taddr)4-0+(taddr+1)
SP ← SP-4
.
Except for TBR and TCALL Depends on
instructions, referenced
Instruction execution of instruction
(taddr)(taddr+1)
*1: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.
2: The TBR, and TCALL instructions are the assembler pseudo-instructions for the table definition of
GETI instruction.
......................................................... .............................
......................................................... .............................
Page 40
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PD75328
10. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Parameter Symbol Conditions Ratings Unit
Supply Voltage VDD -0.3 to +7.0 V
VI1 Other than ports 4, 5 -0.3 to VDD+0.3 V
Input Voltage VI2 Ports 4, 5 w/pull-up -0.3 to VDD+0.3
V
resistor
Open drain -0.3 to +11 V
Output Voltage VO -0.3 to VDD+0.3 V
High-Level Output IOH 1 pin -15 mA
Current
All pins -30 mA
Low-Level Output IOL* 1 pin Peak 30 mA
Current rms 15 mA
Other than ports 0, 2, 3, 5, 8 Peak 100 mA
rms 60 mA
Total of ports 4, 6, 7 Peak 100 mA
rms 60 mA
Operating Temperature Topt -40 to +85 °C
Storage Temperature Tstg -65 to +150 °C
*: rms = Peak value x √Duty
CAPACITANCE (T
a = 25°C, VDD = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input Capacitance CIN f = 1 MHz 15 pF
Output Capacitance COUT Pins other than thosemeasured are at 0 V 15 pF
Input/Output CIO
15 pF
Capacitance
OPERATING SUPPLY VOLTAGE
Parameter Symbol Conditions MIN. MAX. Unit
A/D Converter Supply voltage VDD 3.5 6.0 V
Ambient temperature Ta -10 +70 °C
Other Circuits Supply voltage VDD 2.7 6.0 V
Ambient temperatuare Ta -40 +85 °C
Page 41
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PD75328
MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(T
a = -40 to +85°C, VDD = 2.7 to 6.0 V)
Oscillator
Recommended
Item Conditions MIN. TYP. MAX. Unit
Constants
Ceramic *
3
Oscillation
1.0 5.0
*
4
MHz
frequency(fXX)*
1
Oscillation stabiliza- After VDD came to
tion time*
2
MIN. of oscillation
voltage range
4ms
Crystal *
3
Oscillation
1.0 4.19 5.0
*
4
MHz
frequency (fXX)*
1
Oscillation stabiliza- VDD = 4.5 to 6.0 V 10 ms
tion time*
2
30 ms
External Clock X1 input frequency
1.0 5.0
*
4
MHz
(fX)*
1
X1 input high-,
low-level widths
(tXH, tXL) 100 500 ns
*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics
of the oscillator circuit.
For instruction execution time, refer to AC Characteristics.
2: Time required for oscillation to stabilize after V
DD reaches the minimum value of the oscillation
voltage range or the STOP mode has been released.
3: The oscillators on the next page are recommended.
4: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the
instruction execution time: otherwise, one machine cycle is set to less than 0.95
µ
s, falling short
of the rated minimum value of 0.95
µ
s.
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(T
a = -40 to +85°C, VDD = 2.7 to 6.0 V)
Oscillator
Recommended
Item Conditions MIN. TYP. MAX. Unit
Constants
Crystal Oscillation
32 32.768 35 kHz
frequency (fXT)
Oscillation stabiliza- VDD = 4.5 to 6.0 V 1.0 2 s
tion time*
10 s
External Clock XT1 input frequency
32 100 kHz
(fXT)*
XT1 input high-,
low-level widths 5 15
µ
s
(tXTH, tXTL)
X1 X2
C1 C2
V
DD
X1 X2
C1 C2
V
DD
X1 X2
PD74HCU04
µ
★
XT1 XT2
R
C3 C4
V
DD
XT1 XT2
Open
Page 42
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PD75328
*: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation voltage
range.
Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion
enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity:
• Keep the wiring length as short as possible.
• Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines
through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillator circuit at the same potential as
VDD. Do not connect the power source pattern through which a high current flows.
• Do not extract signals from the oscillation circuit.
The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce
the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise
more easily than the main system clock oscillation circuit. When using the subsystem clock,
therefore, exercise utmost care in wiring the circuit.
RECOMMENDED OSCILLATION CIRCUIT CONSTANTS
MAIN SYSTEM CLOCK: CERAMIC OSCILLATOR (T
a = -40 to +85°C)
CSAx.xxMG093 30 30 2.7
CSTx.xxMG093 Unnecessary Unnecessary 2.7
CSAx.xxMGU 30 30 2.7
CSTx.xxMGU Unnecessary Unnecessary 2.7
CSAx.xxMG 30 30 3.0
CSTx.xxMG Unnecessary Unnecessary 3.0
KBR-2.0MS 2.00 47 47 2.7
KBR-4.0MS 4.00 33 33 2.7
KBR-5.0M 5.00 33 33 3.0
C1 (pF)
Murata
Mfg.
Co., Ltd.
Frequency
(MHz)
Product Name
Manufacturer
Kyoto
Ceramic
Co., Ltd.
MAX. (V)MIN. (V)
Recommended Circuit
Constants
Operating
Voltage Range
2.00 to 2.44
2.45 to 5.00
2.00 to 5.00
6.0
6.0
C2 (pF)
P3 32.768 22 * 22 330 2.7
C3 (pF)
Kinseki
Frequency
(MHz)
Product Name
Manufacturer
MAX. (V)MIN. (V)
Recommended Circuit
Constants
Operating
Voltage Range
6.0
SUBSYSTEM CLOCK: CRYSTAL OSCILLATOR (Ta = -10 to +60°C)
C4 (pF)
R (kΩ)
*: Adjust the oscillation frequency in a range of C3 = 3 to 30 pF.
HC-18U 2.0 to 5.0 22 * 22 2.7
HC-43U, 49/U
C1 (pF)
Kinseki
Frequency
(MHz)
Product Name
Manufacturer
MAX. (V)MIN. (V)
Recommended Circuit
Constants
Operating
Voltage Range
6.0
C2 (pF)
*: Adjust the oscillation frequency in a range of C1 = 15 to 33 pF.
MAIN SYSTEM CLOCK: CRYSTAL OSCILLATOR (Ta = -20 to +70°C)
Page 43
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PD75328
DC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-Level Input VIH1 Ports 2, 3, 8 0.7VDD VDD V
Voltage
VIH2 Ports 0, 1, 6, 7, RESET 0.8VDD VDD V
VIH3 Ports 4, 5 w/pull-up resistor 0.7VDD VDD V
Open-drain 0.7VDD 10 V
VIH4 X1, X2, XT1 VDD-0.5 VDD V
Low-level Input VIL1 Ports 2, 3, 4, 5, 8 0 0.3VDD V
Voltage
VIL2 Ports 0, 1, 6, 7, RESET 0 0.2VDD V
VIL3 X1, X2, XT1 0 0.4 V
High-Level Output VOH1 VDD = 4.5 to 6.0 V VDD-1.0 V
Voltage IOH = -1 mA
IOH = -100 µAVDD-0.5 V
VOH2 VDD = 4.5 to 6.0 V VDD-2.0 V
IOH = -100 µA
IOH = -50 µAVDD-1.0 V
Low-Level Output VOL1 Ports 3, 4, and 5
0.4 2.0 V
Voltage VDD = 4.5 to 6.0 V
IOL = -15 mA
VDD = 4.5 to 6.0 V 0.4 V
IOL = 1.6 mA
IOL = 400 µA 0.5 V
SB0, 1 Open-drain Pull-up
0.2VDD V
resistor ≥ 1 kΩ
VOL2 VDD = 4.5 to 6.0 V 1.0 V
IOL = 100 µA
IOL = 50 µA 1.0 V
High-Level Input ILIH1 VIN = VDD Other than below 3
µ
A
Leakage Current
ILIH2 X1, X2, XT1 20
µ
A
ILIH3 VIN = 10 V Ports 4, 5
20
µ
A
(open-drain)
Low-Level Input ILIL1 VIN = 0 V Other than below -3
µ
A
Leakage Current
ILIL2 X1, X2, XT1 -20
µ
A
High-Level Output ILOH1 VOUT = VDD Other than below 3
µ
A
Leakage Current
ILOH2 VOUT = 10 V Ports 4, 5
20
µ
A
(open-drain)
Low-Level Output ILOL VOUT = 0 V
-3
µ
A
Leakage Current
Internal Pull-Up Resistor RL1
Ports 0, 1, 2, 3, 6, 7, 8
VDD = 5.0 V±10% 15 40 80 kΩ
(except P00) V
IN
= 0V
VDD = 3.0 V±10% 30 300 kΩ
RL2 Ports 4, 5 VDD = 5.0 V±10% 15 40 70 kΩ
V
OUT
= VDD-2.0 V
VDD = 3.0 V±10% 10 60 kΩ
LCD Drive Voltage VLCD 2.5 VDD V
LCD Step-down Resistor RLCD 60 100 140 kΩ
LCD Output Voltage VODC IO = ±5 µA0±0.2 V V
Deviation (Common) *
1
LCD Output Voltage VODS IO = ±1 µA0±0.2 V V
Deviation (Segment) *
1
Ports 0, 2, 3, 4, 5,
6, 7, and 8
BP0-7
(with two IOH
outputs)
Ports 0, 2, 3, 6, 7,
8, and BIAS
BP0-7
(with two IOL
outputs)
VLCD0 = VLCD
VLCD1 = VLCD×2/3
VLCD2 = VLCD×1/3
2.7 V ≤ VLCD ≤ VDD
Page 44
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PD75328
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply Current *2IDD1 4.19 MHz*3 crystal VDD = 5 V±10%*
4
2.5 8 mA
oscillator
VDD = 3 V±10%*
5
0.35 1.2 mA
IDD2
C1 = C2 = 22pF
HALT mode VDD = 5 V± 10% 500 1500µA
VDD = 3 V±10% 150 450
µ
A
IDD3 32 kHz*6 crystal Operation VDD = 3 V±10%
30 90
µ
A
oscillator mode
IDD4 HALT mode VDD = 3 V±10% 5 15
µ
A
IDD5 XT1 = 0 V VDD = 5 V±10% 0.5 20
µ
A
STOP mode
V
DD
= 3 V±10%
0.1 10
µ
A
Ta = 25°C 0.1 5
µ
A
*1: "Voltage deviation" means the difference between the ideal segment or common output value
(V
LCDn: n = 0, 1, 2) and output voltage.
2: Currents for the built-in pull-up resistor and the LCD step-down resistor are not included.
3: Including when the subsystem clock is operated.
4: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.
5: When operated in the low-speed mode with the PCC set to 0000.
6: When operated with the subsystem clock by setting the system clock control register (SCC) to 1011
to stop the main system clock operation.
Page 45
45
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PD75328
A/D CONVERTER (Ta = -10 to +85°C, VDD = 3.5 to 6.0 V, AVSS = VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 8 8 8 bit
Absolute Accuracy*
1
2.5 V ≤ AVREF ≤ VDD*
2
±1.5 LSB
Conversion Time tCONV *
3
168/fX S
Sampling Time tSAMP *
4
44/fX S
Analog Input Voltage VIAN AVSS AVREF V
Analog Input Impedance RAN 1000 MΩ
AVREF Current IREF 0.25 2.0 mA
*1: Absolute accuracy excluding quantization error (±1–2LSB)
2: Set ADM1 as follows, in respect to the reference voltage of the AD converter (AV
REF).
ADM1 can be set to either 0 or 1 when 0.6V
DD ≤ AVREF ≤ 0.65VDD
3: Time since execution of conversion start instruction until EOC = 1 (fX = 4.19 MHz: 40.1 µs)
4: Time since execution of conversion start instruction until end of sampling (f
X = 4.19 MHz: 10.5
µ
s)
2.5 V 0.6 V
DD
0.65 V
DD
VDD(3.5 to 6.0 V)
ADM1=0
ADM1=1
AV
REF
Page 46
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PD75328
AC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CPU Clock Cycle Time tCY w/main system clock VDD = 4.5 to 6.0 V 0.95 64
µ
s
(Minimum Instruction
3.8 64
µ
s
Execution Time
w/sub-system clock
114 122 125
µ
s
= 1 Machine Cycle)*
1
TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz
0 275 kHz
TI0 Input High-, Low- tTIH,VDD = 4.5 to 6.0 V 0.48
µ
s
Level Widths t
TIL
1.8
µ
s
Interrupt Input High-, tINTH, INT0 *2
µ
s
Low-Level Widths t
INTL
INT1, 2, 4 10
µ
s
KR0-7 10
µ
s
RESET Low-Level Width tRSL 10
µ
s
*1: The CPU clock (Φ) cycle time is
determined by the oscillation frequency
of the connected oscillator, system clock
control register (SCC), and processor
clock control register (PCC).
The figure on the right is cycle time t
CY
vs. supply voltage VDD characteristics
at the main system clock.
2: 2tCY or 128/fX depending on the setting
of the interrupt mode register (IM0).
0123 456
0.5
1
2
3
4
5
6
30
Supply voltage V
DD [V]
Cycle time tCY [ s]
tCY vs VDD
(with main system clock)
µ
64
70
Page 47
47
µ
PD75328
SERIAL TRANSFER OPERATION
Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY1 VDD = 4.5 to 6.0 V 1600 ns
3800 ns
SCK High-, Low-Level tKL1 VDD = 4.5 to 6.0 V tKCY1/2-50 ns
Widths
tKH1 tKCY1/2-150 ns
SI Set-Up Time (vs. SCK ↑) tSIK1 150 ns
SI Hold Time (vs. SCK ↑ )tKSI1 400 ns
SCK ↓→ SO Output tKSO1 RL = 1 kΩ,VDD = 4.5 to 6.0 V 250 ns
Delay Time CL = 100 pF*
1000 ns
*: RL and CL are load resistance and load capacitance of the SO output line.
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY2 VDD = 4.5 to 6.0 V 800 ns
3200 ns
SCK High-, Low-Level tKL2 VDD = 4.5 to 6.0 V 400 ns
Widths
tKH2 1600 ns
SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns
SI Hold Time (vs. SCK ↑)tKSI2 400 ns
SCK ↓→ SO Output tKSO2 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 300 ns
Delay Time
1000 ns
*: RL and CL are load resistance and load capacitance of the SO output line.
Page 48
48
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PD75328
SBI MODE (SCK: internal clock output (master))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY3 VDD = 4.5 to 6.0 V 1600 ns
3800 ns
SCK High-, Low-Level tKL3 VDD = 4.5 to 6.0 V tKCY3/2-50 ns
Widths t
KH3
tKCY3/2-150 ns
SB0, 1 Set-Up Time tSIK3
150 ns
(vs. SCK ↑ )
SB0, 1 Hold Time tKSI3
tKCY3/2 ns
(vs. SCK ↑ )
SCK ↓← SB0, 1 Output tKSO3 RL = 1 kΩ,VDD = 4.5 to 6.0 V 0 250 ns
Delay Time CL = 100 pF*
0 1000 ns
SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns
SB0,1 ↓→ SCK tSBK tKCY3 ns
SB0, 1 Low-Level Width tSBL tKCY3 ns
SB0, 1 High-Level Width tSBH tKCY3 ns
*: RL and CL are load resistance and load capacitance of the SO output line.
SBI MODE (SCK: external clock input (slave))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY4 VDD = 4.5 to 6.0 V 800 ns
3200 ns
SCK High-, Low-Level tKL4 VDD = 4.5 to 6.0 V 400 ns
Widths tKH4
1600 ns
SB0, 1 Set-Up Time tSIK4
100 ns
(vs. SCK ↑ )
SB0, 1 Hold Time tKSI4
tKCY4/2 ns
(vs. SCK ↑ )
SCK ↓← SB0, 1 Output tKSO4 RL = 1 kΩ,VDD = 4.5 to 6.0 V 0 300 ns
Delay Time CL = 100 pF*
0 1000 ns
SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns
SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns
SB0, 1 Low-Level Width tSBL tKCY4 ns
SB0, 1 High-Level Width tSBH tKCY4 ns
*: RL and CL are load resistance and load capacitance of the SO output line.
Page 49
49
µ
PD75328
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
X1 input
V
DD
–0.5V
0.4 V
t
XL
t
XH
1/f
X
XT1 input
V
DD
–0.5V
0.4 V
t
XTL
t
XTH
1/f
XT
TI0
t
TIL
t
TIH
1/f
TI
CLOCK TIMING
TI0 TIMING
Test points
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Page 50
50
µ
PD75328
SERIAL TRANSFER TIMING
THREE-LINE SERIAL I/O MODE:
SCK
t
KL1
t
KH1
t
KCY1
Output data
t
SIK1
t
KSI1
t
KSO1
Input data
SI
SO
TWO-LINE SERIAL I/O MODE:
SCK
t
KL2
t
KH2
t
KCY2
t
SIK2
t
KSI2
t
KSO2
SB0,1
Page 51
51
µ
PD75328
SERIAL TRANSFER TIMING
BUS RELEASE SIGNAL TRANSFER:
COMMAND SIGNAL TRANSFER:
SCK
t
KL3,4
t
KCY3,4
t
SIK3,4
t
KSI3,4
t
KSO3,4
SB0,1
t
KH3,4
t
SBK
t
KSB
INTERRUPT INPUT TIMING:
INT0, 1, 2, 4
KR0-7
t
INTL
t
INTH
RESET INPUT TIMING:
RESET
t
RSL
SCK
t
KL3,4
t
KCY3,4
t
SIK3,4
t
KSI3,4
t
KSO3,4
SB0,1
t
KH3,4
t
SBK
t
SBH
t
SBL
t
KSB
Page 52
52
µ
PD75328
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(T
a = –40 to +85 °C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data Retention Supply VDDDR
2.0 6.0 V
Voltage
Data Retention Supply IDDDR VDDDR = 2.0 V
0.1 10
µ
A
Current*
1
Release Signal Set Time tSREL 0
µ
s
Oscillation Stabilization tWAIT Released by RESET 217/fX ms
Wait Time*
2
Released by interrupt *3 ms
*1: Does not include current flowing through internal pull-up resistor
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent
unstable operation when oscillation is started.
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 BTM2 BTM1 BTM0 WAIT time ( ): fXX = 4.19 MHz
–0002
20
/fXX (approx. 250 ms)
–0112
17
/fXX (approx. 31.3 ms)
–1012
15
/fXX (approx. 7.82 ms)
–1112
13
/fXX (approx. 1.95 ms)
DATA RETENTION TIMING (releasing STOP mode by RESET)
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
STOP mode
Data retention mode
STOP instruction
execution
V
DD
RESET
V
DDDR
t
SREL
t
WAIT
Operation
mode
Internal reset operation
HALT mode
STOP mode
Data retention mode
STOP instruction execution
V
DD
V
DDDR
t
SREL
t
WAIT
Operation
mode
HALT mode
Standby release signal
(interrupt request)
Page 53
53
µ
PD75328
11. CHARACTERISTIC CURVES (REFERENCE VALUE)
5000
1000
500
(T = 25˚C)
High-speed mode
PCC=0011
Middle-speed mode
PCC=0010
Low-speed mode
PCC=0000
Main system clock
HALT mode
Main system clock
STOP mode
+ Subsystem clock
operation mode
I vs V (Crystal oscillation: 4.19 MHz)
DD DD
100
50
Main system clock
STOP mode
+ 32 kHz oscillation
only
or subsystem clock
HALT mode
10
5
2
0123 4567
Power supply valtage V [V]
DD
Power supply current I [ A]
DD
µ
X1 X2 XT1 XT2
22 pF 22 pF 22 pF 22 pF
V
DD
V
DD
Crystal
4.19
MHz
Crystal
32.768
kHz
330 kΩ
a
Page 54
54
µ
PD75328
5000
1000
500
(T = 25˚C)
High-speed mode
PCC=0011
Middle-speed mode
PCC=0010
Low-speed mode
PCC=0000
Main system clock
HALT mode
Main system clock
STOP mode
+ Subsystem clock
operation mode
I vs V (Ceramic oscillation: 4.19 MHz)
DD DD
100
50
Main system clock
STOP mode
+ 32 kHz oscillation
only
or subsystem clock
HALT mode
10
5
2
0123 4567
Power supply valtage V [V]
DD
Power supply current I [ A]
DD
µ
X1 X2 XT1 XT2
30 pF 30 pF 22 pF 22 pF
V
DD
V
DD
Ceramic
oscillator
CSA4.19MG
Crystal
32.768
kHz
330 kΩ
a
Page 55
55
µ
PD75328
5000
1000
500
(T = 25˚C)
High-speed mode
PCC=0011
Middle-speed mode
PCC=0010
Low-speed mode
PCC=0000
Main system clock
HALT mode
Main system clock
STOP mode
+ Subsystem clock
operation mode
I vs V (Ceramic oscillation: 2.00 MHz)
DD DD
100
50
Main system clock
STOP mode
+ 32 kHz oscillation
only
or subsystem clock
HALT mode
10
5
2
0123 4567
Power supply valtage V [V]
DD
Power supply current I [ A]
DD
µ
X1 X2 XT1 XT2
30 pF 30 pF 22 pF 22 pF
V
DD
V
DD
Ceramic
oscillator
CSA2.00MG
Crystal
32.768
kHz
330 kΩ
a
Page 56
56
µ
PD75328
(V = 5 V, T = 25˚C)
DD
(V = 3 V, T = 25˚C)
DD
3
2
1
0
12345
f [MHz]
X
0
12345
f [MHz]
X
0.6
0.5
0.4
0.3
0.2
0.1
I
[mA]
DD
I
[mA]
DD
X1 X2
External
clock
X1 X2
External
clock
High-speed mode
PCC = 0011
Main system clock
HALT mode
Middle-speed
mode
PCC = 0010
Low-speed mode
PCC = 0000
High-speed
mode
PCC = 0011
Middle-speed
mode
PCC = 0010
Low-speed mode
PCC = 0000
Main system clock
HALT mode
40
30
(T = 25˚C)
I
[mA]
OL
20
10
0
12345
V [V]
OL
40
30
I
[mA]
OL
20
10
0
12345
V [V]
OL
V = 6 V
DD
V = 5 V
DD
V = 3 V
DD
V = 6 V
DD
V = 4 V
DD
V = 3 V
DD
a a
a
(T = 25˚C)
a
V = 2.7 V
DD
V = 4 V
DD
V = 5 V
DD
V = 2.7 V
DD
IDD vs fX
VOL vs IOL (PORT 0, 2, 6, 7, 8) VOL vs IOL (PORT 3, 4, 5)
IDD vs fX
Page 57
57
µ
PD75328
20
15
10
5
0
12345
V – V [V]
DD OH
I
[mA]
OH
20
15
10
5
0
12345
V – V [V]
DD OH
I
[mA]
OH
(T = 25˚C)
V = 6 V
DD
V = 5 V
DD
V = 3 V
DD
V = 2.7 V
DD
a
(T = 25˚C)
a
V = 4 V
DD
V = 2.7 V
DD
V = 3.5 V
DD
V = 6 V
DD
V = 5 V
DD
V = 4 V
DD
V = 3 V
DD
VOH vs IOH (P83)VOH vs IOH (Except for P83)
Page 58
58
µ
PD75328
(V = 5 V, T = 25˚C)
DD
800
700
600
500
400
300
200
100
0
–600
–500
–400
–300
–200
–100
0
12345
V [V]
OL
12345
V – V [V]
DD OH
I
[ A]
µ
OL
I
[ A]
µ
OH
Number of simultaneous output* : 1
2
3
4
Number of simultaneous output : 1
2
3
4
250
I
[ A]
µ
OL
–200
I
[ A]
µ
OH
123
V [V]
OL
123
V – V [V]
DD OH
Number of simultaneous
output* : 1
200
150
100
50
0
–150
–100
–50
0
Number of simultaneous
output : 1
2
3
4
2
3
4
a
(V = 5 V, T = 25˚C)
DD a
(V = 3 V, T = 25˚C)
DD a
(V = 3 V, T = 25˚C)
DD a
VOL vs IOL (BP0-3, BP4-7) VOH vs IOH (BP0-3, BP4-7)
* Of pins BP0-BP3 and BP4-BP7, for each, the number
of pins simultaneously outputting the same level.
VOL vs IOL (BP0-3, BP4-7)
V
OH vs IOH (BP0-3, BP4-7)
Page 59
59
µ
PD75328
12. PACKAGE DRAWINGS
A
M
F
B
60
61
40
K
L
80 PIN PLASTIC QFP ( 14)
80
1
21
20
41
G
D
C
detail of lead end
S
Q
P
M
IH
J
5°±5°
N
S80GC-65-3B9-3
ITEM MILLIMETERS INCHES
A
B
C
D
F
G
H
I
J
K
L
17.2±0.4
14.0±0.2
0.8
0.30±0.10
0.13
14.0±0.2
0.677±0.016
0.031
0.031
0.005
0.026 (T.P.)
0.551
NOTE
M
N
0.10
0.15
1.6±0.2
0.65 (T.P.)
0.004
0.006
+0.004
–0.003
Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.
0.063±0.008
0.012
0.551
0.8±0.2
0.031
P 2.7 0.106
0.677±0.016
17.2±0.4
0.8
+0.009
–0.008
Q
0.1±0.1
0.004±0.004
S 3.0 MAX. 0.119 MAX.
+0.10
–0.05
+0.009
–0.008
+0.004
–0.005
+0.009
–0.008
Page 60
Page 61
61
µ
PD75328
13. RECOMMENDED SOLDERING CONDITIONS
It is recommended that µPD75328 be soldered under the following conditions.
For details on the recommended soldering conditions, refer to Information Document "Semiconductor
Devices Mounting Manual" (IEI-616).
The soldering methods and conditions are not listed here, consult NEC.
Table 13-1 Soldering Conditions
µ
PD75328GC - xxx - 3B9: 80-pin plastic QFP (■■14 mm)
Soldering Method Soldering Conditions
Symbol for Recommended
Condition
Wave Soldering Soldering bath temperature: 260°C max., WS60-162-1
time: 10 seconds max., number of times: 1,
pre-heating temperature: 120°C max. (package surface
temperature), maximum number of days: 2 days*,
(beyond this period, 16 hours of pre-baking is required
at 125°C).
Infrared Reflow Package peak temperature: 230°C, IR30-162-1
time: 30 seconds max. (210°C min.),
number of times: 1, maximum number of days: 2 days*
(beyond this period, 16 hours of pre-baking is required
at 125°C)
VPS Reflow Package peak temperature: 215°C, VP15-162-1
time: 40 seconds max. (200°C min.),
number of times: 1, maximum number of days: 2 days*
(beyond this period, 16 hours of pre-baking is required
at 125°C)
Pin Partial Heating Pin temperature: 300°C max., —
time: 3 seconds max. (per side)
*:
Number of days after unpacking the dry pack. Storage conditions are 25°C and 65%RH max.
Caution: Do not use two or more soldering methods in combination (except the pin partial heating
method).
A model that can be soldered under the more stringent conditions (infrared reflow peak
temperature: 235°C, number of times: 2, and an extended number of days) is also available.
For details, consult NEC.
Notice
★
Page 62
µ
PD75328
Name
µ
PD75328
µ
PD75308
Item
ROM (Bytes) 8064
RAM (× 4 Bits) 512
General-Purpose • 4-bit manipulation: 8 × 4 banks
Register • 8-bit manipulation: 4 × 4 banks
Instruction Cycle Selectable from 0.95 µs, 1.91 µs, 15.3 ms (main system clock: operating at 4.19 MHz) and
122 µs (subsystem clock: operating at 32.768 kHz)
Input/ COMS 8 (shared with 8 (shared with
Output Input INT, SI, SO) INT, SI, SO)
Port
CMOS 20 (4 lines can 16 (4 lines can
Input/ directly drive directly drive
Output LED) LED)
CMOS 4/8 (shared with segment output, 4/8 (shared with segment output,
Output can be selected using software) can be selected using software)
N-ch 8 (can directly drive LED, can be 8 (can directly drive LED, can be
Input/ sustain with 10 V, and can be sustain with 10 V, and can be
Output pulled up by mask option) pulled up by mask option)
Timer/Counter • Timer/event counter
• Basic interval timer
• Watch timer
Serial Interface • Built-in NEC-standard serial bus interface (SBI)
• Normal clock synchronized serial interface is also possible
A/D Converter 6-channel analog input, 8-bit resolution —
Vector Interrupt External: 3, internal: 3
Test Input External: 1, internal: 1
Instruction Set • Bit data set/reset/test/boolean operation
• 4-bit data transfer/arithmetic/increment/decrement/comparison
• 8-bit data transfer
Display Function LCD controller LCD controller
• Segment outputs: 20 • Segment outputs: 32
(4/8 can be set for output port by using (4/8 can be set for output port by using
software) software)
• Common outputs: 4 • Common outputs: 4
• Display mode • Display mode
(static, 1/2, 1/3, 1/4) (static, 1/2, 1/3, 1/4)
• Built-in step-down resistor network for LCD • Built-in step-down resistor network for LCD
drive voltage supply (mask option) drive voltage supply (mask option)
Operating Voltage 2.7 to 6.0 V
Package 80-pin plastic QFP ( 14mm) 80-pin plastic QFP (14×20 mm)
APPENDIX A. COMPARISON OF FEATURES BETWEEN µPD75328 AND µPD75308
36
(44
max.)
32
(40
max.)
Can be pulled up
using software,
except for P00
Can be pulled up
using software,
except for P00
62
Page 63
62
µ
PD75328
Name
µ
PD75328
µ
PD75308
Item
ROM (Bytes) 8064
RAM (× 4 Bits) 512
General-Purpose • 4-bit manipulation: 8 × 4 banks
Register • 8-bit manipulation: 4 × 4 banks
Instruction Cycle Selectable from 0.95 µs, 1.91 µs, 15.3 µs (main system clock: operating at 4.19 MHz) and
122 µs (subsystem clock: operating at 32.768 kHz)
Input/ COMS 8 (shared with 8 (shared with
Output Input INT, SI, SO) INT, SI, SO)
Port
CMOS 20 (4 lines can 16 (4 lines can
Input/ directly drive directly drive
Output LED) LED)
CMOS 4/8 (shared with segment output, 4/8 (shared with segment output,
Output can be selected using software) can be selected using software)
N-ch 8 (can directly drive LED, can be 8 (can directly drive LED, can be
Input/ sustain with 10 V, and can be sustain with 10 V, and can be
Output pulled up by mask option) pulled up by mask option)
Timer/Counter • Timer/event counter
• Basic interval timer
• Watch timer
Serial Interface • Built-in NEC-standard serial bus interface (SBI)
• Normal clock synchronized serial interface is also possible
A/D Converter 6-channel analog input, 8-bit resolution —
Vector Interrupt External: 3, internal: 3
Test Input External: 1, internal: 1
Instruction Set • Bit data set/reset/test/boolean operation
• 4-bit data transfer/arithmetic/increment/decrement/comparison
• 8-bit data transfer
Display Function LCD controller LCD controller
• Segment outputs: 20 • Segment outputs: 32
(4/8 can be set for output port by using (4/8 can be set for output port by using
software) software)
• Common outputs: 4 • Common outputs: 4
• Display mode • Display mode
(static, 1/2, 1/3, 1/4) (static, 1/2, 1/3, 1/4)
• Built-in step-down resistor network for LCD • Built-in step-down resistor network for
LCD
drive voltage supply (mask option) drive voltage supply (mask option)
Operating Voltage 2.7 to 6.0 V
Package 80-pin plastic QFP (
63
µ
PD75328
EV-9200GC-80
APPENDIX B. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems
using
µ
PD75328:
PROM writing tools
Hardware IE-75000-R *
1
In-circuit emulator for 75X series
IE-75001-R
IE-75000-R-EM *
2
Emulation board for IE-75000-R and IE-75001-R
EP-75328GC-R Emulation prove for µPD75328GC, provided with 80-pin conversion socket
EV-9200GC-80.
PG-1500 PROM programmer
PA-75P328GC PROM programmer adapter solely used for µPD75P328GC. It is connected
to PG-1500.
Software IE Control Program
PG-1500 Controller
RA75X Relocatable
Assembler
*1: Maintenance product
2: Not provided with IE-75001-R.
3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this software.
Remarks: For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
Host machine
• PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3)
• IBM PC/ATTM (PC DOSTM Ver.3.1)
★
Page 64
µ
PD75328
64
APPENDIX C. RELATED DOCUMENTS
★
Page 65
µ
PD75328
65
1 STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled.
The insulation of the gates of the MOS device may be destroyed by a strong static charge.
Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,
or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use
grounding when assembling the MOS device system. Do not leave the MOS device on a plastic
plate and do not touch the pins of the device.
Handle boards on which MOS devices are mounted similarly .
2 PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices.
Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow
through the device, causing the device to malfunction. Therefore, fix the input level of the device
by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an
output pin (whose timing is not specified), each pin should be connected to V
DD or GND through
a resistor.
Refer to “Processing of Unused Pins” in the documents of each devices.
3 STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application.
Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The
output status of pins, I/O setting, and register contents upon power application are not guaranteed.
However, the items defined for reset operation and mode setting are subject to guarantee after
the respective operations have been executed.
When using a device with a reset function, be sure to reset the device after power application.
GENERAL NOTES ON CMOS DEVICES
Page 66
µ
PD75328
66
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which
may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties b y or arising from use of a device described herein or any
other liability arising from use of such device. No license, either express, implied or otherwise, is granted
under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,
nuclear reactor control systems and life support systems. If customers intend to use NEC devices for
above applications or they intend to use "Standard" quality grade NEC devices for the applications not
intended by NEC, please contact our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime system, etc.
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.
M4 92.6
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