Datasheet UPD753208GT-XXX-T2, UPD753208GT-XXX-T1, UPD753208GT-XXX-E2, UPD753208GT-XXX-E1, UPD753208GT-XXX Datasheet (NEC)

©

1996

DATA SHEET

4-BIT SINGLE-CHIP MICROCONTROLLERS

The µPD753208 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing

capability comparable to that of an 8-bit microcontroller.

The

µ

PD753208 has an on-chip LCD controller/driver and is based on the µPD75308B of the 75X Series.

However, the

µ

PD75308B is supplied in an 80-pin package, whereas the µPD753208 is supplied in a 48­pin package (375 mils, 0.65-mm pitch) and therefore is suitable for small-scale application systems. In
addition, the

µ

PD753208 features expanded CPU functions and performs high-speed operations at a low

voltage of 1.8 V.

Detailed information about functions can be found in the following user’s manual. Be sure to read it

before designing.

µ

PD753208 User’s Manual: U10158E

Document No. U10166EJ2V0DS00 (2nd edition)
Date Published March 1997 N
Printed in Japan

MOS INTEGRATED CIRCUIT

µ

PD753204, 753206, 753208

The information in this document is subject to change without notice.

The mark shows major revised points.

Features

• Low-voltage operation: VDD = 1.8 to 5.5 V
– Can be driven by two 1.5-V batteries

• Internal memory
– Program memory (ROM):

4096 × 8 bits (

µ

PD753204)

6144 × 8 bits (

µ

PD753206)

8192 × 8 bits (

µ

PD753208)

– Data memory (RAM):

512 × 4 bits

• Variable instruction execution time for high-speed
operation and power saving operation
– 0.95, 1.91, 3.81, 15.3

µ

s (@ 4.19-MHz operation)

– 0.67, 1.33, 2.67, 10.7

µ

s (@ 6.0-MHz operation)

• Internal programmable LCD controller/driver

• Small package:
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

• One-time PROM version:

µ

PD75P3216

Applications

Remote controllers, Cameras, Sphygnomamometers, Compact-disc radio cassette player compo systems,

gas meters, etc.

Ordering Information

Part number Package ROM (× 8 bits)

µ

PD753204GT-××× 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 4096

µ

PD753206GT-××× 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 6144

µ

PD753208GT-××× 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 8192

Remark ××× indicates ROM code suffix.

Unless otherwise specified, references in this data sheet to the

µ

PD753208 mean the

µ

PD753204 and the µPD753206.

2

µ

PD753204, 753206, 753208

Function Outline

Parameter Function

Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation with system clock)

• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation with system clock)

Internal memory ROM 4096 × 8 bits (

µ

PD753204)
6144 × 8 bits (µPD753206)
8192 × 8 bits (

µ

PD753208)

RAM 512 × 4 bits

General-purpose register • 4-bit operation: 8 × 4 banks

• 8-bit operation: 4 × 4 banks

Input/ CMOS input 6 Connecting on-chip pull-up resistors can be specified by software: 5
output

CMOS input/output 20 Connecting on-chip pull-up resistors can be specified by software: 20

port

Also used for segment pins: 8

N-ch open-drain 4 On-chip pull-up resistors can be specified by mask option
input/output 13-V withstand voltage

Total 30

LCD controller/driver • Segment selection: 4/8/12 segments (can be changed to CMOS input/

output port in 4-time units; max. 8)

• Display mode selection: Static

1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)

• On-chip split resistor for LCD drive can be specified by mask option

Timer 5 channels

• 8-bit timer/event counter: 1 channel

• 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier

generator, and timer with gate)

• Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel

Serial interface • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit

• 2-wire serial I/O mode

• SBI mode

Bit sequential buffer (BSB) 16 bits
Clock output (PCL) • Φ, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)

• Φ, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)

Buzzer output (BUZ) • 2, 4, 32 kHz (@ 4.19-MHz operation with system clock)

• 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)

Vectored interrupts External: 2, Internal: 5
Test input External: 1, Internal: 1
System clock oscillator Ceramic or crystal oscillator for system clock oscillation
Standby function STOP/HALT mode
Power supply voltage V

DD = 1.8 to 5.5 V

Package 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

3

µ

PD753204, 753206, 753208

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ....................................................................................................5

2. BLOCK DIAGRAM................................................................................................................................6

3. PIN FUNCTIONS ....................................................................................................................................7

3.1 Port Pins ......................................................................................................................................7

3.2 Non-Port Pins ..............................................................................................................................9

3.3 Pin Input/Output Circuits .........................................................................................................11

3.4 Recommended Connections for Unused Pins .......................................................................13

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................14

4.1 Difference Between Mk I and Mk II Modes ..............................................................................14

4.2 Setting Method of Stack Bank Select Register (SBS) ...........................................................15

5. MEMORY CONFIGURATION .............................................................................................................16

6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 21

6.1 Digital I/O Port ...........................................................................................................................21

6.2 Clock Generator ........................................................................................................................22

6.3 Clock Output Circuit .................................................................................................................23

6.4 Basic Interval Timer/Watchdog Timer.....................................................................................24

6.5 Watch Timer ..............................................................................................................................25

6.6 Timer/Event Counter.................................................................................................................26

6.7 Serial Interface ..........................................................................................................................30

6.8 LCD Controller/Driver ...............................................................................................................32

6.9 Bit Sequential Buffer ................................................................................................................34

7. INTERRUPT FUNCTION AND TEST FUNCTION ..............................................................................35

8. STANDBY FUNCTION........................................................................................................................37

9. RESET FUNCTION .............................................................................................................................38

10. MASK OPTION ...................................................................................................................................41

11. INSTRUCTION SET ............................................................................................................................42

12. ELECTRICAL SPECIFICATIONS.......................................................................................................56

13. CHARACTERISTIC CURVES (REFERENCE VALUES) ...................................................................68

14. PACKAGE DRAWINGS .....................................................................................................................70

15. RECOMMENDED SOLDERING CONDITIONS .................................................................................71

4

µ

PD753204, 753206, 753208

APPENDIX A µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST .............................................72

APPENDIX B DEVELOPMENT TOOLS.................................................................................................74

APPENDIX C RELATED DOCUMENTS ................................................................................................77

5

µ

PD753204, 753206, 753208

1. PIN CONFIGURATION (TOP VIEW)

• 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

µ

PD753204GT-×××, µPD753206GT-×××,

µ

PD753208GT-×××

Note Connect IC (Internally Connected) pin directly to V

DD.

Pin Identification

P00 to P03 : Port0 S12 to S23 : Segment Output 12 to 23
P10, P13 : Port1 V

LC0 to VLC2 : LCD Power Supply 0 to 2

P20 to P23 : Port2 BIAS : LCD Power Supply Bias Control
P30 to P33 : Port3 LCDCL : LCD Clock
P50 to P53 : Port5 SYNC : LCD Synchronization
P60 to P63 : Port6 TI0 : Timer Input 0
P80 to P83 : Port8 PTO0 to PTO2: Programmable Timer Output 0 to 2
P90 to P93 : Port9 BUZ : Buzzer Clock
KR0 to KR3 : Key Return 0 to 3 PCL : Programmable Clock
COM0 to COM3 : Common Output 0 to 3 INT0, INT4 : External Vectored Interrupt 0, 4
SCK : Serial Clock X1, X2 : System Clock Oscillation 1, 2
SI : Serial Input RESET : Reset
SO : Serial Output IC : Internally Connected
SB0, SB1 : Serial Data Bus 0, 1 V

DD : Positive Power Supply

V

SS : Ground

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

COM0
COM1
COM2
COM3

BIAS

V

LC0

VLC1
VLC2

P30/LCDCL

P31/SYNC

P32
P33

V

SS

P50
P51
P52

P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3

V

DD

X1
X2

S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P10/INT0
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
RESET
IC

Note

6

µ

PD753204, 753206, 753208

2. BLOCK DIAGRAM

Note The ROM capacity depends on the product.

PORT0

PORT1

PORT2

PORT3

PORT5

PORT6

PORT8

PORT9

4

2

4

4

4

4

4

4

P00 to P03

P10,P13

P20 to P23

P30 to P33

P50 to P53

P60 to P63

P80 to P83

P90 to P93

S12 to S15

4

4

4

4

S16/P93 to
S19/P90

S20/P83 to
S23/P80

COM0 to COM3
VLC0

VLC1
VLC2
BIAS
LCDCL/P30
SYNC/P31

f

LCD

LCD
CONTROLLER/
DRIVER

INT0/P10

4

INTW

CPU CLOCK

Φ

IC V

DD VSS

RESET

STANDBY
CONTROL

SYSTEM
CLOCK
GENERATOR

X1 X2

CLOCK
DIVIDER

CLOCK
OUTPUT
CONTROL

PCL/PTO2/P22

f

X/2

N

INTERRUPT
CONTROL

BIT SEQ
BUFFER (16)

INTCSI TOUT

INTT2

CLOCKED
SERIAL
INTERFACE

8-BIT
TIMER
COUNTER #1

8-BIT
TIMER
COUNTER #2

CASCADED
16-BIT
TIMER
COUNTER

PTO1/P21

TOUT

PTO2/PCL/P22

SP (8)

SBS

BANK

GENERAL REG.

DATA
MEMORY
(RAM)
512 × 4 BITS

CY

ALU

PROGRAM
COUNTER

PROGRAM
MEMORY

Note

(ROM)

f

LCD

WATCH
TIMER

BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER

BUZ/P23

TI0/P13

TPO0/P20

8-BIT
TIMER/EVENT
COUNTER #0

INTT1

INTT0 TOUT

SI/SB1/P03
SO/SB0/P02

SCK/P01

INT4/P00

KR0/P60 to
KR3/P63

DECODE
AND
CONTROL

INTBT

7

µ

PD753204, 753206, 753208

3. PIN FUNCTION

3.1 Port Pins (1/2)

Pin Name Input/Output

Alternate

Function

8-bit

After Reset

I/O Circuit

Function I/O TYPE

Note 1

P00 Input INT4 No Input (B)
P01 Input/Output SCK (F)-A
P02 Input/Output SO/SB0 (F)-B
P03 Input/Output SI/SB1 (M)-C
P10 Input INT0 No Input (B)-C

P13 TI0

P20 Input/Output PTO0 No Input E-B
P21 PTO1
P22 PCL/PTO2
P23 BUZ
P30 Input/Output LCDCL No Input E-B
P31 SYNC
P32 –
P33 –
P50 to Input/Output – No M-D

P53

Note 2

Notes 1. Characters in parentheses indicate the Schmitt-trigger input.

2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),

low level input leakage current increases when input or bit manipulation instruction is executed.

4-bit input port (PORT0).
For P01 to P03, on-chip pull-up resistors can
be specified by software in 3-bit units.

High level
(when pull­up resistors
are
provided) or
high­impedance

Input port in 1 bit unit (PORT1).
On-chip pull-up resistors can be specified by
software in 2-bit units.
Noise elimination circuit can be specified with
P10/INT0.

4-bit input/output port (PORT2).
On-chip pull-up resistors can be specified by
software in 4-bit units.

Programmable 4-bit input/output port (PORT3).
This port can be specified input/output bit­wise. On-chip pull-up resistor can be speci­fied by software in 4-bit units.

N-ch open-drain 4-bit input/output port (PORT5).
A pull-up resistor can be contained bit-wise
(mask option).
Withstand voltage is 13 V in open-drain mode.

8

µ

PD753204, 753206, 753208

3.1 Port Pins (2/2)

Pin Name Input/Output

Alternate

Function

8-bit

After Reset

I/O Circuit

Function I/O TYPE

Note 1

P60 Input/Output KR0 No Input (F)-A
P61 KR1
P62 KR2
P63 KR3
P80 Input/Output S23 Yes Input H
P81 S22
P82 S21
P83 S20
P90 Input/Output S19 Input H
P91 S18
P92 S17
P93 S16

Notes 1. Characters in parentheses indicate the Schmitt-trigger input.

2. Do not connect on-chip pull-up resistors specified by software when using as segment signal output

pins.

Programmable 4-bit input/output port (PORT6).
This port can be specified for input/output bit­wise.
On-chip pull-up resistors can be specified by
software in 4-bit units.

4-bit input/output port (PORT8).
On-chip pull-up resistors can be specified by
software in 4-bit units.

Note 2

4-bit input/output port (PORT9).
On-chip pull-up resistors can be specified by
software in 4-bit units.

Note 2

9

µ

PD753204, 753206, 753208

3.2 Non-Port Pins (1/2)

Pin Name Input/Output

Alternate

Function After Reset

I/O Circuit

Function TYPE

Note 1

TI0 Input P13 Inputs external event pulses to the timer/event Input (B)-C

counter.
PTO0 Output P20 Timer/event counter output Input E-B
PTO1 P21 Timer counter output
PTO2 P22/PCL
PCL P22/PTO2 Clock output
BUZ P23 Optional frequency output (for buzzer output

or system clock trimming)
SCK Input/Output P01 Serial clock input/output Input (F)-A
SO/SB0 P02 Serial data output (F)-B

Serial data bus input/output
SI/SB1 P03 Serial data input (M)-C

Serial data bus input/output
INT4 Input P00 Edge detection vectored interrupt input (both Input (B)

rising edge and falling edge detection)
INT0 Input P10 Input (B)-C

KR0 to KR3 Input/Output P60 to P63 Falling edge detection testable input Input (F)-A
S12 to S15 Output – Segment signal output Note 2 G-A
S16 to S19 Output P93 to P90 Segment signal output Input H
S20 to S23 Output P83 to P80 Segment signal output Input H
COM0 to COM3

Output – Common signal output Note 2 G-B

V

LC0 to VLC2 – – LCD drive power – –

On-chip split resistor is enable (mask option).
BIAS Output – Output for external split resistor disconnect Note 3 –
LCDCL

Note 4

Input/Output P30 Clock output for externally expanded driver Input E-B

SYNC

Note 4

Input/Output P31 Clock output for externally expanded driver sync Input E-B

Notes 1. Characters in parentheses indicate the Schmitt trigger input.

2. Each display output selects the following VLCX as input source.

S12 to S15: V

LC1, COM0 to COM2: VLC2, COM3: VLC0.

3. When a split resistor is contained ....... Low level

When no split resistor is contained ...... High-impedance

4. These pins are provided for future system expansion.
At present, these pins are used only as pins P30 and P31.

Edge detection vectored With clock elimination
interrupt input (detection circuit/asynchronous
edge can be selected). selectable
Noise elimination circuit
can be specified.

10

µ

PD753204, 753206, 753208

3.2 Non-Port Pins (2/2)

Pin Name Input/Output

Alternate

Function After Reset

I/O Circuit

Function TYPE

Note 1

X1 Input – Crystal/ceramic connection pin for the system – –

clock oscillator. When inputting the external
clock, input the external clock to pin X1, and

X2 – the reverse phase of the external clock to pin

X2.
RESET Input – System reset input (low-level active) – (B)
IC – – Internally connected. Connect directly to V

DD.– –

V

DD – – Positive power supply – –

VSS – – Ground potential – –

Note Characters in parentheses indicate the Schmitt-trigger input.

11

µ

PD753204, 753206, 753208

3.3 Pin Input/Output Circuits

The

µ

PD753208 pin input/output circuits are shown schematically.

TYPE A

TYPE B

TYPE D

TYPE E-B

TYPE B-C

TYPE F-A

V

DD

IN

P-ch

N-ch

data

output

disable

N-ch

P-ch

IN

OUT

V

DD

P-ch

output

disable

data

P.U.R.
enable

Type D

Type A

IN/OUT

V

DD

P.U.R.
enable

P.U.R.

P-ch

IN

V

DD

P.U.R.

P.U.R.
enable

P-ch

IN/OUT

Type D

Type B

output

disable

data

P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor

P.U.R. : Pull-Up Resistor

Schmitt trigger input having hysteresis characteristic.

CMOS specification input buffer.

Push-pull output that can be placed in output 
high-impedance (both P-ch, N-ch off).

P.U.R.

V

DD

(1/2)

12

µ

PD753204, 753206, 753208

TYPE F-B TYPE H

TYPE G-A

TYPE M-D

TYPE M-C

V

DD

P.U.R
enable

P.U.R

P-ch

P-ch

V

DD

N-ch

output

disable

(P)

data

output

disable

output

disable

(N)

IN/OUT

P.U.R : Pull-Up Resistor

data

output

disable

P.U.R.
enable

P.U.R

V

DD

P-ch

IN/OUT

N-ch

P.U.R : Pull-Up Resistor

V

LC1

P-ch N-ch

OUT

N-ch

V

LC2

N-ch

COM

data

P-ch

IN/OUT
N-ch
(+13-V
withstand)

V

DD

data

output

disable

P.U.R.
(Mask Option)

P.U.R. : Pull-Up Resistor

Voltage
control
circuit

Pull-up resistor that only operates upon the execution
of an input instruction when the pull-up resistor is not
connected via the mask option (it is available during
low-voltage).

Note

V

DD

P-ch

P.U.R.

Note

input

instruction

TYPE G-B

V

LC0

V

LC1

SEG

data

V

LC2

N-ch

SEG

data

data

output

disable

TYPE G-A

TYPE E-B

IN/OUT

(2/2)

P-ch
N-ch

V

LC0

P-ch
N-ch

P-ch
N-ch

P-ch N-ch

OUT

N-ch

P-ch
N-ch

P-ch
N-ch

P-ch
N-ch

13

µ

PD753204, 753206, 753208

3.4 Recommended Connections for Unused Pins

Table 3-1. List of Recommended Connections for Unused Pins

Pin Recommended Connection
P00/INT4 Connect to VSS or VDD
P01/SCK Connect individually to VSS or VDD via a resistor
P02/SO/SB0
P03/SI/SB1 Connect to VSS
P10/INT0 Connect to VSS or VDD
P13/TI0
P20/PTO0 Input state: Connect individually to VSS or V DD via a resistor
P21/PTO1 Output state: No connection
P22/PCL/PTO2
P23/BUZ
P30/LCDCL
P31/SYNC
P32
P33
P50 to P53 Input state : Connect to V

SS

Output state : Connect to VSS (Do not connect pull-up

resistor in the mask option)

P60/KR0 to P63/KR3 Input state : Connect individually to VSS or VDD via a

resistor

Output state : No connection
S0 to S15 No connection
COM0 to COM3
S16/P93 to S19/P90 Input state: Connect individually to VSS or VDD via a resistor
S20/P83 to S23/P80 Output state: No connection
VLC0 to VLC2 Connect to VSS
BIAS Only if all of VLC0 to VLC2 are unused, connect to VSS.

In other cases, no connection.
IC Connect to VDD directly

14

µ

PD753204, 753206, 753208

4 SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

4.1 Difference Between Mk I and Mk II Modes

The CPU of the

µ

PD753208 has the following two modes: Mk I and Mk II, either of which can be selected.

The mode can be switched by bit 3 of the Stack Bank Select register (SBS).

• Mk I mode: Upward compatible with the

µ

PD75308B. Can be used in the 75XL CPU with a ROM

capacity of up to 16 Kbytes.

• Mk II mode: Incompatible with

µ

PD75308B. Can be used in all the 75XL CPU including those products

whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Mk I mode Mk II mode

Number of stack bytes 2 bytes 3 bytes
for subroutine instructions

BRA ! addr1 instruction Not available Available
CALLA ! addr1 instruction

CALL ! addr instruction 3 machine cycles 4 machine cycles
CALLF ! faddr instruction 2 machine cycles 3 machine cycles

Caution The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.

Software compatibility with products whose program memory exceeds 16 Kbytes can be raised
by using this mode.
When the MkII mode is selected, the number of stack bytes increases by one byte per stack
during subroutine call instruction execution compared with the MkI mode. When the !faddr
instruction is used, the length of each machine cycle increases by 1 machine cycle. Therefore,
if RAM efficiency or processing speed is emphasized over software compatibility, use of the MkI
mode is recommended.

15

µ

PD753204, 753206, 753208

Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode.

When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode.

4.2 Setting Method of Stack Bank Select Register (SBS)

Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be

initialized to 100×B

Note

at the beginning of a program. When using the Mk II mode, it must be initialized to 000×B

Note

.

Note The desired numbers must be set in the × positions.

Figure 4-1. Stack Bank Select Register Format

SBS3 SBS2 SBS1 SBS0

3210

Symbol

SBS

Address

F84H

00
01

0

1

0

Memory bank 0
Memory bank 1

Other than 
above

0 must be set in the bit 2 position.

Stack area specification

Mk II mode
Mk I mode

Mode switching specification

Setting prohibited

16

µ

PD753204, 753206, 753208

5. MEMORY CONFIGURATION

• Program Memory (ROM) .... 4096 × 8 bits (

µ

PD753204)

.... 6144 × 8 bits (

µ

PD753206)

.... 8192 × 8 bits (

µ

PD753208)

– Addresses 0000H and 0001H

Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET
signal is generated are written. Reset and start are possible at an arbitrary address.

– Addresses 0002H to 000DH

Vector table wherein the program start address and values set for the RBE and MBE by the vectored
interrupts are written. Interrupt execution can be started at an arbitrary address.

– Addresses 0020H to 007FH

Table area referenced by the GETI instruction

Note

.

Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte

instruction, or two 1-byte instructions. It is used to decrease the program steps.

• Data Memory (RAM)

– Data area ... 512 words × 4 bits (000H to 1FFH)
– Peripheral hardware area ... 128 words × 4 bits (F80H to FFFH)

17

µ

PD753204, 753206, 753208

Figure 5-1. Program Memory Map (1/3)

(a)

µ

PD753204

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

000H

Address

7654

MBE RBE 0 0 Internal reset start address (high-order 4 bits)

0

002H MBE RBE 0 0 INTBT/INT4 (high-order 4 bits)start address

004H MBE RBE 0 0 INT0 (high-order 4 bits)start address

006H

008H MBE RBE 0 0 INTCSI (high-order 4 bits)start address

00AH MBE RBE 0 0 INTT0 (high-order 4 bits)start address

00CH MBE RBE 0 0 INTT1/INTT2 (high-order 4 bits)start address

020H

07FH

080H

7FFH

800H

FFFH

GETI instruction reference table

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

BRCB
! caddr instruction
branch address

CALL !addr instruction
subroutine entry address

BR $addr instruction
relative branch address

–15 to –1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

Internal reset start address

INTBT/INT4 start address

INT0 start address

INTCSI start address

INTT0 start address

INTT1/INTT2 start address

Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1

Note

or

CALLA !addr1

Note

instructions

CALLF
! faddr
instruction
entry
address

18

µ

PD753204, 753206, 753208

Figure 5-1. Program Memory Map (2/3)

(b)

µ

PD753206

0000H

Address

0002H MBE RBE 0 INTBT/INT4 (high-order 5 bits)start address

0004H MBE RBE 0 INT0 (high-order 5 bits)start address

0006H

0008H MBE RBE 0 INTCSI (high-order 5 bits)start address

000AH MBE RBE 0 INTT0 (high-order 5 bits)start address

0020H

007FH

0080H

07FFH

0800H

MBE RBE 0

Internal reset start address (high-order 5 bits)

0FFFH

1000H

17FFH

GETI instruction reference table

000CH MBE RBE 0 INTT1/INTT2 (high-order 5 bits)start address

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

CALLF
! faddr
instruction
entry
address

BRCB ! caddr 
instruction 
branch 
address

Branch address 
of BR BCXA, BR 
BCDE, BR ! addr, 
BRA ! addr1

Note

or 

CALLA ! addr1

Note



instructions

CALL ! addr 
instruction
subroutine entry 
address

BR $ addr 
instruction relative 
branch address

–15 to –1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

BRCB ! caddr 
instruction 
branch 
address

765 0

Internal reset start address

INTBT/INT4

INT0

INTCSI

INTT0

INTT1/INTT2

start address

start address

start address

start address

start address

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

19

µ

PD753204, 753206, 753208

Figure 5-1. Program Memory Map (3/3)

(c)

µ

PD753208

0000H

Address

0002H MBE RBE 0 INTBT/INT4 (high-order 5 bits)start address

0004H MBE RBE 0 INT0 (high-order 5 bits)start address

0006H

0008H MBE RBE 0 INTCSI (high-order 5 bits)start address

000AH MBE RBE 0 INTT0 (high-order 5 bits)start address

0020H

007FH

0080H

07FFH

0800H

MBE RBE 0

Internal reset start address (high-order 5 bits)

0FFFH

1000H

1FFFH

GETI instruction reference table

000CH MBE RBE 0 INTT1/INTT2 (high-order 5 bits)start address

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

(low-order 8 bits)

CALLF
! faddr
instruction
entry
address

BRCB ! caddr 
instruction 
branch 
address

Branch address 
of BR BCXA, BR 
BCDE, BR ! addr, 
BRA ! addr1

Note

or 

CALLA ! addr1

Note



instructions

CALL ! addr 
instruction
subroutine entry 
address

BR $ addr 
instruction relative 
branch address

–15 to –1,
+2 to +16

Branch destination
address and
subroutine entry
address when GETI
instruction is executed

BRCB ! caddr 
instruction 
branch 
address

765 0

Internal reset start address

INTBT/INT4

INT0

INTCSI

INTT0

INTT1/INTT2

start address

start address

start address

start address

start address

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order

eight bits of PC by executing the BR PCDE or BR PCXA instruction.

20

µ

PD753204, 753206, 753208

Figure 5-2. Data Memory Map

Note As a stack area, either memory bank 0 or 1 can be selected.

Data area
static RAM
(512×4)

Stack area

Note

General-purpose
register area

000H

01FH

0FFH

100H

1EBH
1ECH

1F7H

1F8H

1FFH

F80H

FFFH

Display data
memory area

Peripheral hardware area

Data memory Memory bank

0

(32 × 4)

256 × 4

(224 × 4)

256 × 4

(236 × 4)

(12 × 4)

(8 × 4)

Not incorporated

128 × 4

15

1

020H

21

µ

PD753204, 753206, 753208

6. PERIPHERAL HARDWARE FUNCTION

6.1 Digital I/O Port

There are three kinds of I/O ports.

• CMOS input ports (Ports 0, 1) : 6

• CMOS input/output ports (Ports 2, 3, 6, 8, 9) : 20

• N-ch open-drain input/output ports (Port 5) : 4
Total 30

Table 6-1. Types and Features of Digital Ports

Port Function Operation and features Remarks

PORT0 4-bit input The alternate function pins have an output function Also used for the INT4, SCK,

with operation mode when using the serial interface SO/SB0, and SI/SB1 pins.
function.

PORT1 1-bit input 2-bit input dedicated port Also used for the INT0 and

TI0.

PORT2 4-bit I/O Can be set to input mode or output mode in 4-bit Also used for the PTO0 to

units. PTO2, PCL, and BUZ pins.

PORT3 Can be set to input mode or output mode bit-wise. Also used for the LCDCL

and SYNC pins.

PORT5 4-bit I/O (N- Can be set to input mode or output mode in 4-bit —

channel open- units. On-chip pull-up resistor can be specified
drain, 13-V by mask option bit-wise.

withstand)

PORT6 4-bit I/O Can be set to input mode or output mode bit-wise. Also used for the KR0 to

KR3 pins.

PORT8 Can be set to input mode Ports 8 and 9 are paired Also used for the S20 to

or output mode in 4-bit and data can be input/ S23 pins.
units. output in 8-bit units.

PORT9 Also used for the S16 to

S19 pins.

22

µ

PD753204, 753206, 753208

6.2 Clock Generator

The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is

shown in Figure 6-1.

The operation of the clock generator is determined by the Processor Clock Control Register (PCC).
The instruction execution time can also be changed.

• 0.95, 1.91, 3.81, 15.3

µ

s (system clock: @ 4.19-MHz operation)

• 0.67, 1.33, 2.67, 10.7

µ

s (system clock: @ 6.0-MHz operation)

Figure 6-1. Clock Generator Block Diagram

Note Instruction execution

4

Φ

























VDD

X2

X1

f

X

Oscillation stop

System clock
oscillator

1/2 1/4 1/16

1/1 to 1/4096
Divider

Selector

Divider

1/4

· CPU

· INT0 noise eliminator

· Clock output circuit

HALT F/F

S

RQ

Wait release signal from BT

RESET Signal

Standby release signal from
interrupt control circuit

S

R

Q

F/FSTOP

PCC2,
PCC3
Clear

STOP

Note

PCC2

PCC3

PCC1

PCC0

PCC

HALT

Note

Internal bus

· Basic interval timer (BT)

· Timer/event counter 0

· Timer counter 1, 2

· Watch timer

· LCD controller/driver

· Serial interface

· INT0 noise eliminator

· Clock output circuit

23

µ

PD753204, 753206, 753208

From clock

generator

Φ

f

X/2

3

fX/2

4

fX/2

6

Selector

CLOM3 0 CLOM1 CLOM04CLOM

P22 
output latch

Port 2 I/O mode
specification bit

PORT2.2 Bit 2 of PMGB

Internal bus

Output buffer

PCL/PTO2/P22

From timer counter
(channel 2)

Selector

Remarks 1. f X = System clock frequency

2. Φ = CPU clock

3. PCC: Processor Clock Control Register

4. One clock cycle (t

CY) of the CPU clock is equal to one machine cycle of the instruction.

6.3 Clock Output Circuit

The clock output circuit is provided to output the clock pulses from the PCL pin (also functions as P22 or PTO2)

to the remote control wave outputs and peripheral LSIs.

• Clock Output (PCL) : Φ, 524, 262, 65.5 kHz (system clock: @ 4.19-MHz operation)
Φ, 750, 375, 93.8 kHz (system clock: @ 6.0-MHz operation)

Figure 6-2. Clock Output Circuit Block Diagram

Remark Special care has been taken in designing the chip so that small-width pulses may not be output when

switching clock output enable/disable.

24

µ

PD753204, 753206, 753208

From clock
generator

f

X/2

5

fX/2

7

fX/2

9

fX/2

12

MPX

BTM3 BTM2 BTM1 BTM0 BTM

4

SET1

Note

Internal bus

81

Basic interval timer

(8-bit frequency divider)

Clear

BT

Wait release signal
when standby is
released.

Set

Clear

3

WDTM

SET1

Note

Internal reset
signal

Vectored
interrupt
request signal

BT
interrupt
request flag

IRQBT

6.4 Basic Interval Timer/Watchdog Timer

The basic interval timer/watchdog timer has the following functions.

• Interval timer operation to generate a reference time interrupt

• Watchdog timer operation to detect program runaway and reset the CPU

• Selects and counts the wait time when the standby mode is released

• Reads the contents of counting

Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram

Note Instruction execution

25

µ

PD753204, 753206, 753208

6.5 Watch Timer

The

µ

PD753208 has one watch timer channel, whose functions are as follows.

• Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW.

• 0.5 sec interval can be created with the system clock (4.194304 MHz)

• Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the

fast feed mode.

• Outputs a frequency (2.048, 4.096, or 32.768 kHz) to the BUZ pin (P23), usable for buzzer and trimming

of system clock frequencies.

• Clears the frequency divider to make the clock start with zero seconds.

Figure 6-4. Watch Timer Block Diagram

From
clock

generator

Selector

f

X

128

(32.768 kHz)

fW
(32.768 kHz)

Divider

4 kHz 2 kHz

f

W

2

3

fW
2

4

Clear

Selector

fW
2

7

fW
2

6

(512 Hz : 1.95 ms)
(256 Hz : 3.91 ms)

f

W

2

14

Selector

2 Hz

0.5 sec

IRQW
set signal

INTW

f

LCD

Output buffer

PMGB bit 2PORT2.3WM

WM7 0 WM5 WM4 WM3 WM2 WM1 WM0

P23
output-latch

Port 2 input/
output mode

8

Internal bus

P23/BUZ

Note 2

Note 1

Notes 1. WM3 is undefined while reading data.

2. Be sure to set WM0 to 0.

Remark The values enclosed in parentheses are applied when f

X = 4.194304 MHz.

26

µ

PD753204, 753206, 753208

6.6 Timer/Event Counter

The

µ

PD753208 provides one channel for timer/event counters and two channels for timer counters. Figures

6-5 to 6-7 show the block diagrams. Timer/event counter functions are as follows.

• Programmable interval timer operation

• Square wave output of any frequency to the PTO0 pin (n = 0 to 2).

• Event counter operation (Channel 0 only)

• Divides the frequency of signal input via the TI0 pin to 1-nth of the original signal and outputs the divided
frequency to the PTO0 pin (frequency divider operation).

• Supplies the shift clock to the serial interface circuit.

• Reads the counting status.

The timer/event counter operates in the following four modes as set by the mode register.

Table 6-2. Operation Modes of Timer/Event Counter

Channel

Channel 0 Channel 1 Channel 2

Mode

8-bit timer/event counter mode

Note 1

AA A

Gate control function N/A

Note 2

N/A A
PWM pulse generator mode N/A N/A A
16-bit timer counter mode N/A A

Gate control function N/A

Note 2

A

Carrier generator mode N/A A

Notes 1. Channel 0 only. 8-bit timer counter mode for channel 1 and channel 2

2. Used for gate control signal generation

Remark A: Available

N/A: Not available

27

µ

PD753204, 753206, 753208

Figure 6-5. Timer/Event Counter Block Diagram (channel 0)

Note Execution of instruction

Caution When data is set to TM0, always set bit 1 to 0.

PORT1.3

Input

buffer

TI0/P13

f

X/2

4

fX/26fX/2

8

fX/2

10

From

clock

generator

MPX

TM06 TM05 TM04 TM03 TM02 – –

888

8

8

TM0

SET1

Note

Modulo register (8)

Comparator (8)

Count register (8)

TMOD0

T0

CP

Timer operation start

Clear

Match

TOUT

F/F

Reset

T0

enable flag

P20

output latch

Port 2

input/output

mode

TOE0 PORT2.0 PMGB bit 2

To serial interface

PTO0/P20

INTT0

IRQT0

set signal

RESET

IRQT0

clear signal

To timer counter (channel 2)

Internal bus

Output buffer

–

TOUT0

28

µ

PD753204, 753206, 753208

Figure 6-6. Timer/Event Counter Block Diagram (channel 1)

Note Execution of instruction

From clock

generator

MPX

– TM16 TM15 TM14 TM13TM12 TM11 TM10

TM1

Decoder

16 bit timer counter mode

CP

Timer operation start

Selector

Clear

8

8

8

8

Modulo register (8)

Comparator (8)

Count register (8)

Timer counter match signal (channel 2)

(During 16-bit timer counter mode)

Timer counter comparator (channel 2)

(During 16-bit timer counter mode)

Timer counter reload signal (channel 2)

T1

TMOD1

Match

TOUT

F/F

Reset

T1

enable flag

P21

output latch

Port 2

input/output

mode

INTT1

IRQT1

set signal

IRQT1 clear signal

RESET

TOE1 PORT2.1 PMGB bit 2

P21/PTO1

Output buffer

Internal bus

Timer counter

(channel 2) output

f

X/2

5

fX/26fX/2

8

fX/210fX/2

12

SET1

Note

29

µ

PD753204, 753206, 753208

Figure 6-7. Timer Counter Block Diagram (channel 2)

Note Execution of instruction

TM25TM26 TM24 TM23 TM22 TM21 TM20

TM2

8

8

TC2

Decoder

High-level period setting

modulo register (8)

Modulo register (8)

TGCE TOE2

REMC NRZB

NRZ

Reload

MPX (8)

Comparator (8)

Count register (8)

8

8

Clear

16-bit timer counter mode

Timer operation start

Timer counter

match signal (channel 1)

(During 16-bit timer

counter mode)

Timer counter

clear signal (channel 1)

(During 16-bit timer

counter mode)

Timer counter

match signal (channel 1)

(When carrier generator mode)

Match

Overflow

Carrier generator mode

PORT2.2 PMGB bit 2

P22

output latch

Output buffer

P22/PCL/PTO2

Timer clock

input (channel 1)

INTT2

IRQT2

set signal

IRQT2 clear signal

RESET

T2

TMOD2

TMOD2H

Internal bus

CP

Timer event counter

TOUT F/F (channel 0)

Reset

8

8

8

Selector

Selector

Port 2

input/output

TOUT

F/F

8

From clock

generator

MPX

Selector

From clock generator

fX/24fX/2

2

fX/2

f

X/2

6

fX/2

8

fX/2

10

SET1

Note

30

µ

PD753204, 753206, 753208

6.7 Serial Interface

The

µ

PD753208 incorporates a clock-synchronous 8-bit serial interface and can be used in the following four

modes.

• Operation stop mode

• 3-wire serial I/O mode

• 2-wire serial I/O mode

• SBI mode (serial bus interface mode)

31

µ

PD753204, 753206, 753208

Figure 6-8. Serial Interface Block Diagram

Internal bus

8

88

8/4

Bit manipulation Bit test

SBIC

Slave address register (SVA)

Address comparator

Shift

register

(SIO)

(8)

(8)

(8)

RELT

CMDT

SO latch

SET CLR

DQ

CSIM

P03/SI/SB1

P02/SO/SB0

P01/SCK

P01

output Iatch

Bus release/

command/

acknowledge

detection circuit

RELD

CMDD

ACKD

ACKT

Serial clock counter

Serial clock control

circuit

Serial clock

selector

INTCSI

control circuit

ACKE

BSYE

Busy/

acknowledge

output circuit

INTCSI

IRQCSI

set signal

f

X/2

3

fX/24fX/26TOUT0

(from timer/event counter

(channel 0))

Bit test

Match signal

Selector

Selector

External SCK

32

µ

PD753204, 753206, 753208

6.8 LCD Controller/Driver

The

µ

PD753208 incorporates a display controller which generates segment and common signals according
to the display data memory contents and incorporates segment and common drivers which can drive the panel
directly.

The

µ

PD753208 LCD controller/driver functions are as follows:

• Display data memory is read automatically by DMA operation and segment and common signals are
generated.

• Display mode can be selected from among the following five:
<1> Static
<2> 1/2 duty (time multiplexing by 2), 1/2 bias
<3> 1/3 duty (time multiplexing by 3), 1/2 bias
<4> 1/3 duty (time multiplexing by 3), 1/3 bias
<5> 1/4 duty (time multiplexing by 4), 1/3 bias

• A frame frequency can be selected from among four in each display mode.

• A maximum of 12 segment signal output pins (S12 to S23) and four common signal output pins (COM0 to
COM3).

• The segment signal output pins (S16 to S23) can be changed to the I/O ports (PORT8 and PORT9).

• Split-resistor can be incorporated to supply LCD drive power. (Mask option)
– Various bias methods and LCD drive voltages can be applicable.
– When display is off, current flowing through the split resistor is cut.

• Display data memory not used for display can be used for normal data memory.

33

µ

PD753204, 753206, 753208

Figure 6-9. LCD Controller/Driver Block Diagram

Port 8

output latch

3 2 1 0

Port 9

output latch

3 2 1 0

Port mode

register group C

0 1

LCD/port

selection 

register

1F7H

3210

1F0H

3210

1EFH

3210

1ECH

3210

Display mode register

Display 

control

register

Port 3

output latch

10

Port mode

register group A

10

4448484444

Internal bus

4

Port 8

Input/Output buffer

01 23

Port 9

Input/Output buffer

0123

S23/P80 S16/P93 S15 S0

COM3 COM2 COM1 COM0

V

LC2

V

LC1

V

LC0

P31/SYNC P30/LCDCL

LCD drive

mode 

switching

LCD drive

voltage control

Common driver

Segment driverSegment driver

3210 3210 3210 3210

Timing

controller

f

LCD

Decoder

34

µ

PD753204, 753206, 753208

Address
Bit

Symbol

L register L = FH L = CH L = BH L = 8H L = 7H L = 4H L = 3H L = 0H

DECS L

INCS L

BSB3 BSB2 BSB1 BSB0

3210321032103210

FC3H FC2H FC1H FC0H

6.9 Bit Sequential Buffer ....... 16 Bits

The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be
easily performed by changing the address specification and bit specification in sequence, therefore it is useful
when processing large data bit-wise.

Figure 6-10. Bit Sequential Buffer Format

Remarks 1. In pmem.@L addressing, the specified bit moves corresponding to the L register.

2. In pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification.

35

µ

PD753204, 753206, 753208

7. INTERRUPT FUNCTION AND TEST FUNCTION

There are seven interrupt sources and two test sources in the µPD753208.
The interrupt control circuit of the

µ

PD753208 has the following functions.

(1) Interrupt function

• Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the
interrupt enable flag (IE×××) and interrupt master enable flag (IME).

• Can set any interrupt start address.

• Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register
(IPS).

• Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software.

• Release the standby mode. A release interrupt can be selected by the interrupt enable flag.

(2) Test function

• Test request flag (IRQ×××) generation can be checked by software.

• Release the standby mode. The test source to be released can be selected by the test enable flag.

36

µ

PD753204, 753206, 753208

Internal bus

Interruput enable flag (IE×××)

IRQBT

IRQ4

IRQ0

IRQCSI

IRQT0

IRQT1

IRQT2

IRQW

IRQ2

INTCSI

INTT0

INTT1

INTT2

INTW

Both edge

detector

Edge

detector

Selec-

tor

INT4/P00

INT0/P10

KR0/P60

KR3/P63

Falling edge

detector

Selec-

tor

IM2

Standby release

signal

Priority control

circuit

Vector table

address

generator

Decoder

IME IPS IST0

VRQn

Note

IM2 IM0

24

INTBT

IST1

Figure 7-1. Interrupt Control Circuit Block Diagram

Note Noise eliminator (Standby release is disabled when noise eliminator is selected.)

37

µ

PD753204, 753206, 753208

8. STANDBY FUNCTION

In order to save power dissipation while a program is in standby mode, two types of standby modes (STOP

mode and HALT mode) are provided for the

µ

PD753208.

Table 8-1. Operation Status in Standby Mode

Item Mode STOP mode HALT mode
Set instruction STOP instruction HALT instruction
Operation Clock generator The system clock stops oscillation. Only the CPU clock Φ halts (oscillation

status continues).

Basic interval timer/ Operation stops. Operable only when the system clock
Watchdog timer is oscillated. (The IRQBT is set in the

reference interval).

Serial interface Operable only when an external SCK Operable

input is selected as the serial clock.

Timer/event counter Operable only when a signal input to Operable

the TI0 pin is specified as the count

clock.
Watch timer Operation stops. Operable
LCD controller/driver Operation stops. Operable
External interrupt The INT4 is operable.

Only the INT0 is not operated

Note

.

CPU Operation stops.

Release signal Interrupt request signal sent from the operable hardware enabled by the

interrupt enable flag or RESET signal input.

Note Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register

(IM0).

38

µ

PD753204, 753206, 753208

RESET

Internal RESET signal

RESET signal sent from the
basic interval timer/watchdog timer

WDTM

Internal bus

Operation mode or

standby mode

Wait

Note

RESET

signal

generated

Operation modeHALT mode

Internal reset operation

9. RESET FUNCTION

There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/
watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure
9-1 shows the circuit diagram of the above two inputs.

Figure 9-1. Configuration of Reset Function

Each hardware is initialized by the RESET signal generation as listed in Table 9-1. Figure 9-2 shows the
timing chart of the reset operation.

Figure 9-2. Reset Operation by RESET Signal Generation

Note The following two times can be selected by the mask option.

2

17

/fX (21.8 ms: @ 6.0-MHz operation, 31.3 ms: @ 4.19-MHz operation)

2

15

/fX (5.46 ms: @ 6.0-MHz operation, 7.81 ms: @ 4.19-MHz operation)

39

µ

PD753204, 753206, 753208

Table 9-1. Status of Each Device After Reset (1/2)

Hardware

RESET signal generation RESET signal generation

in the standby mode during operation

Program counter (PC)

µ

PD753204 Sets the low-order 4 bits of Sets the low-order 4 bits of

program memory’s address program memory’s address
0000H to PC11 to PC8 and 0000H to PC11 to PC8 and
the contents of address 0001H the contents of address 0001H
to PC7 to PC0. to PC7 to PC0.

µ

PD753206, Sets the low-order 5 bits of Sets the low-order 5 bits of

µ

PD753208 program memory's address program memory's address

0000H to PC12 to PC8 and 0000H to PC12 to PC8 and
the contents of address 0001H the contents of address 0001H
to PC7 to PC0. to PC7 to PC0.

PSW Carry flag (CY) Held Undefined

Skip flag (SK0-SK2) 0 0
Interrupt status flag (IST0, IST1) 0 0
Bank enable flag (MBE, RBE) Sets bit 6 of program memory’s Sets bit 6 of program memory’s

address 0000H to RBE and bit address 0000H to RBE and bit

7 to MBE. 7 to MBE.
Stack pointer (SP) Undefined Undefined
Stack bank select register (SBS) 1000B 1000B
Data memory (RAM) Held Undefined
General-purpose register (X, A, H, L, D, E, B, C) Held Undefined
Bank select register (MBS, RBS) 0, 0 0, 0
Basic interval

Counter (BT) Undefined Undefined

timer/watchdog

Mode register (BTM) 0 0

timer

Watchdog timer enable flag (WDTM)

00
Timer/event Counter (T0) 0 0
counter (T0) Modulo register (TMOD0) FFH FFH

Mode register (TM0) 0 0

TOE0, TOUT F/F 0, 0 0, 0
Timer Counter (T1) 0 0
counter (T1) Modulo register (TMOD1) FFH FFH

Mode register (TM1) 0 0

TOE1, TOUT F/F 0, 0 0, 0
Timer Counter (T2) 0 0
counter (T2) Modulo register (TMOD2) FFH FFH

High-level period setting modulo FFH FFH

register (TMOD2H)

Mode register (TM2) 0 0

TOE2, TOUT F/F 0, 0 0, 0

REMC, NRZ, NRZB 0, 0, 0 0, 0, 0

TGCE 0 0
Watch timer Mode register (WM) 0 0

40

µ

PD753204, 753206, 753208

Table 9-1. Status of Each Device After Reset (2/2)

Hardware

RESET signal generation RESET signal generation

in the standby mode during operation

Serial interface Shift register (SIO) Held Undefined

Operation mode register (CSIM) 0 0
SBI control register (SBIC) 0 0
Slave address register (SVA) Held Undefined

Clock generator,

Processor clock control register (PCC) 0 0

clock output circuit

Clock output mode register (CLOM) 0 0
LCD controller/ Display mode register (LCDM) 0 0
driver Display control register (LCDC) 0 0

LCD/port selection register (LPS) 0 0
Interrupt Interrupt request flag (IRQ×××) Reset (0) Reset (0)
function Interrupt enable flag (IE×××)0 0

Interrupt priority selection register (IPS)

00

INT0, 2 mode registers (IM0, IM2) 0, 0 0, 0
Digital port Output buffer Off Off

Output latch Cleared (0) Cleared (0)

I/O mode registers (PMGA, B, C) 0 0

Pull-up resistor setting register (POGA, B)

00

Bit sequential buffer (BSB0 to BSB3) Held Undefined

41

µ

PD753204, 753206, 753208

10. MASK OPTION

The µPD753208 has the following mask options.

• P50 to P53 mask options
Selects whether or not to connect an internal pull-up resistor.
<1> Connect pull-up resistor internally bit-wise.
<2> Do not connect pull-up resistor internally.

•V

LC0 to VLC2 pins, BIAS pins mask option

Selects whether or not to internally connect LCD-driving split resistors.
<1> Do not connect split resistor internally.
<2> Connect four 10-kΩ (typ.) split resistors simultaneously internally.
<3> Connect four 100-kΩ (typ.) split resistors simultaneously internally.

• Standby function mask option
Selects the wait time with the RESET signal.
<1> 2

17

/fx (21.8 ms: When fX = 6.0 MHz, 31.3 ms: When fX = 4.19 MHz)

<2> 2

15

/fx (5.46 ms: When fX = 6.0 MHz, 7.81 ms: When fX = 4.19 MHz)

42

µ

PD753204, 753206, 753208

11. INSTRUCTION SET

(1) Expression formats and description methods of operands

The operand is described in the operand column of each instruction in accordance with the description
method for the operand expression format of the instruction. For details, refer to "RA75X ASSEMBLER
PACKAGE USERS’ MANUAL—LANGUAGE (EEU-1363)". If there are several elements, one of them
is selected. Capital letters and the + and – symbols are key words and are described as they are.
For immediate data, appropriate numbers and labels are described.
Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described.
However, there are restrictions in the labels that can be described for fmem and pmem. For details, see
the user's manual.

Representation

Description method

format

reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L

rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rp' XA, BC, DE, HL, XA', BC', DE', HL'
rp'1 BC, DE, HL, XA', BC', DE', HL'

rpa HL, HL+, HL–, DE, DL
rpa1 DE, DL

n4 4-bit immediate data or label
n8 8-bit immediate data or label

mem 8-bit immediate data or label

Note

bit 2-bit immediate data or label
fmem FB0H-FBFH, FF0H-FFFH immediate data or label

pmem FC0H-FFFH immediate data or label
addr 000H-FFFH immediate data or label (

µ

PD753204)
0000H-17FFH immediate data or label (µPD753206)
0000H-1FFFH immediate data or label (µPD753208)

addr1 000H-FFFH immediate data or label (µPD753204)
(Only in the 0000H-17FFH immediate data or label (µPD753206)
MKII mode) 0000H-1FFFH immediate data or label (µPD753208)
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label

taddr 20H-7FH immediate data (where bit 0 = 0) or label
PORTn PORT0-PORT3, PORT5, PORT6, PORT8, PORT9

IE××× IEBT, IET0-IET2, IE0, IE2, IE4, IECSI, IEW
RBn RB0-RB3
MBn MB0, MB1, MB15

Note mem can be only used for even address in 8-bit data processing.

43

µ

PD753204, 753206, 753208

(2) Legend in explanation of operation

A : A register, 4-bit accumulator
B : B register
C : C register
D : D register
E : E register
H : H register
L : L register
X : X register
XA : XA register pair; 8-bit accumulator
BC : BC register pair
DE : DE register pair
HL : HL register pair
XA’ : XA’ expanded register pair
BC’ : BC’ expanded register pair
DE’ : DE’ expanded register pair
HL’ : HL’ expanded register pair
PC : Program counter
SP : Stack pointer
CY : Carry flag, bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn : Port n (n = 0 to 3, 5, 6, 8, 9)
IME : Interrupt master enable flag
IPS : Interrupt priority selection register
IE××× : Interrupt enable flag
RBS : Register bank selection register
MBS : Memory bank selection register
PCC : Processor clock control register
. : Separation between address and bit
(××) : Contents addressed by ××
××H : Hexadecimal data

44

µ

PD753204, 753206, 753208

(3) Explanation of symbols under addressing area column

*1 MB = MBE•MBS

(MBS = 0, 1, 15)
*2 MB = 0
*3 MBE = 0 : MB = 0 (000H-07FH)

MB = 15 (F80H-FFFH) Data memory addressing

MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH
*5 MB = 15, pmem = FC0H-FFFH
*6

µ

PD753204 addr = 000H-FFFH

µ

PD753206 addr = 0000H-17FFH

µ

PD753208 addr = 0000H-1FFFH

*7 addr, addr1 = (Current PC) – 15 to (Current PC) – 1

(Current PC) + 2 to (Current PC) + 16

*8

µ

PD753204 caddr = 000H-FFFH

µ

PD753206 caddr = 0000H-0FFFH(PC12 = 0) or Program memory addressing

1000H-17FFH(PC12 = 1)

µ

PD753208 caddr = 0000H-0FFFH(PC12 = 0) or

1000H-1FFFH(PC12 = 1)

*9 faddr = 0000H-07FFH

*10 taddr = 0020H-007FH
*11

µ

PD753204 addr1 = 000H-FFFH

µ

PD753206 addr1 = 0000H-17FFH

µ

PD753208 addr1 = 0000H-1FFFH

Remarks 1. MB indicates memory bank that can be accessed.

2. In *2, MB = 0 independently of how MBE and MBS are set.

3. In *4 and *5, MB = 15 independently of how MBE and MBS are set.

4. *6 to *11 indicate the areas that can be addressed.

(4) Explanation of number of machine cycles column

S denotes the number of machine cycles required by skip operation when a skip instruction is executed.
The value of S varies as follows.

• When no skip is made: S = 0

• When the skipped instruction is a 1- or 2-byte instruction: S = 1

• When the skipped instruction is a 3-byte instruction

Note

: S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle of CPU clock (= t

CY); time can be selected from among four types

by setting PCC.

45

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Transfer MOV A, #n4 1 1 A ← n4 String effect A
instruction

reg1, #n4 2 2 reg1 ← n4
XA, #n8 2 2 XA ← n8 String effect A
HL, #n8 2 2 HL ← n8 String effect B
rp2, #n8 2 2 rp2 ← n8
A, @HL 1 1 A ← (HL) *1
A, @HL+ 1 2+S A ← (HL), then L ← L+1 *1 L = 0
A, @HL– 1 2+S A ← (HL), then L ← L–1 *1 L = FH
A, @rpa1 1 1 A ← (rpa1) *2
XA, @HL 2 2 XA ← (HL) *1
@HL, A 1 1 (HL) ← A*1
@HL, XA 2 2 (HL) ← XA *1
A, mem 2 2 A ← (mem) *3
XA, mem 2 2 XA ← (mem) *3
mem, A 2 2 (mem) ← A*3
mem, XA 2 2 (mem) ← XA *3
A, reg 2 2 A ← reg
XA, rp' 2 2 XA ← rp'
reg1, A 2 2 reg1 ← A
rp'1, XA 2 2 rp'1 ← XA

XCH A, @HL 1 1 A ↔ (HL) *1

A, @HL+ 1 2+S A ↔ (HL), then L ← L+1 *1 L = 0
A, @HL– 1 2+S A ↔ (HL), then L ← L–1 *1 L = FH
A, @rpa1 1 1 A ↔ (rpa1) *2
XA, @HL 2 2 XA ↔ (HL) *1
A, mem 2 2 A ↔ (mem) *3
XA, mem 2 2 XA ↔ (mem) *3
A, reg1 1 1 A ↔ reg1
XA, rp' 2 2 XA ↔ rp'

46

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Table MOVT XA, @PCDE 1 3

●

µ

PD753204

reference XA ← (PC

11–8+DE)ROM

●

µ

PD753206, 753208

XA ← (PC

12–8+DE)ROM

XA, @PCXA 1 3 ● µPD753204

XA ← (PC

11–8+XA)ROM

●

µ

PD753206, 753208

XA ← (PC

12–8+XA)ROM

XA, @BCDE 1 3 XA ← (BCDE)ROM

Note

*6

XA, @BCXA 1 3 XA ← (BCXA)

ROM

Note

*6

Bit transfer MOV1 CY, fmem.bit 2 2 CY ← (fmem.bit) *4

CY, pmem.@L 2 2 CY ← (pmem

7–2+L3–2.bit(L1–0)) *5

CY, @H+mem.bit 2 2 CY ← (H+mem

3–0.bit) *1

fmem.bit, CY 2 2 (fmem.bit) ← CY *4
pmem.@L, CY 2 2 (pmem

7–2+L3–2.bit(L1–0)) ← CY *5

@H+mem.bit, CY 2 2 (H+mem

3–0.bit) ← CY *1

Operation ADDS A, #n4 1 1+S A ← A+n4 carry

XA, #n8 2 2+S XA ← XA+n8 carry
A, @HL 1 1+S A ← A+(HL) *1 carry
XA, rp' 2 2+S XA ← XA+rp' carry
rp'1, XA 2 2+S rp'1 ← rp'1+XA carry

ADDC A, @HL 1 1 A, CY ← A+(HL)+CY *1

XA, rp' 2 2 XA, CY ← XA+rp'+CY
rp'1, XA 2 2 rp'1, CY ← rp'1+XA+CY

SUBS A, @HL 1 1+S A ← A–(HL) *1 borrow

XA, rp' 2 2+S XA ← XA–rp' borrow
rp'1, XA 2 2+S rp'1 ← rp'1–XA borrow

SUBC A, @HL 1 1 A, CY ← A–(HL)–CY *1

XA, rp' 2 2 XA, CY ← XA–rp'–CY
rp'1, XA 2 2 rp'1, CY ← rp'1–XA–CY

Note Set "0" to register B if the µPD753204 is used. Only the low-order one bit of register B will be valid if the

µ

PD753206 or 753208 is used.

47

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Operation AND A, #n4 2 2 A ← A ∧ n4

A, @HL 1 1 A ← A ∧ (HL) *1
XA, rp' 2 2 XA ← XA ∧ rp'
rp'1, XA 2 2 rp'1 ← rp'1 ∧ XA

OR A, #n4 2 2 A ← A ∨ n4

A, @HL 1 1 A ← A ∨ (HL) *1
XA, rp' 2 2 XA ← XA ∨ rp'
rp'1, XA 2 2 rp'1 ← rp'1 ∨ XA

XOR A, #n4 2 2 A ← A v

n4

A, @HL 1 1 A ← A v

(HL) *1

XA, rp' 2 2 XA ← XA v

rp'

rp'1, XA 2 2 rp'1 ← rp'1 v

XA

Accumulator RORC A 1 1 CY ← A

0, A3 ← CY, An–1 ← An

manipulation
instructions NOT A 2 2 A ← A

Increment INCS reg 1 1+S reg ← reg+1 reg=0
and
Decrement rp1 1 1+S rp1 ← rp1+1 rp1=00H
instructions

@HL 2 2+S (HL) ← (HL)+1 *1 (HL)=0
mem 2 2+S (mem) ← (mem)+1 *3 (mem)=0

DECS reg 1 1+S reg ← reg–1 reg=FH

rp' 2 2+S rp' ← rp'–1 rp'=FFH

Comparison SKE reg, #n4 2 2+S Skip if reg = n4 reg=n4
instruction

@HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4
A, @HL 1 1+S Skip if A = (HL) *1 A = (HL)
XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL)
A, reg 2 2+S Skip if A = reg A=reg
XA, rp' 2 2+S Skip if XA = rp' XA=rp'

Carry flag SET1 CY 1 1 CY ← 1
manipulation
instruction CLR1 CY 1 1 CY ← 0

SKT CY 1 1+S Skip if CY = 1 CY=1
NOT1 CY 1 1 CY ← CY

48

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Memory bit SET1 mem.bit 2 2 (mem.bit) ← 1 *3
manipulation
instructions fmem.bit 2 2 (fmem.bit) ← 1 *4

pmem.@L 2 2 (pmem7–2+L 3–2.bit(L1–0)) ← 1 *5
@H+mem.bit 2 2 (H+mem

3–0.bit) ← 1 *1

CLR1 mem.bit 2 2 (mem.bit) ← 0 *3

fmem.bit 2 2 (fmem.bit) ← 0 *4
pmem.@L 2 2 (pmem

7–2+L3–2.bit(L1–0)) ← 0 *5

@H+mem.bit 2 2 (H+mem

3–0.bit) ← 0 *1

SKT mem.bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1

fmem.bit 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1
pmem.@L 2 2+S Skip if (pmem

7–2+L3–2.bit(L1–0))=1 *5 (pmem.@L)=1

@H+mem.bit 2 2+S Skip if (H+mem

3–0.bit)=1 *1

(@H+mem.bit)=1

SKF mem.bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0

fmem.bit 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0
pmem.@L 2 2+S Skip if (pmem

7–2+L3–2.bit(L1–0))=0 *5 (pmem.@L)=0

@H+mem.bit 2 2+S Skip if (H+mem

3–0.bit)=0 *1

(@H+mem.bit)=0

SKTCLR fmem.bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1

pmem.@L 2 2+S Skip if (pmem

7–2+L3–2.bit(L1–0))=1 and clear *5 (pmem.@L)=1

@H+mem.bit 2 2+S Skip if (H+mem

3–0.bit)=1 and clear *1

(@H+mem.bit)=1

AND1 CY, fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY ∧ (pmem

7–2+L3–2.bit(L1–0)) *5

CY, @H+mem.bit 2 2 CY ← CY ∧ (H+mem

3–0.bit) *1

OR1 CY, fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY ∨ (pmem

7–2+L3–2.bit(L1–0)) *5

CY, @H+mem.bit 2 2 CY ← CY ∨ (H+mem

3–0.bit) *1

XOR1 CY, fmem.bit 2 2 CY ← CY v

(fmem.bit) *4

CY, pmem.@L 2 2 CY ← CY v

(pmem7–2+L3–2.bit(L1–0)) *5

CY, @H+mem.bit 2 2 CY ← CY v

(H+mem3–0.bit) *1

49

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Branch BR

Note

addr – – • µPD753204 *6

instructions PC

11–0 ← addr

Select the most appropriate instruction from
among BR !addr, BRCB !caddr and BR $addr
according to the assembler being used.

•

µ

PD753206, 753208

PC

12–0 ← addr

Select the most appropriate instruction
from among BR !addr, BRCB !caddr
and BR $addr according to the
assembler being used.

addr1 – –

•

µ

PD753204 *11

PC

11-0 ← addr1

Select the most appropriate instruction
from among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.

•

µ

PD753206, 753208

PC

12–0 ← addr1

Select the most appropriate instruction
from among BR !addr, BRA !addr1,
BRCB !caddr and BR $addr1 according
to the assembler being used.

! addr 3 3

•

µ

PD753204 *6

PC

11–0 ← addr

•

µ

PD753206, 753208

PC

12–0 ← addr

$addr 1 2

•

µ

PD753204 *7

PC

11–0 ← addr

•

µ

PD753206, 753208

PC

12–0 ← addr

$addr1 1 2

•

µ

PD753204

PC

11–0 ← addr1

•

µ

PD753206, 753208

PC

12–0 ← addr1

Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

50

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Branch BR PCDE 2 3

•

µ

PD753204

instruction PC

11–0 ← PC11-8+DE

•

µ

PD753206, 753208

PC

12–0 ← PC12-8+DE

PCXA 2 3

•

µ

PD753204

PC

11–0 ← PC11-8+XA

•

µ

PD753206, 753208

PC

12–0 ← PC12-8+XA

BCDE 2 3

•

µ

PD753204 *6

PC

11–0 ← BCDE

Note 1

•

µ

PD753206, 753208

PC

12–0 ← BCDE

Note 2

BCXA 2 3 • µPD753204 *6

PC

11–0 ← BCXA

Note 1

•

µ

PD753206, 753208

PC

12–0 ← BCXA

Note 2

BRA

Note 3

!addr1 3 3 • µPD753204 *6

PC

11–0 ← addr1

•

µ

PD753206, 753208

PC

12–0 ← addr1

BRCB !caddr 2 2

•

µ

PD753204 *8

PC

11–0 ← caddr11–0

•

µ

PD753206, 753208

PC

12–0 ← PC12+caddr11–0

Subroutine CALLA

Note 3

!addr1 3 3 • µPD753204 *11

stack control (SP–2) ← ×, ×, MBE, RBE
instructions (SP–6) (SP–3) (SP–4) ← PC

11–0

(SP–5) ← 0, 0, 0, 0
PC

11–0 ← addr1, SP ← SP–6

•

µ

PD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC

11–0

(SP–5) ← 0, 0, 0, PC12
PC12–0 ← addr1, SP ← SP–6

Notes 1. "0" must be set to the B register.

2. Only the low-order one bit is valid in the B register.

3. The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

51

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Subroutine CALL

Note

!addr 3 3 • µPD753204 *6

stack control (SP–3) ← MBE, RBE, 0, 0
instructions (SP–4) (SP–1) (SP–2) ← PC

11–0

PC11–0 ← addr, SP ← SP–4

•

µ

PD753206, 753208

(SP–3) ← MBE, RBE, 0, PC

12

(SP–4) (SP–1) (SP–2) ← PC11–0
PC12–0 ← addr, SP ← SP–4

4

•

µ

PD753204
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC

11–0

(SP–5) ← 0, 0, 0, 0
PC

11–0 ← addr, SP ← SP–6

•

µ

PD753206, 753208
(SP–2) ← ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC

11–0

(SP–5) ← 0, 0, 0, PC12
PC12–0 ← addr, SP ← SP–6

CALLF

Note

!faddr 2 2 • µPD753204 *9

(SP–3) ← MBE, RBE, 0, 0
(SP–4) (SP–1) (SP–2) ← PC

11–0

PC11–0 ← 0+faddr, SP ← SP–4

•

µ

PD753206, 753208
(SP–3) ← MBE, RBE, 0, PC

12

(SP–4) (SP–1) (SP–2) ← PC11–0
PC12–0 ← 00+faddr, SP ← SP–4

3

•

µ

PD753204
(SP–2) ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC

11–0

(SP–5) ← 0, 0, 0, 0
PC

11–0 ← 0+faddr, SP ← SP–6

•

µ

PD753206, 753208
(SP–2) ×, ×, MBE, RBE
(SP–6) (SP–3) (SP–4) ← PC

11–0

(SP–5) ← 0, 0, 0, PC12
PC12–0 ← 00+faddr, SP ← SP–6

Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

←

←

52

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Subroutine RET

Note

13•

µ

PD753204

stack control PC

11–0 ← (SP) (SP+3) (SP+2)

instructions MBE, RBE, 0, 0 ← (SP+1), SP ← SP+4

•

µ

PD753206, 753208

PC

11–0 ← (SP) (SP+3) (SP+2)

MBE, RBE, 0, PC

12 ← (SP+1), SP ← SP+4

•

µ

PD753204
×, ×, MBE, RBE ← (SP+4)
0, 0, 0, 0, ← (SP+1)
PC

11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6

•

µ

PD753206, 753208
×, ×, MBE, RBE ← (SP+4)
MBE, 0, 0, PC

12 ← (SP+1)

PC

11–0 ← (SP) (SP+3) (SP+2), SP ← SP+6

RETS

Note

1 3+S • µPD753204

Unconditional
MBE, RBE, 0, 0 ← (SP+1)
PC

11–0 ← (SP) (SP+3) (SP+2)

SP ← SP+4
then skip unconditionally

•

µ

PD753206, 753208

MBE, RBE, 0, PC

12 ← (SP+1)

PC

11–0 ← (SP) (SP+3) (SP+2)

SP ← SP+4
then skip unconditionally

•

µ

PD753204
0, 0, 0, 0 ← (SP+1)
PC

11–0 ← (SP) (SP+3) (SP+2)

×, ×, MBE, RBE ← (SP+4)
SP ← SP+6
then skip unconditionally

•

µ

PD753206, 753208
0, 0, 0, PC

12 ← (SP+1)

PC

11–0 ← (SP) (SP+3) (SP+2)

×, ×, MBE, RBE ← (SP+4)
SP ← SP+4
then skip unconditionally

Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations

can be performed only in the Mk I mode.

53

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Subroutine RETI

Note 1

13•

µ

PD753204
stack control MBE, RBE, 0, 0 ← (SP+1)
instructions PC

11–0 ← (SP) (SP+3) (SP+2)

PSW ← (SP+4) (SP+5), SP ← SP+6

•

µ

PD753206, 753208

MBE, RBE, 0, PC

12 ← (SP+1)

PC

11–0 ← (SP) (SP+3) (SP+2)

PSW ← (SP+4) (SP+5), SP ← SP+6

•

µ

PD753204

0, 0, 0, 0 ← (SP+1)
PC

11–0 ← (SP) (SP+3) (SP+2)

PSW ← (SP+4) (SP+5), SP ← SP+6

•

µ

PD753206, 753208

0, 0, 0, PC

12 ← (SP+1)

PC

11–0 ← (SP) (SP+3) (SP+2)

PSW ← (SP+4) (SP+5), SP ← SP+6

PUSH rp 1 1 (SP–1)(SP–2) ← rp, SP ← SP–2

BS 2 2 (SP–1) ← MBS, (SP–2) ← RBS, SP ← SP–2

POP rp 1 1 rp ← (SP+1) (SP), SP ← SP+2

BS 2 2 MBS ← (SP+1), RBS ← (SP), SP ← SP+2

Interrupt EI 2 2 IME (IPS.3) ← 1
control

instructions IE××× 22IE××× ← 1

DI 2 2 IME (IPS.3) ← 0

IE××× 22IE××× ← 0

Input/output IN

Note 2

A, PORTn 2 2 A ← PORTn (n = 0-3, 5, 6, 8, 9)

instructions

XA, PORTn 2 2 XA ← PORTn+1, PORTn (n = 8)

OUT

Note 2

PORTn, A 2 2 PORTn ← A (n = 3, 5, 6, 8, 9)
PORTn, XA 2 2 PORTn+1, PORTn ← XA (n = 8)

CPU control HALT 2 2 Set HALT Mode (PCC.2 ← 1)
instructions

STOP 2 2 Set STOP Mode (PCC.3 ← 1)

NOP 1 1 No Operation

Special SEL RBn 2 2 RBS ← n (n = 0-3)
instructions

MBn 2 2 MBS ← n (n = 0, 1, 15)

Notes 1. The above operations in the double boxes can be performed only in the Mk II mode. The other

operations can be performed only in the Mk I mode.

2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and
MBS must be set to 15.

54

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Special GET

Notes 1, 2

taddr 1 3 •µPD753204 *10

instructions • When TBR instruction

PC

11–0 ← (taddr) 3–0 + (taddr+1)

• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC

11–0

(SP–3) ← MBE, RBE, 0, 0
PC

11–0 ← (taddr) 3–0 + (taddr+1)

SP ← SP–4

• When instruction other than TBR and Depending on
TCALL instructions the reference
(taddr) (taddr+1) instruction is executed. instruction

•

µ

PD753206, 753208

• When TBR instruction
PC

12–0 ← (taddr) 4–0 + (taddr+1)

• When TCALL instruction
(SP–4) (SP–1) (SP–2) ← PC

11–0

(SP–3) ← MBE, RBE, 0, PC12
PC12–0 ← (taddr) 4–0 + (taddr+1)
SP ← SP–4

• When instruction other than TBR and Depending on
TCALL instructions the reference
(taddr) (taddr+1) instruction is executed. instruction

3 •µPD753204 *10

• When TBR instruction
PC

11–0 ← (taddr) 3–0 + (taddr+1)

4 • When TCALL instruction

(SP–6) (SP–3) (SP–4) ← PC

11–0

(SP–5) ← 0, 0, 0, 0
(SP–2) ← ×, ×, MBE, RBE
PC

11–0 ← (taddr) 3–0 + (taddr+1)

SP ← SP–6

3 • When instruction other than TBR and Depending on

TCALL instructions the reference
(taddr) (taddr+1) instruction is executed. instruction

Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI

instruction.

2. The above operations in the double boxes can be performed only in the Mk II mode. The other
operations can be performed only in the Mk I mode.

––––––––––––––––––––––––––––––––––

–––––––––––––

–––––––––––––––––––––––––––––––––– –––––––––––––

––––––––––––––––––––––––––––––––––

–––––––––––––

––––––––––––––––––––––––––––––––––

–––––––––––––

–––––––––––––

–––––––––––––

––––––––––––––––––––––––––––––––––––– –––– -

––––––––––––––––––––––––––––––––––––– –––– -

55

µ

PD753204, 753206, 753208

Instruction Number

Number

Addressing

Mnemonic Operand

of machine

Operation Skip condition

group of bytes

cycles

area

Special GETI

Notes 1, 2

taddr 1 3 •µPD753206, 753208 *10

instructions • When TBR instruction

PC

12–0 ← (taddr) 4–0 + (taddr+1)

4 • When TCALL instruction

(SP–6) (SP–3) (SP–4) ← PC

11–0

(SP–5) ← 0, 0, 0, PC12
(SP–2) ← ×, ×, MBE, RBE
PC

12–0 ← (taddr) 4–0 + (taddr+1)

SP ← SP–6

3 • When instruction other than TBR and Depending on

TCALL instructions the reference
(taddr) (taddr+1) instruction is executed. instruction

Notes 1. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI

instruction.

2. The above operations in the double boxes can be performed only in the Mk II mode.

–––––––––––––

–––––––––––––

––––––––––––––––––––––––––––––––––––– ––––

––––––––––––––––––––––––––––––––––––– ––––

56

µ

PD753204, 753206, 753208

12. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (TA = 25˚C)

Parameter Symbol Test Conditions Rating Unit

Supply voltage V

DD –0.3 to +7.0 V

Input voltage VI1 Except port 5 –0.3 to VDD + 0.3 V

V

I2 Port 5 On-chip pull-up resistor –0.3 to VDD + 0.3 V

When N-ch open-drain –0.3 to +14 V

Output voltage V

O –0.3 to VDD + 0.3 V

Output current high IOH Per pin –10 mA

Total for all pins –30 mA

Output current low I

OL Per pin 30 mA

Total for all pins 220 mA

Operating ambient T

A –40 to +85

Note

˚C

temperature
Storage temperature T

stg –65 to +150 ˚C

Note When LCD is driven in normal mode: TA = –10 to +85˚C

Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single

parameter or even momentarily. That is, the absolute ratings are rated values at which the
product is on the verge of suffering physical damage, and therefore the product must be used
under conditions which ensure that the absolute maximum ratings are not exceeded.

CAPACITANCE (T

A = 25˚C, VDD = 0 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Input capacitance CIN f = 1 MHz 15 pF
Output capacitance C

OUT Unmeasured pins returned to 0 V. 15 pF

I/O capacitance CIO 15 pF

57

µ

PD753204, 753206, 753208

SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Resonator Recommended constant Parameter Test conditions MIN. TYP. MAX. Unit
Ceramic Oscillator 1.0

6.0

Note 2

MHz

resonator frequency (fX)

Note 1

Oscillation After VDD reaches oscil- 4 ms
stabilization time

Note 3

lation voltage range MIN.

Crystal Oscillator 1.0

6.0

Note 2

MHz

resonator frequency (fX)

Note 1

Oscillation VDD = 4.5 to 5.5 V 10 ms
stabilization time

Note 3

30

External X1 input 1.0

6.0

Note 2

MHz

clock frequency (fX)

Note 1

X1 input 83.3 500 ns
high/low level width
(tXH, tXL)

Notes 1. The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the

instruction execution time, refer to the AC characteristics.

2. When the oscillator frequency is 4.19 MHz < fx ≤ 6.0 MHz, setting the processor clock control register
(PCC) to 0011 results in 1 machine cycle being less than the required 0.95

µ

s. Therefore, set PCC

to a value other than 0011.

3. The oscillation stabilization time is necessary for oscillation to stabilize after applying V

DD or releasing

the STOP mode.

Caution When using the system clock oscillator, wiring in the area enclosed with the dotted line should

be carried out as follows to avoid an adverse effect from wiring capacitance.

• Wiring should be as short as possible.

• Wiring should not cross other signal lines.

• Wiring should not be placed close to a varying high current.

• The potential of the oscillator capacitor ground should be the same as V

DD.

• Do not ground it to the ground pattern in which a high current flows.

• Do not fetch a signal from the oscillator.

X2

X1

C1

C2

V

DD

X2

X1

C1

C2

V

DD

X1

X2

58

µ

PD753204, 753206, 753208

RECOMMENDED OSCILLATOR CONSTANTS
Ceramic resonator (TA = –40 to 85

°C)

Manufacturer Part number

Frequency

Oscillator constant (pF)

Oscillation voltage range (VDD)

Remark

(MHz)

C1 C2 MIN. (V) MAX. (V)

TDK CCR1000K2 1.0 100 100 1.8 5.5 —

CCR2.0MC33 2.0 — — 2.0 On-chip
CCR3.58MC3 3.58

capacitor

CCR4.19MC3 4.19
FCR4.19MC5 2.2
CCR6.0MC3 6.0
FCR6.0MC5 2.5

Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.

Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency
precision, the oscillaiton frequency must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.

59

µ

PD753204, 753206, 753208

DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Output voltage low I

OL Per pin 15 mA

Sum of the all pins 150 mA

Input voltage high V

IH1 Ports 2, 3, 8, and 9 2.7 ≤ VDD ≤ 5.5 V 0.7VDD VDD V

1.8 ≤ VDD < 2.7 V 0.9VDD VDD V

VIH2 Ports 0, 1, 6, RESET 2.7 ≤ VDD ≤ 5.5 V 0.8VDD VDD V

1.8 ≤ V

DD < 2.7 V 0.9VDD VDD V

VIH3 Port 5 When a pull-up register 2.7 ≤ VDD ≤ 5.5 V 0.7VDD VDD V

is incorporated

1.8 ≤ VDD < 2.7 V 0.9VDD VDD V

When N-ch open-drain 2.7 ≤ V

DD ≤ 5.5 V 0.7VDD 13 V

1.8 ≤ VDD < 2.7 V 0.9VDD 13 V

VIH4 X1

VDD – 0.1

VDD V

Input voltage low VI

L1 Ports 2, 3, 5, 8, and 9 2.7 ≤ VDD ≤ 5.5 V 0 0.3VDD V

1.8 ≤ VDD < 2.7 V 0 0.1VDD V

VIL2 Ports 0, 1, 6, RESET 2.7 ≤ VDD ≤ 5.5 V 0 0.2VDD V

1.8 ≤ VDD < 2.7 V 0 0.1VDD V

V

IL3 X1 0 0.1 V

Output voltage high VOH SCK, SO, ports 2, 3, 6, 8, and 9 IOH = –1.0 mA

VDD – 0.5

V

Output voltage low VOL1 SCK, SO, ports 2, 3, 5, 6, 8, IOL = 15 mA, 0.2 2.0 V

and 9 VDD = 4.5 to 5.5 V

I

OL = 1.6 mA 0.4 V

VOL2 SB0, SB1 N-ch open-drain 0.2VDD V

pull-up resistor ≥ 1 kΩ

Input leakage ILIH1 VIN = VDD Other pins than X1 3

µ

A

current high

ILIH2 X1 20

µ

A

I

LIH3 VIN = 13 V Port 5 (When N-ch open-drain) 20

µ

A

Input leakage ILIL1 VIN = 0 V Other pins than port 5 and X1 –3

µ

A

current low

ILIL2 X1 –20

µ

A

I

LIL3 Port 5 (When N-ch open drain) –3

µ

A
Other than when an input instruction
is executed

Port 5 (When N-ch open-drain)

–30

µ

A
When an input instruction

VDD = 5.0 V –10 –27

µ

A
is executed

VDD = 3.0 V –3 –8

µ

A

Output leakage ILOH1 VOUT = VDD SCK, SO/SB0, SB1, ports 2, 3, 6, 8 3

µ

A

current high and 9

Port 5 (When a pull-up resistor
is incorporated.)

ILOH2 VOUT = 13 V Port 5 (When N-ch open-drain) 20

µ

A

Output leakage ILOL VOUT = 0 V –3

µ

A

current low
On-chip pull-up resistor R

L1 VIN = 0 V Ports 0 to 3, 6, 8, and 9 50 100 200 kΩ

(Excluding P00 pin)

RL2 Port 5 (Mask option) 15 30 60 kΩ

60

µ

PD753204, 753206, 753208

DC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

LCD drive voltage V

LCD VAC0 = 0 TA = –40 to +85˚C 2.7 VDD V

TA = –10 to +85˚C 2.2 VDD V

VAC0 = 1 1.8 V

DD V

VAC current

Note 1

IVAC VAC0 = 1, V DD = 2.0 V ± 10% 1 4

µ

A

LCD split resistor

Note 2

RLCD1 50 100 200 kΩ
RLCD2 51020kΩ

LCD output voltage V

ODC lO = ±1.0

µ

AVLCD0 = VLCD 0 ±0.2 V

deviation

Note 3

(common) VLCD1 = VLCD × 2/3

LCD output voltage VODS lO = ±0.5 µA

VLCD2 = VLCD × 1/3

0 ± 0.2 V

deviation

Note 3

(segment)

1.8 V ≤ VLCD ≤ VDD

Supply current

Note 4

IDD1 6.0 MHz VDD = 5.0 V ± 10%

Note 5

1.9 6.0 mA

Crystal oscillation

VDD = 3.0 V ± 10%

Note 6

0.4 1.3 mA

I

DD2

C1 = C2 = 22 pF

HALT mode VDD = 5.0 V ±10% 0.72 2.1 mA

VDD = 3.0 V ±10% 0.27 0.8 mA

I

DD1 4.19 MHz VDD = 5.0 V ± 10%

Note 5

1.5 4.0 mA

Crystal oscillation

VDD = 3.0 V ± 10%

Note 6

0.25 0.75 mA

I

DD2

C1 = C2 = 22 pF

HALT mode VDD = 5.0 V ±10% 0.7 2.0 mA

VDD = 3.0 V ±10% 0.23 0.7 mA

I

DD3 STOP mode VDD = 5.0 V ±10% 0.05 10

µ

A

VDD = 3.0 V 0.02 5

µ

A

±10%

T

A = 25˚C 0.02 3

µ

A

Notes 1. Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1

µ

A.

2. Either R

LCD1 or RLCD2 can be selected by the mask option.

3. The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (V

LCDn; n = 0, 1, 2).

4. Not including currents flowing in on-chip pull-up resistors or LCD split resistors.

5. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-

speed mode.

6. When PCC is set to 0000 and the device is operated in the low-speed mode.

61

µ

PD753204, 753206, 753208

AC CHARACTERISTICS (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

CPU clock cycle t

CY VDD = 2.7 to 5.5 V 0.67 64

µ

s

time

Note 1

0.95 64

µ

s

TI0 input frequency fTI VDD = 2.7 to 5.5 V 0 1.0 MHz

0 275 kHz

TI0 input t

TIH, tTIL VDD = 2.7 to 5.5 V 0.48

µ

s

high/low-level width

1.8

µ

s

Interrupt input high/ tINTH, INT0 IM02 = 0 Note 2

µ

s

low-level width tINTL

IM02 = 1 10

µ

s

INT4 10

µ

s

KR0 to KR3 10

µ

s

RESET low level width tRSL 10

µ

s

Notes 1. The cycle time (minimum instruc-

tion execution time) of the CPU
clock (Φ) is determined by the
oscillation frequency of the con­nected resonator (and external
clock) and the processor clock
control register (PCC). The figure
at the right indicates the cycle
time t

CY versus supply voltage

V

DD characteristic.

2. 2t

CY or 128/fX is set by setting the

interrupt mode register (IM0).

10 23456

0.5

1

3

4

5

6

30

64

Supply Voltage VDD [V]

t

CY vs VDD

Cycle Time tCY [ s]

Guaranteed Operation
Range

µ

62

µ

PD753204, 753206, 753208

SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (T

A = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY1 VDD = 2.7 to 5.5 V 1300 ns

3800 ns

SCK high/low-level t KL1, tKH1 VDD = 2.7 to 5.5 V tKCY1/2 – 50 ns
width

tKCY1/2 – 150 ns

SI

Note 1

setup time tSIK1 VDD = 2.7 to 5.5 V 150 ns

(to SCK↑)

500 ns

SI

Note 1

hold time tKSI1 VDD = 2.7 to 5.5 V 400 ns

(from SCK↑)

600 ns

SO

Note 1

output delay tKSO1 RL = 1 kΩ,

Note 2

VDD = 2.7 to 5.5 V 0 250 ns

time from SCK↓ CL = 100 pF

0 1000 ns

Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.

2. R

L and CL are the load resistance and load capacitance of the SO output lines.

2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (T

A = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

SCK cycle time t

KCY2 VDD = 2.7 to 5.5 V 800 ns

3200 ns

SCK high/low-level t KL2, tKH2 VDD = 2.7 to 5.5 V 400 ns
width

1600 ns

SI

Note 1

setup time tSIK2 VDD = 2.7 to 5.5 V 100 ns

(to SCK↑)

150 ns

SI

Note 1

hold time tKSI2 VDD = 2.7 to 5.5 V 400 ns

(from SCK↑)

600 ns

SO

Note 1

output delay tKSO2 RL = 1 kΩ,

Note 2

VDD = 2.7 to 5.5 V 0 300 ns

time from SCK↓ CL = 100 pF

0 1000 ns

Notes 1. In the 2-wire serial I/O mode, read SB0 or SB1 instead.

2. R

L and CL are the load resistance and load capacitance of the SO output lines.

63

µ

PD753204, 753206, 753208

SBI Mode (SCK...Internal clock output (master)): (TA = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

SCK cycle time t

KCY3 VDD = 2.7 to 5.5 V 1300 ns

3800 ns
SCK high/low-level tKL3, tKH3 VDD = 2.7 to 5.5 V tKCY3/2 – 50 ns
width t

KCY3/2 – 150 ns

SB0, 1 setup time tSIK3 VDD = 2.7 to 5.5 V 150 ns
(to SCK↑)

500 ns

SB0, 1 hold time tKSI3 VDD = 2.7 to 5.5 V tKCY3/2 ns
(from SCK↑)

SB0, 1 output delay tKSO3 RL = 1 kΩ,

Note

VDD = 2.7 to 5.5 V 0 250 ns

time from SCK↓ CL = 100 pF

0 1000 ns
SB0, 1↓ from SCK↑ tKSB tKCY3 ns
SCK↓ from SB0, 1↑ tSBK tKCY3 ns
SB0, 1 low-level width tSBL tKCY3 ns
SB0, 1 high-level width tSBH tKCY3 ns

Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines.

SBI Mode (SCK...External clock input (slave)): (T

A = –40 to +85 ˚C, VDD = 1.8 to 5.5 V)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

SCK cycle time tKCY4 VDD = 2.7 to 5.5 V 800 ns

3200 ns
SCK high/low-level tKL4, tKH4 VDD = 2.7 to 5.5 V 400 ns
width 1600 ns
SB0, 1 setup time tSIK4 VDD = 2.7 to 5.5 V 100 ns

(to SCK↑)

150 ns

SB0, 1 hold time tKSI4 VDD = 2.7 to 5.5 V tKCY4/2 ns
(from SCK↑)

SB0, 1 output delay tKSO4 RL = 1 kΩ,

Note

VDD = 2.7 to 5.5 V 0 300 ns

time from SCK↓ CL = 100 pF

0 1000 ns

SB0, 1↓ from SCK↑ t

KSB tKCY4 ns

SCK↓ from SB0, 1↑ tSBK tKCY4 ns
SB0, 1 low-level width tSBL tKCY4 ns
SB0, 1 high-level width tSBH tKCY4 ns

Note RL and CL are the load resistance and load capacitance of the SB0 and SB1 output lines.

64

µ

PD753204, 753206, 753208

X1 Input

1/fX

tXL

tXH

0.1 V

V

DD–0.1 V

TI0

1/fTI

tTIL

tTIH

AC Timing Test Point (Excluding X1 Input)

VIH (MIN.)
V

IL

(MAX.)

V

IH

(MIN.)

V

IL

(MAX.)

VOH (MIN.)
V

OL

(MAX.)

V

OH

(MIN.)

V

OL

(MAX.)

Clock Timing

TI0 Timing

65

µ

PD753204, 753206, 753208

tKCY1, 2

tKL1, 2 tKH1, 2

SCK

SI

SO

tSIK1, 2 tKSI1, 2

tKSO1, 2

Input Data

Output Data

tKSO1, 2

tSIK1, 2

tKL1, 2

tKH1, 2

SCK

tKSI1, 2

SB0, 1

tKCY1, 2

Serial Transfer Timing
3-wire serial I/O mode

2-wire serial I/O mode

66

µ

PD753204, 753206, 753208

tKCY3, 4

tKH3, 4

tKSI3, 4

tSIK3, 4

tKSO3, 4

SCK

SB0, 1

tKL3, 4

tSBKtSBHtSBLtKSB

tKCY3, 4

tKH3, 4

tKSI3, 4

tSIK3, 4

tKSO3, 4

SCK

SB0, 1

tKL3, 4

tSBKtKSB

tRSL

RESET

tINTL tINTH

INTP0, 4 

KR0 to 3

Serial Transfer Timing
Bus release signal transfer

Command signal transfer

Interrupt input timing

RESET input timing

67

µ

PD753204, 753206, 753208

DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS

(T

A = –40 to +85˚C)

Parameter Symbol Test conditions MIN. TYP. MAX. Unit

Release signal set time t

SREL 0

µ

s

Oscillation stabilization tWAIT Release by RESET Note 2 ms
wait time

Note 1

Release by interrupt Note 3 ms

Notes 1. The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent

unstable operation at the oscillation start.

2. Either 2

17

/fX or 215/fX can be selected by the mask option.

3. Depends on the basic interval timer mode register (BTM) settings (See the table below).

BTM3 BTM2 BTM1 BTM0 Wait time

When fx = 4.19-MHz operation When fx = 6.0-MHz operation

—0002

20

/fX (approx. 250 ms) 220/fX (approx. 175 ms)

—0112

17

/fX (approx. 31.3 ms) 217/fX (approx. 21.8 ms)

—1012

15

/fX (approx. 7.81 ms) 215/fX (approx. 5.46 ms)

—1112

13

/fX (approx. 1.95 ms) 213/fX (approx. 1.37 ms)

Data Retention Timing (STOP Mode Release by RESET)

Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

VDD

RESET

STOP Instruction Execution

STOP Mode

Data Retention Mode

Internal Reset Operation

Halt mode

Operating Mode

tSREL

tWAIT

tSREL

tWAIT

VDD

STOP Instruction Execution

STOP Mode

Data Retention Mode

Halt mode

Operating Mode

Standby Release Signal
(Interrupt Request)

68

µ

PD753204, 753206, 753208

012345678

0.01

0.05

0.1

0.5

1.0

5.0

10

Supply Current IDD (mA)

(TA = 25 °C)

IDD vs VDD (System Clock : 6.0-MHz Crystal Resonator)

Supply Voltage V

DD (V)

PCC = 0000
System clock
HALT mode

PCC = 0001

PCC = 0010

VDD

22 pF

Crystal 
resonator

6.0 MHz

22 pF

X1 X2

PCC = 0011

13. CHARACTERISTIC CURVES (REFERENCE VALUES)

69

µ

PD753204, 753206, 753208

012345678

0.01

0.05

0.1

0.5

1.0

5.0

10

Supply Current IDD (mA)

(TA = 25°C)

IDD vs VDD (System Clock : 4.19-MHz Crystal Resonator)

Supply Voltage V

DD (V)

PCC = 0011

PCC = 0000
System clock

HALT mode

PCC = 0001

PCC = 0010

VDD

22 pF

Crystal
resonator

4.19 MHz

22 pF

X1 X2

70

µ

PD753204, 753206, 753208

48 PIN PLASTIC SHRINK SOP (375 mil)

C

B

D

E

F

G

A

124

48 25

L

I

H

J

K

detail of lead end

3°

M

M

N

+7°

–3°

P48GT-65-375B-1

ITEM MILLIMETERS INCHES

A
B
C

D
E

F
G
H

I

J

K

16.21 MAX.

0.65 (T.P.)

2.0 MAX.

1.7±0.1

10.0±0.3

0.63 MAX.

0.639 MAX.

0.005±0.003

0.079 MAX.

0.394

0.315±0.008

0.025 MAX.

NOTE

L

M

0.5±0.2

0.15

1.0±0.2

8.0±0.2

0.004

0.020

+0.008

–0.009

Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.

0.067±0.004

0.026 (T.P.)

0.006

N

0.10

0.004

0.012

0.30±0.10

0.125±0.075

+0.004

–0.002

0.10

+0.10

–0.05

+0.004

–0.005

+0.012
–0.013

0.039

+0.009

–0.008

14. PACKAGE DRAWINGS

71

µ

PD753204, 753206, 753208

15. RECOMMENDED SOLDERING CONDITIONS

The µPD753208 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document “Semiconductor Device

Mounting Technology Manual” (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 15-1. Surface Mounting Type Soldering Conditions

µ

PD753204GT-xxx : 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

µ

PD753206GT-xxx : 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

µ

PD753208GT-xxx : 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

Soldering

Soldering Conditions Symbol

Method

Infrared rays Peak package's surface temperature: 235˚C, Reflow time: 30 seconds or less IR35-00-2
reflow (at 210˚C or higher), Number of reflow processes: Twice max.

VPS Peak package's surface temperature: 215˚C, Reflow time: 40 seconds or less VP15-00-2

(at 200˚C or higher), Number of reflow processes: Twice max.

Wave soldering Solder temperature: 260˚C or below, Flow time: 10 seconds or less, Number of WS60-00-1

flow process: 1, Preheating temperature: 120˚C or below (Package surface
temperature)

Partial heating Pin temperature: 300˚C or below, Time: 3 seconds or less (per device side) —

Caution Use of more than one soldering method should be avoided (except for partial heating).

72

µ

PD753204, 753206, 753208

APPENDIX A µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST

Parameter

µ

PD753108

µ

PD753208

µ

PD75P3216

Program memory Mask ROM One-time PROM

0000H-1FFFH 0000H-3FFFH

(8192 × 8 bits) (16384 × 8 bits)

Data memory 000H-1FFH

(512 × 4 bits)

CPU 75XL CPU

Instruction When main system • 0.95, 1.91, 3.81, 15.3

µ

s (@ 4.19-MHz operation)

execution clock is selected • 0.67, 1.33, 2.67, 10.7

µ

s (@ 6.0-MHz operation)

time

When subsystem 122

µ

s (@ 32.768-kHz None

clock is selected operation)

I/O port CMOS input

8 (on-chip pull-up resistors can

6 (on-chip pull-up resistors can be specified by software: 5)

be specified by software: 7)

CMOS input/output 20 (on-chip pull-up resistors can be specified by software)

N-ch open drain 4 (on-chip pull-up resistors can be specified by software, 4 (no mask option, withstand
input/output withstand voltage is 13 V) voltage is 13 V)

Total 32 30

LCD controller/driver Segment selection: 16/20/24 Segment selection: 4/8/12 segments

(can be changed to CMOS (can be changed to CMOS input/output port in 4 time-unit;
input/output port in 4 time- max. 8)
unit; max. 8)

Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)

On-chip split resistor for LCD driver can be specified by No on-chip split resistor for
using mask option. LCD driver

Timer 5 channels 5 channels

• 8-bit timer/event • 8-bit timer counter: 2 channels (can be used as the 16-bit
counter: 3 channels timer counter, carrier generator, and timer with gate)

• Basic interval timer/ • 8-bit timer/event counter: 1 channel
watchdog timer: 1 channel • Basic interval timer/watchdog timer: 1 channel

• Watch timer: 1 channel • Watch timer: 1 channel

Clock output (PCL) • Φ, 524, 262, 65.5 kHz

(Main system clock: @ 4.19-MHz operation)

• Φ , 750, 375, 93.8 kHz
(Main system clock: @ 6.0-MHz operation)

Buzzer output (BUZ) • 2, 4, 32 kHz • 2, 4, 32 kHz

(Main system clock: @ (Main system clock: @ 4.19-MHz operation)

4.19-MHz operation or sub- • 2.93, 5.86, 46.9 kHz
system clock: @ 32.768-kHz (Main system clock: @ 6.0-MHz operation)
operation)

• 2.86, 5.72, 45.8 kHz
(Main system clock: @

6.0-MHz operation)

Serial interface 3 modes are available

• 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit

• 2-wire serial I/O mode

• SBI mode

SCC register Contained None

SOS register

Vectored interrupt External: 3, internal: 5 External: 2, internal: 5

73

µ

PD753204, 753206, 753208

Parameter

µ

PD753108

µ

PD753208

µ

PD75P3216

Test input External: 1, internal: 1

Operation supply voltage V

DD = 1.8 to 5.5 V

Operating ambient temperature T

A = –40 to +85°C

Package • 64-pin plastic QFP • 48-pin plastic shrink SOP

(14 × 14 mm) (375 mils, 0.65-mm pitch)

• 64-pin plastic QFP
(12 × 12 mm)

74

µ

PD753204, 753206, 753208

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for system development using the µPD753208.
In 75XL series, the relocatable assembler which is common to the

µ

PD753208 Subseries is used in combination

with the device file of each product.

Language processor

RA75X relocatable assembler

Host machine

Part number

OS Distribution media

(product name)

PC-9800 series MS-DOS

TM

3.5-inch 2HD

µ

S5A13RA75X

Ver. 3.30 to 5-inch 2HD

µ

S5A10RA75X

Ver. 6.2

Note

IBM PC/ATTM and Refer to section

3.5-inch 2HC

µ

S7B13RA75X

compatible machines

“OS for IBM PC”

5-inch 2HC

µ

S7B10RA75X

Device file

Host machine

Part number

OS Distribution media

(product name)

PC-9800 series MS-DOS 3.5-inch 2HD

µ

S5A13DF753208

Ver. 3.30 to 5-inch 2HD

µ

S5A10DF753208

Ver. 6.2

Note

IBM PC/AT and Refer to section

3.5-inch 2HC

µ

S7B13DF753208

compatible machines

“OS for IBM PC”

5-inch 2HC

µ

S7B10DF753208

PROM write tools

Hardware PG-1500 PG-1500 is a PROM programmer which enables you to program single chip microcomputers

including PROM by stand-alone or host machine operation by connecting an attached board
and optional programmer adapter to PG-1500. It also enables you to program typical PROM
devices of 256 Kbits to 4 Mbits.

PA-75P3216GT PROM programmer adapter for the µPD75P3216GT. Connect the programmer adapter to

PG-1500 for use.

Software PG-1500 controller PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500

is controlled on the host machine.

Host machine

Part number

OS Distribution media

(product name)

PC-9800 series MS-DOS 3.5-inch 2HD

µ

S5A13PG1500

Ver. 3.30 to 5-inch 2HD

µ

S5A10PG1500

Ver. 6.2

Note

IBM PC/AT and Refer to section

3.5-inch 2HD

µ

S7B13PG1500

compatible machines

“OS for IBM PC”

5-inch 2HC

µ

S7B10PG1500

Note Ver. 5.00 or later have the task swap function, but it cannot be used for this software.

Remarks 1. Operation of the assembler and device file is guaranteed only on the above host machine and OSs.

2. Operation of the PG-1500 controller is guaranteed only on the above host machine and OSs.

75

µ

PD753204, 753206, 753208

Debugging tool

The in-circuit emulators (IE-75000-R and IE-75001-R) are available as the program debugging tool for the

µ

PD753208.

The system configurations are described as follows.

Hardware IE-75000-R

Note 1

In-circuit emulator for debugging the hardware and software when developing the
application systems that use the 75X series and 75XL series. When developing a

µ

PD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP­753208GT-R that are sold separately must be used with the IE-75000-R.
By connecting with the host machine and the PROM programmer, efficient debugging
can be made.
It contains the emulation board IE-75000-R-EM which is connected.

IE-75001-R In-circuit emulator for debugging the hardware and software when developing the

application systems that use the 75X series and 75XL series. When developing a

µ

PD753208 subseries, the emulation board IE-75300-R-EM and emulation probe EP­753208GT-R which are sold separately must be used with the IE-75001-R.
It can debug the system efficiently by connecting the host machine and PROM
programmer.

IE-75300-R-EM Emulation board for evaluating the application systems that use a µPD753208

subseries.
It must be used with the IE-75000-R or IE-75001-R.

EP-753208GT-R Emulation probe for the µPD753208GT.

It must be connected to the IE-75000-R (or IE-75001-R) and IE-75300-R-EM.
It is supplied with the 48-pin conversion adapter EV-9500GF-48 which facilitates

EV-9500GF-48 connection to a target system.

Software IE control program Connects the IE-75000-R or IE-75001-R to a host machine via RS-232-C and Centronix

I/F and controls the above hardware on a host machine.

Host machine

Part No.

OS Distribution media

(product name)

PC-9800 series MS-DOS 3.5-inch 2HD

µ

S5A13IE75X

Ver. 3.30 to 5-inch 2HD

µ

S5A10IE75X

Ver. 6.2

Note 2

IBM PC/AT and its Refer to section

3.5-inch 2HC

µ

S7B13IE75X

compatible machine

“OS for IBM PC”

5-inch 2HC

µ

S7B10IE75X

Notes 1. Maintenance parts.

2. Ver. 5.00 or later have the task swap function, but it cannot be used for this software.

Remarks 1. Operation of the IE control program is guaranteed only on the above host machines and OSs.

2. The

µ

PD753204, 753206, 753208, and 75P3216 are commonly referred to as the µPD753208

Subseries.

76

µ

PD753204, 753206, 753208

OS for IBM PC

The following IBM PC OS’s are supported.

OS Version

PC DOS

TM

Ver. 5.02 to Ver. 6.3
J6.1/V

Note

to J6.3/V

Note

MS-DOS Ver. 5.0 to Ver. 6.22

5.0/V

Note

to 6.2/V

Note

IBM DOS

TM

J5.02/V

Note

Note English version is supported.

Caution Ver. 5.0 and later have the task swap function, but it cannot be used for this software.

77

µ

PD753204, 753206, 753208

APPENDIX C RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.

Documents related to device

Document No.

Document Name

Japanese English

µ

PD753204, 753206, 753208 Data Sheet U10166J This manual

µ

PD75P3216 Data Sheet U10241J U10241E

µ

PD753208 User’s Manual U10158J U10158E

75XL Series Selection Guide U10453J U10453E

Documents related to development tool

Document No.

Document Name

Japanese English

Hardware IE-75000-R/IE-75001-R User‘s Manual EEU-846 EEU-1416

IE-75300-R-EM User’s Manual U11354J U11354E
EP-753208GT-R User’s Manual U10739J U10739E
PG-1500 User’s Manual U11940J EEU-1335

Software RA75X Assembler Package User’s Manual Operation EEU-731 EEU-1346

Language EEU-730 EEU-1363

PG-1500 Controller User’s Manual PC-9800 Series EEU-704 EEU-1291

(MS-DOS) Base
IBM PC Series EEU-5008 U10540E

(PC DOS) Base

Other related documents

Document No.

Document Name

Japanese English
Semiconductor Device Package Manual C10943X
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grades on NEC Semiconductor Devices C11531J C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E
Electrostatic Discharge (ESD) Test MEM-539 IEI-1201
Guide to Quality Assurance for Semiconductor Devices C11893J MEI-1202
Microcontroller – Related Product Guide – Third Party Products – C11416J –

Caution The contents of the documents listed above are subject to change without prior notice to users.

Make sure to use the latest edition when starting design.

78

µ

PD753204, 753206, 753208

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry.
Each unused pin should be connected to VDD or GND with a resistor, if it is
considered to have a possibility of being an output pin. All handling related
to the unused pins must be judged device by device and related specifications
governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately
after power-on for devices having reset function.

79

µ

PD753204, 753206, 753208

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel:[phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J96. 8

80

µ

PD753204, 753206, 753208

MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be
prohibited without governmental license, the need for which must be judged by the customer. The export or re­export of this product from a country other than Japan may also be prohibited without a license from that country.
Please call an NEC sales representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5