Datasheet UPD75316GF-XXX-3B9, UPD75316GF-A-XXX-3B9, UPD75312GF-XXX-3B9, UPD75312GF-A-XXX-3B9 Datasheet (NEC)
Page 1
NEC Corporation 1991
Document No. IC-2825A
(O. D. No. IC-8270A)
Date Published December 1993 P
Printed in Japan
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD75312(A), 75316(A)
The information in this document is subject to change without notice.
The mark ★ shows major revised points.
DESCRIPTION
The µPD75316(A) is one of the 75X Series 4-bit single-chip microcomputer having a built-in LCD controller/
driver, and has a data processing capability comparable to that of an 8-bit microcomputer.
In addition to high-speed operation with 0.95 µs minimum instruction execution time for the CPU, the
µ
PD75316(A) can also process data in 1-, 4-, and 8-bit units. Therefore, as a 4-bit single-chip microcomputer
chip having a built-in LCD panel controller/driver, its data processing capability is the highest in its class in
the world.
Detailed functions are described in the following user's manual. Be sure to read it for designing.
µ
PD75308 User's Manual: IEM-5016
FEATURES
• Higher reliability than µPD75316
• Internal memory
• Program memory (ROM)
: 16256 × 8 bits (
µ
PD75316(A))
: 12160 × 8 bits (
µ
PD75312(A))
• Data memory
: 512 × 4 bits
• Capable of high-speed operation and variable instruction execution time to power save
• 0.95 µs, 1.91 µs, 15.3 µs (operating at 4.19 MHz)
• 122
µ
s (operating at 32.768 kHz)
• 75X architecture comparable to that for an 8-bit microcomputer is employed
• Built-in programmable LCD controller/driver
• Clock operation at reduced power dissipation: 5
µ
A TYP. (operating at 3 V)
• Enhanced timer function (3 channels)
• Interrupt functions especially enhanced for applications, such as remote control receiver
• Pull-up resistors can be provided for 31 I/O lines
• Built-in NEC standard serial bus interface (SBI)
• Upgraded model of
µ
PD7514 (µPD7500 Series)
• PROM version (
µ
PD75P316, µPD75P316A) available
APPLICATIONS
Suitable for controlling automotive and transportation equipment.
The
µ
PD75316(A) is treated as the representative model throughout this document,
unless there are differences between
µ
PD75312(A) and µPD75316(A) functions.
4-BIT SINGLE-CHIP MICROCOMPUTER
Page 2
µ
PD75312(A), 75316(A)
2
ORDERING INFORMATION
Part Number Package Quality Grade
µ
PD75312GF(A)-xxx-3B9 80-pin plastic QFP (14×20 mm) Special
µ
PD75316GF(A)-xxx-3B9 80-pin plastic QFP (14×20 mm) Special
Remarks: xxx is ROM code number.
Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209)
published by NEC Corporation to know the specification of quality grade on the devices and its
recommended applications.
DIFFERENCE BETWEEN µPD75316(A) and µPD75316
Product
µ
PD75316(A)
µ
PD75316
Item
Quality Grade Special Standard
Directly Driving LED Not offered Offered
Absolute Maximum Ratings Differ in high-level output currrent and low-level output
current
DC Characteristics Differ in low-level output voltage
Electrical
Characteristics
Page 3
µ
PD75312(A), 75316(A)
3
FUNCTIONAL OUTLINE (1/2)
Item Function
Number of Basic 41
Instructions
Instruction Cycle • 0.95 µs, 1.91 µs, 15.3 µs (Main system clock: operating at 4.19 MHz)
• 122 µs (Subsystem clock: operating at 32.768 kHz)
ROM 16256 × 8-bit (µPD75316(A)), 12160 × 8-bit (µPD75312(A))
RAM 512 × 4 bits
General-Purpose • 4-bit manipulation: 8 (B, C, D, E, H, L, X, A)
Registers • 8-bit manipulation: 4 (BC, DE, HL, XA)
Accumulator • Bit accumulator (CY)
• 4-bit accumulator (A)
• 8-bit accumulator (XA)
Instruction Set • Abundant bit manipulation instructions
• Efficient 4-bit data manipulation instructions
• 8-bit data transfer instructions
• GETI instruction executing 2-/3-byte instruction with a single byte
I/O Line 40 8 CMOS input pins Pull-up by software is possible.
: 23
16 CMOS input/output pins
8 CMOS output pins Also serve as segment pins
8 N-ch open-drain input/output Withstand voltage: 10 V
Pull-up by mask option is possible.
: 8
LCD Controller/ • Segment number selection: 24/28/32 segments
Driver (4/8 pins can also be used as bit ports.)
• Display mode selection: Static, 1/2 duty, 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty
• Dividing resistor for LCD driving can be built-in by mask option.
Supply Voltage VDD = 2.7 to 6.0 V
Range
Internal
Memory
Timer 3 chs • 8-bit timer/event counter
• Clock source: 4 steps
• Event count is possible
• 8-bit basic interval timer
• Reference time generation: 1.95 ms, 7.82 ms, 31.3 ms, 250 ms
(operating at 4.19 MHz)
• Can be used as watchdog timer
• Watch timer
• Generates 0.5-second time intervals
• Count clock source: Main system clock or subsystem clock (selectable)
• Watch fast forward mode (generates 3.9-ms time intervals)
• Buzzer output (2 kHz)
Page 4
µ
PD75312(A), 75316(A)
4
FUNCTIONAL OUTLINE (2/2)
Item Function
8-bit Serial Interface • Three modes:
• 3-line serial I/O mode
• 2-line serial I/O mode
• SBI mode
• LSB/MSB first selectable
Bit Sequential Special bit manipulation memory: 16 bits
Buffer • Ideal for remote controller
Clock Output Timer/event counter output (PTO0): Output of square wave at specified frequency
Function
Clock output (PCL): Φ, 524, 262, 65.5 kHz (operating at 4.19 MHz)
Buzzer output (BUZ): 2 kHz (operating at 4.19 MHz or 32.768 kHz)
Vector Interrupt • External: 3
• Internal: 3
Test Input • External: 1
• Internal: 1
System Clock • Ceramic/crystal oscillator circuit for main system clock oscillation: 4.194304 MHz
Oscillator Circuit • Crystal oscillator circuit for subsystem clock oscillation: 32.768 kHz
Standby STOP/HALT mode
Package 80-pin plastic QFP (14 × 20 mm)
Page 5
µ
PD75312(A), 75316(A)
5
CONTENTS
1. PIN CONFIGURATION (Top View) ................................................................................................ 7
2. BLOCK DIAGRAM ........................................................................................................................... 8
3. PIN FUNCTIONS.............................................................................................................................. 9
3.1 PORT PINS............................................................................................................................................. 9
3.2 NON PORT PINS ................................................................................................................................... 11
3.3 PIN INPUT/OUTPUT CIRCUITS ........................................................................................................... 13
3.4 RECOMMENDED PROCESSING OF UNUSED PINS .......................................................................... 15
3.5 NOTES ON USING THE P00/INT4, AND RESET PINS ...................................................................... 16
4. MEMORY CONFIGURATION .......................................................................................................... 16
5. PERIPHERAL HARDWARE FUNCTIONS........................................................................................ 20
5.1 PORTS .................................................................................................................................................... 20
5.2 CLOCK GENERATOR CIRCUIT ............................................................................................................ 21
5.3 CLOCK OUTPUT CIRCUIT .................................................................................................................... 22
5.4 BASIC INTERVAL TIMER ..................................................................................................................... 23
5.5 WATCH TIMER ...................................................................................................................................... 24
5.6 TIMER/EVENT COUNTER ..................................................................................................................... 25
5.7 SERIAL INTERFACE .............................................................................................................................. 27
5.8 LCD CONTROLLER/DRIVER.................................................................................................................. 29
5.9 BIT SEQUENTIAL BUFFER................................................................................................................... 31
6. INTERRUPT FUNCTIONS................................................................................................................ 31
7. STANDBY FUNCTIONS .................................................................................................................. 33
8. RESET FUNCTION........................................................................................................................... 34
9. INSTRUCTION SET ......................................................................................................................... 36
10. SELECTION OF MASK OPTION ..................................................................................................... 42
11. ELECTRICAL SPECIFICATIONS ...................................................................................................... 43
12. PACKAGE DRAWINGS ................................................................................................................... 55
Page 6
µ
PD75312(A), 75316(A)
6
13. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 57
APPENDIX A. COMPARISION OF FEATURES AMONG THIS SERIES PRODUCTS ..................... 58
APPENDIX B. DEVELOPMENT TOOLS .............................................................................................. 59
APPENDIX C. RELATED DOCUMENTS.............................................................................................. 60
Page 7
µ
PD75312(A), 75316(A)
7
P00-P03 : Port 0 S0-S31 : Segment Output 0-31
P10-P13 : Port 1 COM0-COM3 : Common Output 0-3
P20-P23 : Port 2 VLC0-VLC2 : LCD Power Supply 0-2
P30-P33 : Port 3 BIAS : LCD Power Supply Bias Control
P40-P43 : Port 4 LCDCL : LCD Clock
P50-P53 : Port 5 SYNC : LCD Synchronization
P60-P63 : Port 6 TI0 : Timer Input 0
P70-P73 : Port 7 PTO0 : Programmable Timer Output 0
BP0-BP7 : Bit Port BUZ : Buzzer Clock
KR0-KR7 : Key Return PCL : Programmable Clock
SCK : Serial Clock
INT0, INT1, INT4: External Vectored Interrupt 0, 1, 4
SI : Serial Input INT2 : External Test Input 2
SO : Serial Output X1, X2 : Main System Clock Oscillation 1, 2
SB0, SB1 : Serial Bus 0,1 XT1, XT2 : Subsystem Clock Oscillation 1, 2
RESET : Reset Input NC : No Connection
1. PIN CONFIGURATION (Top View)
S12
PD75316GF(A)
– –3B9×××
µ
V
LC0
S11
1
80
2
P70/KR4
78
77 76 7574 73 72 71 69 68 67 66 65
S10S9S8S7S6S5S4S3S2S1S0
RESET
P73/KR7
P72/KR6
P71/KR5
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
COM0
COM1
COM2
COM3
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
BIAS
V
LC1VLC2
P40
P41
P42
P43
V
SS
P50
P51
P52
P53
P00/INT4
P01/SCK
P02/SO/SB0
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P63/KR3
P62/KR2
P61/KR1
P60/KR0
X2
X1
NC
XT2
XT1
V
DD
P33
P32
P31/SYNC
P30/LCDCL
P23/BUZ
P22/PCL
P21
P20/PTO0
P13/TI0
P12/INT2
P11/INT1
P10/INT0
P03/SI/SB1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PD75312GF(A)
– –3B9×××
µ
79
70
Page 8
µ
PD75312(A), 75316(A)
8
2. BLOCK DIAGRAM
TI0/P13
BASIC
INTERVAL
TIMER
INTBT
TIMER/EVENT
COUNTER
#0
INTT0
PTO0/P20
BUZ/P23
WATCH
TIMER
INTW f
LCD
INTCSI
CLOCKED
SERIAL
INTERFACE
SI/SB1/P03
SO/SB0/P02
SCK/P01
PROGRAM
COUNTER (14)
ALU
CY
SP (8)
BANK
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60
–KR7/P73
8
INTERRUPT
CONTROL
BIT SEQ.
BUFFER (16)
PROGRAM
MEMORY
(ROM)
16256 8 BITS
: PD75316(A)
12160 8 BITS
: PD75312(A)
×
DECODE
AND
CONTROL
GENERAL REG.
DATA
MEMORY
(RAM)
512 4 BITS
×
f /2
X
N
VDDVSSRESET
PCL/P22 XT1 XT2 X1 X2
SUB MAIN
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
SYSTEM CLOCK
GENERATOR
STAND BY
CONTROL
CPU
CLOCK
f
LCD
SYNC/P31
LCDCL/P30
BIAS
V -V
LC0 LC2
3
LCD
CONTROLLER
/DRIVER
4
8
24
COM0-COM3
S24/BP0
-S31/BP7
S0-S23
PORT 7
P70-P734
PORT 6
P60-P634
PORT 5
P50-P534
PORT 4
P40-P434
PORT 3
P30-P334
PORT 2
P20-P234
PORT 1
P10-P134
PORT 0
P00-P034
×
µ
µ
Page 9
µ
PD75312(A), 75316(A)
9
3. PIN FUNCTIONS
3.1 PORT PINS (1/2)
Input/
Output
Circuit
TYPE
P00
P01
P02
P03
P10
P11
P12
P13
P20
P21
P22
P23
P30
P31
P32
P33
P40-43
P50-53
Pin Name
Input/Output Function 8-Bit I/O When Reset
Also Served
As
INT4
SCK
SO/SB0
SI/SB1
INT0
INT1
INT2
TI0
PTO0
—
PCL
BUZ
LCDCL
SYNC
—
—
—
—
4-bit input port (PORT0)
Pull-up resistors can be specified in 3-bit
units for the P01 to P03 pins by software.
With noise elimination function
4-bit input port (PORT1)
Internal pull-up resistors can be
specified in 4-bit units by software.
4-bit input/output port (PORT2)
Internal pull-up resistors can be
specified in 4-bit units by software.
Programmable 4-bit input/output port
(PORT3)
This port can be specified for input/
output in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.
N-ch open-drain 4-bit input/output port
(PORT4)
Internal pull-up resistors can be
specified in bit units. (mask option)
Withstand voltage is 10 V in the opendrain mode.
N-ch open-drain 4-bit input/output port
(PORT5)
Internal pull-up resistors can be
specified in bit units. (mask option)
Withstand voltage is 10 V in the opendrain mode.
Input
Input
Input
Input
High level
(with internal
pull-up
resistor) or
high impedance
B
B -C
E-B
E-B
M
M
×
×
×
×
*: Circles indicate Schmitt trigger inputs.
Input
Input/
Output
Input/
Output
Input/
Output
Input
Input/
Output
Input/
Output
Input/
Output
Input/
Output
●●
F -A
M -C
F -B
High level
(with internal
pull-up
resistor) or
high impedance
*
Page 10
µ
PD75312(A), 75316(A)
3
P60
P61
P62
P63
P70
P71
P72
P73
BP0
BP1
BP2
BP3
BP4
BP5
BP6
BP7
KR0
KR1
KR2
KR3
KR4
KR5
KR6
KR7
S24
S25
S26
S27
S28
S29
S30
S31
●●
Also Served
As
3.1 PORT PINS (2/2)
Input/
Output
Circuit
TYPE*
1
Programmable 4-bit input/output port
(PORT6)
This port can be specified for input/
output in bit units.
Internal pull-up resistors can be
specified in 4-bit units by software.
Input
F -A
4-bit input/output port (PORT7)
Internal pull-up resistors can be
specified in 4-bit units by software.
Input
F -A
Pin Name Input/Output Function 8-Bit I/O When Reset
1-bit output port (BIT PORT)
Shared with a segment output pin.
×
*2
G-C
Input/
Output
Input/
Output
Output
Output
*1: Circles indicate Schmitt trigger inputs.
2: For BP0-7, V
LC1 indicated below are selected as the input source. However, the output level is
changed depending on BP0-7 and the V
LC1 external circuits.
Example: Since BP0-7 are connected to each other within the µPD75316(A) as shown in the diagram
below, the output level of BP0-7 depends on the sizes of R
1, R2 and R3.
PD75316(A)
µ
ON
ON
BP0
BP1
V
DD
R
2
R
3
V
LC1
R
1
10
Page 11
µ
PD75312(A), 75316(A)
11
TI0
PTO0
PCL
BUZ
SCK
SO/SB0
SI/SB1
INT4
INT0
INT1
INT2
KR0-KR3
KR4-KR7
S0-S23
S24-S31
COM0-
COM3
VLC0-VLC2
BIAS
LCDCL*
4
SYNC*
4
X1, X2
XT1
XT2
Input
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input/
Output
Input
Input
Input
Input/
Output
Input/
Output
Output
Output
Output
—
Output
Input/
Output
Input/
Output
Input
Input
—
P13
P20
P22
P23
P01
P02
P03
P00
P10
P11
P12
P60-P63
P70-P73
—
BP0-7
—
—
—
P30
P31
—
—
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
*2
*2
*2
—
*3
Input
Input
—
—
B -C
E-B
E-B
E-B
F -A
F -B
M -C
B
B -C
B -C
F -A
F -A
G-A
G-C
G-B
—
—
E-B
E-B
—
—
Pin Name Input/Output
Also Served
As
Functon When Reset
Input/
Output
Circuit
TYPE*
1
3.2 NON PORT PINS
Timer/event counter external event pulse Input
Timer/event counter output
Clock output
Fixed frequency output (for buzzer or for trimming the system clock)
Serial clock input/output
Serial data output
Serial bus input/output
Serial data input
Serial bus input/output
Edge detection vector interrupt input (both
rising and falling edge detection are effective)
Edge detection vector
interrupt input (detection
edge can be selected)
Edge detection testable
input (rising edge detection)
Parallel falling edge detection testable input
Parallel falling edge detection testable input
Segment signal output
Segment signal output
Common signal output
LCD drive power
Internal dividing resistor (mask option)
Disconnect output for external expanded driver
Externally expanded driver clock output
Externally expanded driver sync clock output
To connect the crystal/ceramic oscillator to the
main system clock generator. When inputting the
external clock, input the external clock to pin X1,
and the reverse phase of the external clock to pin
X2.
To connect the crystal oscillator to the subsystem
clock generator.
When the external clock is used, pin XT1 inputs the
external clock. In this case, pin XT2 must be left
open.
Pin XT1 can be used as a 1-bit input (test) pin.
Clock synchronous
Asynchronous
Asynchronous
(to be cont'd)
Page 12
µ
PD75312(A), 75316(A)
12
Also Served
As
(cont'd)
Input/
Output
Circuit
TYPE*
1
Pin Name Input/Output Function When Reset
RESET
NC *
5
VDD
VSS
Input
—
—
—
—
—
—
—
System reset input
No connection
Positive power supply
GND
—
—
—
—
B
—
—
—
*1: Circles indicate Schmitt trigger inputs.
2: For these display output, V
LCX indicated below are selected as the input source.
S0 to S31: V
LC1, COM0 to COM2: VLC2, COM3: VLC0
However, display output level varies depending on the particular display output and VLCX
external circuit.
3: Internal dividing resistor provided : Low level
Internal dividing resistor not provided : High impedance
4: These pins are provided for future system expansion. At present, these pins are used only as
pins P30 and P31.
5: When sharing the printed circuit board with the
µ
PD75P316 and 75P316A, the NC pin must be
connected to V
DD.
Page 13
µ
PD75312(A), 75316(A)
13
3.3 PIN INPUT/OUTPUT CIRCUITS
The following shows a simplified input/output circuit diagram for each pin of the
µ
PD75316(A).
TYPE A (for TYPE E–B)
TYPE D (for TYPE E –
B, F
TYPE B
TYPE E–B
IN
V
DD
Input buffer of CMOS standard
data
output
disable
OUT
P–ch
N–ch
Push–pull output that can be set in a output
high–impedance state (both P–ch and N–ch are off)
IN
Schmitt trigger input with hysteresis characteristics
data
output
disable
Type D
Type A
P.U.R.
enable
V
DD
P.U.R.
P–ch
IN/OUT
P.U.R. : Pull–Up Resistor
P.U.R.
enable
V
DD
P.U.R.
P–ch
TYPE B–C
TYPE F–A
IN
data
output
disable
Type D
Type B
P.U.R.
enable
V
DD
P.U.R.
P–ch
IN/OUT
P.U.R. : Pull–Up ResistorP.U.R. : Pull
–Up Resistor
A)
–
V
DD
P–ch
N–ch
Page 14
µ
PD75312(A), 75316(A)
14
P-ch
TYPE M–C
data
output
disable
P.U.R.
enable
V
DD
P.U.R.
IN/OUT
P–ch
N-ch
TYPE F–B
TYPE M
data
output
disable
P.U.R.
enable
V
DD
IN/OUT
Middle voltage input buffer
(withstand voltage: +10 V)
P.U.R. : Pull–Up Resistor
data
output
disable
P.U.R.
enable
V
DD
P.U.R.
P–ch
N-ch
P-ch
output
disable
(P)
output
disable
(N)
VDD
(Mask option)
P.U.R. : Pull–Up Resistor
IN/OUT
TYPE G–C
TYPE G–A
P.U.R. : Pull–Up Resistor
TYPE G–B
VDD
VLC0
VLC0
VLC1
VLC2
SEG
data/Bit Port data
P-ch
N-ch
OUT
N-ch
V
LC1
VLC2
P-ch
P-ch
N-ch
OUT
N-ch
VLC0
VLC1
VLC2
P-ch
N-ch
SEG
data
COM
data
OUT
P-ch N-ch
N-ch P-ch
N-ch
Page 15
µ
PD75312(A), 75316(A)
15
3.4 RECOMMENDED PROCESSING OF UNUSED PINS
Connect to VSS
Table 3-1 Unused Pins Processing
Pin Recommended Connections
P00/INT4 Connect to VSS
P01/SCK
P02/SO/SB0 Connect to VSS or VDD
P03/SI/SB1
P10/INT0-P12/INT2
P13/TI0
P20/PTO0
P21
P22/PCL
P23/BUZ
P30/LCDCL
P31/SYNC Input : Connect to VSS or VDD
P32
Output: Open
P33
P40-P43
P50-P53
P60/KR0-P63/KR3
P70/KR4-P73/KR7
S0-S23
S24/BP0-S31/BP7 Open
COM0-COM3
VLC0-VLC2 Connect to VSS
BIAS Connect to VSS only when all of the VLC0-VLC2
pins are unused, otherwise, open.
XT1 Connect to VSS or VDD
XT2 Open
Page 16
µ
PD75312(A), 75316(A)
16
3.5 NOTES ON USING THE P00/INT4, AND RESET PINS
In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode,
in which the internal fuctions of the
µ
PD75316(A) are tested, is provided to the P00/INT4 and RESET pins.
If a voltage exceeding V
DD is applied to either of these pins, the
µ
PD75316(A) is put into test mode. Therefore,
even when the
µ
PD75316(A) is in normal operation, if noise exceeding the VDD is input into any of these pins,
the
µ
PD75316(A) will enter the test mode, and this will cause problems for normal operation.
As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and
the above montioned problem may occur.
Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot
be avoided, suppress the noise using a capacitor or diode as shown in the figure below.
• Connect a diode having a low VF across
P00/INT4 and RESET, and V
DD.
• Connect a capacitor across P00/INT4 and
RESET, and VDD.
4. MEMORY CONFIGURATION
• Program memory (ROM) ...16256 × 8 bits (0000H-3F7FH): µPD75316(A)
...12160 × 8 bits (0000H-2F7FH):
µ
PD75312(A)
• 0000H, 0001H : Vector table to which address from which program is started is written after
reset
• 0002H-000BH: Vector table to which address from which program is started is written after
interrupt
• 0020H-007FH: Table area referenced by GETI instruction
• Data memory
• Data area .... 512 × 4 bits (000H–1FFH)
• Peripheral hardware area .... 128 × 4 bits (F80H–FFFH)
VDD
VDD
P00/INT4, RESET
VDD
VDD
P00/INT4, RESET
Low VF
diode
Page 17
µ
PD75312(A), 75316(A)
17
(a) µPD75316(A)
Address
7
6
5
0
0000H
MBE
0
0002H
MBE
0
0004H
MBE
0
0006H
MBE
0
0008H
MBE
0
000AH
MBE
0
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3F7FH
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
GETI instruction reference table
CALLF
! faddr
instruction
entry
address
BRCB
! caddr
instruction
branch
address
CALL ! addr
instruction
subroutine
entry address
BR ! addr
instruction
branch address
BR $addr
instruction
relational
branch address
(-15 to -1,
+2 to +16)
Branch destination
address and
subroutine entry
address for
GETI instruction
BRCB ! caddr
instruction branch
address
BRCB ! caddr
instruction branch
address
BRCB ! caddr
instruction branch
address
Fig. 4-1 Program Memory Map (1/2)
Page 18
µ
PD75312(A), 75316(A)
18
(b) µPD75312(A)
Address
7
6
5
0
0000H
MBE
0
0002H
MBE
0
0004H
MBE
0
0006H
MBE
0
0008H
MBE
0
000AH
MBE
0
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2F7FH
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
GETI instruction reference table
CALLF
! faddr
instruction
entry
address
BRCB
! caddr
instruction
branch
address
CALL ! addr
instruction
subroutine
entry address
BR ! addr
instruction
branch address
BR $addr
instruction
relational
branch address
(-15 to -1,
+2 to +16)
Branch destination
address and
subroutine entry
address for
GETI instruction
BRCB ! caddr
instruction branch
address
BRCB ! caddr
instruction branch
address
Fig. 4-1 Program Memory Map (2/2)
Page 19
µ
PD75312(A), 75316(A)
19
000H
007H
008H
0FFH
100H
1DFH
1E0H
1FFH
F80H
FFFH
Data memory
Memory bank
(8 × 4)
256× 4
(248× 4)
256× 4
(224× 4)
Unmapped
(32 × 4)
128× 4
0
1
15
General-purpose
register area
Stack area
Display data memory area
Data area
Static RAM
(512× 4)
Peripheral hardware area
Fig. 4-2 Data Memory Map
Page 20
µ
PD75312(A), 75316(A)
20
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 PORTS
I/O ports are classified into the following 4 kinds:
• CMOS input (PORT0, 1) : 8
• CMOS input/output (PORT2, 3, 6, 7) : 16
• N-ch open-drain (PORT4, 5) : 8
• CMOS output (BP0-BP7) : 8
Total : 40
Port Name
PORT0
PORT1
PORT2
PORT7
PORT3
PORT6
PORT4
PORT5
BP0-BP7
Function
4-bit input
4-bit Input/Output
4-bit Input/Output
(N-ch open-drain,
10 V)
1-bit output
Operation and Feature
Can be always read or tested regardless of operation mode of multiplexed pin.
Can be set in input or output mode in 4-bit units.
Ports 6 and 7 are used in pairs to input/output data
in 8-bit units.
Can be set in input or output mode in 1-bit units.
Can be set in input or output mode in 4-bit units.
Ports 4 and 5 are used in pairs to input/output data
in 8-bit units.
Output data in 1-bit units. Can be used as LCD drive
segment output pins S24-S31 through software.
Remarks
Multiplexed with INT4,
SCK, SO/SB0, and SI/SB1
Multiplexed with INT0INT2 and TI0
Multiplexed with PTO0,
PCL, and BUZ
Multiplexed with KR4-KR7
Multiplexed with LCDCL
and SYNC
Multiplexed with KR0-KR3
Can be connected to a
pull-up resistor in 1-bit
units by using mask
option.
Low drive capability
For driving CMOS load
Page 21
µ
PD75312(A), 75316(A)
21
5.2 CLOCK GENERATOR CIRCUIT
The operation of the clock generator circuit is determined by the processor clock control regiser (PPC) and
system clock control register (SCC).
This circuit can generate two types of clocks: main system clock and subsystem clock.
In addition, it can also change the instruction execution time.
• 0.95
µ
s/1.91 µs/15.3 µs (main system clock: 4.19 MHz)
• 122
µ
s (subsystem clock: 32.768 kHz)
Remarks 1: f
X = Main system clock frequency
2: f
XT = Subsystem clock frequency
3: PCC: Processor clock control register
4: SCC: System clock control register
5: *: instruction execution.
6: One clock cysle (tCY) of Φ is one machine cycle of an instruction. For tCY, refer to AC
characteristics in 11. ELECTRICAL SPECIFICATIONS.
Fig. 5-1 Clock Generator Block Diagram
VDD
VDD
XT1
XT2
X1
X2
f
XT
fX
LCD controller
/driver
Watch timer
Subsystem
clock
oscillator
Main system
clock
oscillator
1/2 1/16
1/8 to 1/4096
Frequency divider
· Basic interval timer (BT)
· Timer/event counter
· Serial interface
· Watch timer
· LCD controller/driver
· INT0 noise rejecter circuit
· Clock output circuit
Internal bus
WM.3
SCC
SCC3
SCC0
PCC
PCC0
PCC1
PCC2
PCC3
HALT*
STOP*
4
PCC2, PCC3
clear signal
STOP F/F
QS
R
Q
S
R
HALT F/F
Oscillator
disable
signal
Frequency
divider
1/4
Selector
Selector
Φ
· CPU
· INT0 noise
rejecter circuit
· Clock output
circuit
Wait release
signal from BT
RESET signal
Standby release
signal from interrupt
control circuit
★
Page 22
µ
PD75312(A), 75316(A)
22
Selector
Output
buffer
PCL/P22
Bit 2 of PMGBPORT2.2
Port 2 input/
output mode
specification
bit
P22 output
latch
Internal bus
CLOM3 0 CLOM1 CLOM0 CLOM
4
Φ
f
X
/2
3
fX/2
4
fX/2
6
From the
clock
generator
Fig. 5-2 Clock Output Circuit Configuration
Remarks:
A measures to prevent outputting narrow width pulse when selecting clock output enable/
disable is taken.
5.3 CLOCK OUTPUT CIRCUIT
The clock output circuit outputs clock pulse from the P22/PCL pin. This clock pulse is used for the remote
control output, peripheral LSIs, etc.
• Clock output (PCL) : Φ, 524, 262, 65.5 kHz (operating at 4.19 MHz)
•
Buzzer output (BUZ) : 2 kHz (operating at 4.19 MHz or 32.768 kHz)
Fig. 5-2 shows the clock output circuit configuration.
Page 23
µ
PD75312(A), 75316(A)
23
5.4 BASIC INTERVAL TIMER
The basic interval timer has these functions:
• Interval timer operation which generates a reference time interrupt
• Watchdog timer application which detects a program runaway
• Selects the wait time for releasing the standby mode and counts the wait time
• Reads out the count value
Remarks
: *: Instruction execution
Fig. 5-3 Basic Interval Timer Configuration
From the
clock generator
f
X
/2
5
fX/2
7
fX/2
9
fX/2
12
MPX
Clear
Basic interval timer
(8-bit frequency divider circuit)
3
4
8
BT
Clear
Set
signal
BT
interrupt
request flag
IRQBT
Wait release signal
for standby release
Vector
interrupt
request
signal
Internal bus
BTM3 BTM2 BTM1 BTM0 BTM
SET1*
Page 24
µ
PD75312(A), 75316(A)
24
5.5 WATCH TIMER
The
µ
PD75316(A) has a built-in 1-ch watch timer. The watch timer is configured as shown in Fig. 5-4.
• Sets the test flag (IRQW) with 0.5 sec interval.
The standby mode can be released by IRQW.
• 0.5 second interval can be generated either from the main system clock or subsystem clock.
• Time interval can be advanced to 128 times faster (3.91 ms) by setting the fast mode. This is convenient
for program debugging, test, etc.
• Fixed frequency (2.048 kHz) can be output to the P23/BUZ pin. This can be used for beep and system clock
frequency trimming.
• The frequency divider circuit can be cleared so that zero second watch start is possible.
WM7 0 0 0 WM3 WM2 WM1 WM0
Selector Frequency divider
f
W
2
6
(512 Hz: 1.95 ms)
f
W
2
7
(256 Hz: 3.91 ms)
f
LCD
INTW
(IRQW
set signal)
f
W
2
14
(2 Hz
0.5 sec)
Selector
f
W
(32.768
kHz)
f
W
16
(2.048
kHz)
Clear
f
X
128
(32.768 kHz)
f
XT
(32.768 kHz)
From the
clock
generator
WM PORT2.3 Bit 2 of PMGB
Output buffer
P23/BUZ
P23
output
latch
Port 2
input/output
mode
Bit test
instruction
8
Internal bus
( ) is for fX = 4.194304 MHz, fXT = 32.768 kHz.
Fig. 5-4 Watch Timer Block Diagram
Page 25
µ
PD75312(A), 75316(A)
25
5.6 TIMER/EVENT COUNTER
The
µ
PD75316(A) has a built-in 1-ch timer/event counter. The timer/even counter has these functions:
• Programmable interval timer operation
• Outputs square-wave signal of an arbitrary frequency to the PTO0 pin.
• Event counter operation
• Divides the TI0 pin input in N and outputs to the PTO0 pin (frequency divider operation).
• Supplies serial shift clock to the serial interface circuit.
• Count condition read out function
Page 26
µ
PD75312(A), 75316(A)
26
Internal bus
88 SET1*
— TM06 TM05 TM04 TM03 TM02 — —
TM0
PORT1.3
Input
buffer
P13/TI0
From the
clock
generator
MPX
Timer operation start signal
CP
8
8
Modulo register (8)
Comparator (8)
Count register (8)
Clear
T0
TMOD0
Reset
TOE0 PORT2.0
Bit 2 of PGMB
To serial interface
P20/PTO0
INTT0
IRQT0
set signal
()
RESET
IRQT0
clear signal
Output
buffer
TOUT
F/F
TO
enable
flag
P20
output
latch
Port 2
input/
output
mode
Coincidence
8
Fig. 5-5 Timer/Event Counter Block Diagram
1
*
2
*1: SET1: Instruction execution
2: For details, refer to Fig. 5-1.
Page 27
µ
PD75312(A), 75316(A)
27
5.7 SERIAL INTERFACE
The
µ
PD75316(A) is equipped with an 8-bit clocked serial interface that operates in the following three
modes:
• Three-line serial I/O mode
• Two-line serial I/O mode
• SBI mode (serial bus interface mode)
Page 28
µ
PD75312(A), 75316(A)
28
Internal bus
8/4
8
88
CSIM
P03/SI/SB1
P02/SO/SB0
P01/SCK
P01
output
latch
Selector Selector
Bit
test
Slave address register
(SVA)
Address comparator
Shift register (SIO)
SET CLR
Bit manipulation
(8)
(8)
Coincidence
signal
SBIC
RELT
CMDT
SO latch
Bit test
ACKT
ACKE
BSYE
Busy/
acknowledge
output
circuit
Bus release/
command/
acknowledge
detector
circuit
RELD
CMDD
ACKD
Serial clock
counter
Serial clock
control
circuit
INTCSI
control
circuit
Serial clock
selector
I
NTCSI
IRQCSI
set signal
(
)
DQ
f
X
/2
3
fX/2
4
fX/2
6
TOUT F/F
(from timer/
event counter)
External SCK
(8)
Fig. 5-6 Serial Interface Block Diagram
Page 29
µ
PD75312(A), 75316(A)
29
5.8 LCD CONTROLLER/DRIVER
The
µ
PD75316(A) is provided with a display controller that generates segment and common signals and
a segment driver and a common driver that can directly drive an LCD panel.
Figure 5-7 shows the LCD controller/driver configuration.
These LCD controller and drivers have the following functions:
• Generate segment and common signals by automatically reading the display data memory by means of
DMA
• Five display modes selectable
➀ Static
➁ 1/2 duty (1/2 bias)
➂ 1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
➄ 1/4 duty (1/3 bias)
• Four types of frame frequencies selectable in each display mode
• Up to 32 segment signals (S0-S31) and four common signals (COM0-COM3) can be output.
• Four segment signal output pins (S24-S27, S28-S31) can be used as an output port (BP0-BP3, BP4-BP7).
• Dividing resistor for LCD driving power source can be provided (by mask option).
• All bias modes and LCD drive voltages can be used.
• Current flowing to dividing resistor can be cut when display is off.
• Display data memory not used for display can be used as ordinary data memory.
• Can also operate on subsystem clock.
4
Page 30
µ
PD75312(A), 75316(A)
30
Internal bus
1FFH
3210
Display
data
memory
3210
1FEH
3210
3210
1F9H
3210
3210
1F8H
3210
3210
1ECH
3210
3210
Multiplexer
Selector
S31/BP7
Common driver
S30/BP6 S24/BP0 S23 S0 COM3 COM2 COM1 COM0 V P31/
SYNC
LC2VLC1VLC0
LCD driving
voltage control
P30/
LCDCL
Timing
controller
f
LCD
Display mode register
Display
control
register
Port 3 output latch
10
Port mode register group A
10
48448
Fig. 5-7 LCD Controller/Driver Block Diagram
Segment driver
Page 31
µ
PD75312(A), 75316(A)
31
5.9 BIT SEQUENTIAL BUFFER .... 16 BITS
The bit sequential buffer is a data memory specifically provided for bit manipulation. With this buffer,
addresses and bit specifications can be sequentially up-dated in bit manipulation operation. Therefore, this
buffer is very useful for processing long data in bit units.
Remarks:
For the pmem.@L addressing, the specification bit is shifted according to the L register.
Fig. 5-8 Bit Sequential Buffer Format
6. INTERRUPT FUNCTIONS
The µPD75316(A) has 6 different interrupt sources and multiple interrupt by software control is also
possible. The
µ
PD75316(A) is also provided with two types of test sources, of which INT2 has two types of
edge detection testable inputs.
The interrupt control circuit of the
µ
PD75316(A) has these functions:
• Hardware controlled vector interrupt function which can control whether or not to accept an interrupt by
using the interrupt flag (IExxx) and interrupt master enable flag (IME).
• The interrupt start address can be arbitrarily set.
• Interrupt request flag (IRQxxx) test function (an interrupt generation can be confirmed by means of
software).
• Standby mode release (Interrupts to be released can be selected by the interrupt enable flag).
Address bit
Symbol
L register
32103210 32103210
L = F L = C L = B L = 8 L = 7 L = 4 L = 3 L = 0
BSB3 BSB2 BSB1 BSB0
DECS L
INCS L
FC3H FC2H FC1H FC0H
Page 32
µ
PD75312(A), 75316(A)
32
Internal bus
213
IM2 IM1 IM0
IRQBT
INT4
/P00
INT0
/P10
INT1
/P11
INT2
/P12
KR0/P60
KR7/P73
Noise
elimination
circuit
INT
BT
INTCSI
INTT0
INTW
Selector
Both edge
detection
circuit
Edge
detection
circuit
Edge
detection
circuit
Rising edge
detection
circuit
Falling edge
detection
circuit
IRQ4
IRQ0
IRQ1
IRQCSI
IRQT0
IRQW
IRQ2
IM2
Interrupt enable flag (IE )×××
IME
VRQn
Decoder
IST0
Priority control
circuit
Vector table
address
generator
Standby
release signal
Fig. 6-1 Interrupt Control Block Diagram
Page 33
µ
PD75312(A), 75316(A)
33
An interrupt request signal from a
hardware whose operation is
enabled by the interrupt enable flag
or the RESET signal input
Can operate only when the external
SCK input is selected for the serial
clock
7. STANDBY FUNCTIONS
The µPD75316(A) has two different standby modes (STOP mode and HALT mode) to reduce the power
consumption while waiting for program execution.
Table 7-1 Each Status in Standby Mode
STOP instrtuction HALT instruction
Can be set either with the main
system clock or the subsystem clock
Only the main system clock stops its
operation.
Only the CPU clock Φ stops its
operation. (oscillation continues)
No operation Operation (Sets IRQBT at reference
time interval) *
STOP Mode
HALT Mode
Can be set only when operating on
the main system clock
Can operate *
Can operate only when the TI0 pin
input is selected for the count clock
Can operate *
Can operateCan operate when fXT is selected for
the count clock
Can operate
Can operate only when fXT is
selected for LCDCL
INT1, INT2, and INT4 can operate.
Only INT0 cannot operate.
No operation
Clock Generator
Basic Interval
Timer
Serial Interface
Timer/Event
Counter
Watch Timer
LCD Controller
External Interrupt
CPU
Setting Instruction
Operation
Status
System Clock for Setting
Release Signal
*: Operation is possible only when the main system clock is operating.
An interrupt request signal from a
hardware whose operation is enabled
by the interrupt enable flag or the
RESET signal input
Page 34
µ
PD75312(A), 75316(A)
34
8. RESET FUNCTION
When the RESET signal is input, the µPD75316(A) is reset and each hardware is initialized as indicated in
Table 8-1. Fig. 8-1 shows the reset operation timing.
RESET input
Wait
(31.3ms/4.19MHz)
Operation mode
or standby mode
HALT mode Operation mode
Internal reset operation
Fig. 8-1 Reset Operation by RESET Input
Hardware RESET Input in Standby Mode RESET Input during Operation
Program Counter (PC) The contents of the lower 6 bits
of address 0000H of the program
memory are set to PC13-8, and
the contents of address 0001H
are set to PC7-0.
The contents of the lower 6 bits
of address 0000H of the program
memory are set to PC13-8, and
the contents of address 0001H
are set to PC7-0.
PSW Carry Flag (CY) Retained Undefined
Skip Flag (SK0-2) 0 0
Interrupt Status Flag (IST0) 0 0
Bank Enable Flag (MBE) The contents of bit 7 of address
0000H of the program memory
are set to MBE.
The contents of bit 7 of address
0000H of the program memory
are set to MBE.
Stack Pointer (SP) Undefined Undefined
Data Memory (RAM) Retained * Undefined
General-Purpose Register
(X, A, H, L, D, E, B, C)
Retained Undefined
Bank Selection Register (MBS) 0 0
Basic Interval
Timer
Counter (BT) Undefined Undefined
Timer/Event
Counter
Counter (T0) 0 0
Module Register
(TMOD0)
FFH
FFH
Mode Register (TM0) 0 0
TOE0, TOUT F/F 0, 0 0, 0
Mode Register (BTM) 0 0
Mode Register (WM) 0
Watch Timer
0
*: Data of address 0F8H to 0FDH of the data memory becomes undefined when a RESET signal is input.
Table 8-1 Status of Each Hardware after Reset (1/2)
Page 35
µ
PD75312(A), 75316(A)
35
Serial Shift Register (SIO) Retained Undefined
Interface
Operation Mode 0 0
Register (CSIM)
SBI Control Register 0 0
(SBIC)
Slave Address Register Retained Undefined
(SVA)
Clock Processor Clock Control 0 0
Generator, Register (PCC)
Clock Output
System Clock Control 0 0
Circuit
Register (SCC)
Clock Output Mode 0 0
Register (CLOM)
LCD Display Mode Register 0 0
Controller (LCMD)
Display Control 0 0
Register (LCDC)
Interrupt Interrupt Request Flag Reset (0) Reset (0)
Function (IRQxxx)
Interrupt Enable Flag 0 0
(IExxx)
Interrupt Master Enable 0 0
Flag (IME)
INT0, INT1, INT2 Mode 0, 0, 0 0, 0, 0
Registers (IM0,1, 2)
Digital Port Output Buffer Off Off
Output Latch Clear (0) Clear (0)
Input/Output Mode 0 0
Register (PMGA, B)
Pull-Up Resistor 0 0
Specification Register
(POGA)
Bit Sequential Buffer (BSB0-3) Retained Specified
Hardware RESET Input during OperationRESET Input in Standby Mode
Table 8-1 Status of Each Hardware after Reset (2/2)
Page 36
µ
PD75312(A), 75316(A)
36
*: Only even addresses can be described as mem for 8-bit data processing.
9. INSTRUCTION SET
(1) Operand representation and description
Describe one or more operands in the operand field of each instruction according to the operand
representation and description methods of the instruction (for details, refer to RA75X Assembler Package
User's Manual - Language (EEU-730)). With some instructions, only one operand should be selected from
several operands. The uppercase characters, +, and – are keywords and must be described as is.
Describe an appropriate numeric value or label as immediate data.
The symbols in the register and flag symbols can be described as labels in the places of mem, fmem, pmem,
and bit (for details, refer to
µ
PD75308 User's Manual (IEM-5016)). However, fmem and pmem restricts
the label that can be described.
Representation Description
reg X, A, B, C, D, E, H, L
reg1 X, B, C, D, E, H, L
rp XA, BC, DE, HL
rp1 BC, DE, HL
rp2 BC, DE
rpa HL, DE, DL
rpa1 DE, DL
n4 4-bit immediate data or label
n8 8-bit immediate data or label
mem * 8-bit immediate data or label
bit 2-bit immediate data or label
fmem FB0H to FBFH,FF0H to FFFH immediate data or label
pmem FC0H to FFFH immediate data or label
addr
µ
PD75312(A) 0000H-2F7FH immediate data or label
µ
PD75316(A) 0000H-3F7FH immediate data or label
caddr 12-bit immediate data or label
faddr 11-bit immediate data or label
taddr 20H to 7FH immediate data (where bit0 = 0) or label
PORTn PORT0 to PORT7
IExxx IEBT, IECSI, IET0, IE0, IE1, IE2, IE4, IEW
MBn MB0, MB1, MB15
Page 37
µ
PD75312(A), 75316(A)
37
(2) Legend of operation field
A : A register; 4-bit accumulator
B : B register; 4-bit accumulator
C : C register; 4-bit accumulator
D : D register; 4-bit accumulator
E : E register; 4-bit accumulator
H : H register; 4-bit accumulator
L : L register; 4-bit accumulator
X : X register; 4-bit accumulator
XA : Register pair (XA); 8-bit accumulator
BC : Register pair (BC); 8-bit accumulator
DE : Register pair (DE); 8-bit accumulator
HL : Register pair (HL); 8-bit accumulator
PC : Program counter
SP : Stack pointer
CY : Carry flag; or bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
PORTn : Port n (n = 0 to 7)
IME : Interrupt mask enable flag
IExxx : Interrupt enable flag
MBS : Memory bank selector register
PCC : Processor clock control register
.
: Delimiter of address and bit
(xx) : Contents addressed by xx
xxH : Hexadecimal data
Page 38
µ
PD75312(A), 75316(A)
38
(3) Symbols in addressing area field
*1 MB = MBE . MBS
(MBS = 0, 1, 15)
*2 MB = 0
*3 MBE = 0 : MB = 0 (00H-7FH) Data memory
MB = 15 (80H-FFH) addressing
MBE = 1 : MB = MBS (MBS = 0, 1, 15)
*4 MB = 15, fmem = FB0H-FBFH,
FF0H-FFFH
*5 MB = 15, pmem = FC0H-FFFH
*6
µ
PD75312(A) addr = 0000H-2F7FH
µ
PD75316(A) addr = 0000H-3F7FH
*7 addr = (Current PC) – 15 to (Current PC) – 1
(Current PC) + 2 to (Current PC) + 16
*8
µ
PD75312(A) caddr = 0000H-0FFFH (PC13 = 0, PC12 = 0) or Program
1000H-1FFFH (PC13 = 0, PC12 = 1) or memory
2000H-2F7FH (PC13 = 1, PC12 = 0) addressing
µ
PD75316(A) caddr = 0000H-0FFFH (PC13 = 0, PC12 = 0) or
1000H-1FFFH (PC13 = 0, PC12 = 1) or
2000H-2FFFH (PC13 = 1, PC12 = 0) or
3000H-3F7FH (PC13 = 1, PC12 = 1)
*9 faddr = 0000H-07FFH
*10 taddr = 0020H-007FH
Remarks 1: MB indicates memory bank that can be accessed.
2: In *2, MB = 0 regardless of MBE and MBS.
3: In *4 and *5, MB = 15 regardless of MBE and MBS.
4: *6 to *10 indicate areas that can be addressed.
(4) Machine cycle field
In this field, S indicates the number of machine cycles required when an instruction having a skip
function skips. The value of S varies as follows:
• When no instruction is skipped .................................................................................. S = 0
• When 1-byte or 2-byte instruction is skipped ........................................................... S = 1
• When 3-byte instruction (BR ! addr or CALL ! addr) is skipped ............................ S = 2
Note
: The GETI instruction is skipped in one machine cycle.
One machine cycle equals to one cycle of the CPU clock Φ, (=tCY), and can be changed in three
steps depending on the setting of the processor clock control register (PCC).
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Ma- Ad-
Instruc- Mne-
Operand Bytes
chine
Operation
dress- Skip
tions monics Cyc- ing Conditions
les Area
Transfer MOV A, #n4 1 1 A ← n4 String effect A
reg1, #n4 2 2 reg1 ← n4
XA, #n8 2 2 XA ← n8 String effect A
HL, #n8 2 2 HL ← n8 String effect B
rp2, #n8 2 2 rp2 ← n8
A, @HL 1 1 A ← (HL) *1
A, @rpa1 1 1 A ← (rpa1) *2
XA, @HL 2 2 XA ← (HL) *1
@HL, A 1 1 (HL) ← A*1
@HL, XA 2 2 (HL) ← XA *1
A, mem 2 2 A ← (mem) *3
XA, mem 2 2 XA ← (mem) *3
mem, A 2 2 (mem) ← A*3
mem, XA 2 2 (mem) ← XA *3
A, reg 2 2 A ← reg
XA, rp 2 2 XA ← rp
reg1, A 2 2 reg1 ← A
rp1, XA 2 2 rp1 ← XA
XCH A, @HL 1 1 A ↔ (HL) *1
A, @rpa1 1 1 A ↔ (rpa1) *2
XA, @HL 2 2 XA ↔ (HL) *1
A, mem 2 2 A ↔ (mem) *3
XA, mem 2 2 XA ↔ (mem) *3
A, reg1 1 1 A ↔ reg1
XA, rp 2 2 XA ↔ rp
MOVT XA, @PCDE 1 3 XA ← (PC13-8+DE)ROM
XA, @PCXA 1 3 XA ← (PC13-8+XA)ROM
Arith- ADDS A, #n4 1 1+S A ← A+n4 carry
metic A, @HL 1 1+S A ← A+(HL) *1 carry
Opera- ADDC A, @HL 1 1 A, CY ← A+(HL)+CY *1
tion SUBS A, @HL 1 1+S A ← A-(HL) *1 borrow
SUBC A, @HL 1 1 A, CY ← A-(HL)-CY *1
AND A, #n4 2 2 A ← A ∧ n4
A, @HL 1 1 A ← A ∧ (HL) *1
OR A, #n4 2 2 A ← A ∨ n4
A, @HL 1 1 A ← A ∨ (HL) *1
XOR A, #n4 2 2 A ← A ∨ n4
A, @HL 1 1 A ← A ∨ (HL) *1
Accumu- RORC A 1 1 CY ← A0, A3 ← CY, An-1 ← An
lator
Manipu-
NOT A 2 2 A ← A
lation
Table Reference
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Operation
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tions monics Cyc- ing Conditions
les Area
Incre- INCS reg 1 1+S reg ← reg+1 reg = 0
ment/ @HL 2 2+S (HL) ← (HL)+1 *1 (HL) = 0
Decre- mem 2 2+S (mem) ← (mem)+1 *3 (mem) = 0
ment DECS reg 1 1+S reg ← reg-1 reg = FH
Compare SKE reg, #n4 2 2+S Skip if reg = n4 reg = n4
@HL, #n4 2 2+S Skip if (HL) = n4 *1(HL) = n4
A, @HL 1 1+S Skip if A = (HL) *1 A = (HL)
A, reg 2 2+S Skip if A = reg A = reg
Carry SET1 CY 1 1 CY ← 1
flag CLR1 CY 1 1 CY ← 0
Manipu- SKT CY 1 1+S Skip if CY = 1 CY = 1
lation NOT1 CY 1 1 CY ← CY
Memory/ SET1 mem.bit 2 2 (mem.bit) ← 1*3
Bit fmem.bit 2 2 (fmem.bit) ← 1 *4
Manipu- pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 1*5
lation @H+mem.bit 2 2 (H + mem3-0.bit) ← 1*1
CLR1 mem.bit 2 2 (mem.bit) ← 0 *3
fmem.bit 2 2 (fmem.bit) ← 0 *4
pmem.@L 2 2 (pmem7-2 + L3-2.bit(L1-0)) ← 0*5
@H+mem.bit 2 2 (H+mem3-0.bit) ← 0*1
SKT mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1
fmem.bit 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1
pmem.@L 2 2+S
Skip if (pmem
7-2+L3-2
.bit (L
1-0
)) = 1
*5 (pmem.@L) = 1
@H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 1 *1
(@H+mem.bit) = 1
SKF mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0
fmem.bit 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0
pmem.@L 2 2+S
Skip if (pmem7-2 +L3-2.bit (L1-0)) = 0
*5 (pmem.@L) = 0
@H+mem.bit 2 2+S Skip if (H + mem3-0.bit) = 0 *1
(@H+mem.bit) = 0
SKTCLR
fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1
pmem.@L 2 2+S Skip if (pmem7-2+L3-2.bit *5 (pmem.@L) = 1
(L1-0)) = 1 and clear
@H+mem.bit 2 2+S
Skip if (H+mem3-0.bit) = 1 and clear
*1
(@H+mem.bit) = 1
AND1 CY,fmem.bit 2 2 CY ← CY ∧ (fmem.bit) *4
CY,pmem.@L 2 2
CY ← CY ∧ (pmem7-2+L3-2.bit(L1-0))
*5
CY,@H+mem.bit
2 2 CY ← CY ∧ (H+mem3-0.bit) *1
OR1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4
CY,pmem.@L 2 2
CY ← CY ∨ (pmem7-2+L3-2.bit (L1-0))
*5
CY,@H+mem.bit
2 2 CY ← CY ∨ (H+mem3-0.bit) *1
XOR1 CY,fmem.bit 2 2 CY ← CY ∨ (fmem.bit) *4
CY,pmem.@L 2 2
CY ← CY
∨
(pmem
7-2+L3-2
.bit (L
1-0
))
*5
CY,@H+mem.bit
2 2 CY ← CY ∨ (H+mem3-0.bit) *1
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Ma- Ad-
Instruc- Mne-
Operand Bytes
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Operation
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tions monics Cyc- ing Conditions
les Area
Branch BR addr — — PC13-0 ← addr *6
(The most suitable instruction
is selectable from among BR
!addr, BRCB !caddr, and BR
$addr depending on the
assembler.)
!addr 3 3 PC13-0 ← addr *6
$addr 1 2 PC13-0 ← addr *7
BRCB !caddr 2 2 PC13-0 ← PC13,12 + caddr11-0 *8
CALL !addr 3 3 (SP-4)(SP-1)(SP-2) ← PC11-0 *6
(SP-3) ← MBE, 0, PC13, PC12
PC13-0 ← addr, SP ← SP-4
CALLF !faddr 2 2 (SP-4)(SP-1)(SP-2) ← PC11-0 *9
(SP-3) ← MBE, 0, PC13, PC12
PC13-0 ← 00, faddr, SP ← SP-4
RET 1 3 MBE, PC13, PC12 ← (SP+1)3, 1, 0
PC11-0 ← (SP)(SP+3)(SP+2)
SP ← SP+4
RETS 1 3+S MBE, PC13, PC12 ← (SP+1)3, 1, 0 Undefined
PC11-0 ← (SP)(SP+3)(SP+2)
SP ← SP+4,
then skip unconditionally
RETI 1 3 PC13, PC12 ← (SP+1)1, 0
PC11-0 ← (SP)(SP+3)(SP+2)
PSW ← (SP+4)(SP+5), SP ← SP+6
PUSH rp 1 1 (SP-1)(SP-2) ← rp, SP ← SP-2
BS 2 2
(SP-1) ← MBS, (SP-2) ← 0, SP ← SP-2
POP rp 1 1 rp ← (SP+1)(SP), SP ← SP+2
BS 2 2 MBS ← (SP+1), SP ← SP+2
Inter- EI 2 2 IME ← 1
rupt IExxx 2 2 IExxx ← 1
Control DI 2 2 IME ← 0
IExxx 2 2 IExxx ← 0
I/O IN A,PORTn 2 2 A ← PORTn (n = 0-7)
XA,PORTn 2 2
XA
←
PORTn+1,PORTn
(n = 4, 6)
OUT PORTn,A 2 2 PORTn ← A (n = 2-7)
PORTn,XA 2 2 PORTn+1,PORTn ← XA (n = 4, 6)
CPU HALT 2 2 Set HALT Mode (PCC.2 ← 1)
Control STOP 2 2 Set STOP Mode (PCC.3 ← 1)
NOP 1 1 No Operation
Special SEL MBn 2 2 MBS ← n (n = 0, 1, 15)
GETI taddr 1 3
.
Where TBR instruction, *10
PC13-0 ← (taddr)5-0+(taddr+1)
.
Where TCALL instruction,
(SP-4)(SP-1)(SP-2) ← PC11-0
(SP-3) ← MBE, 0, PC13, PC12
PC13-0 ← (taddr)5-0+(taddr+1)
SP ← SP-4
.
Except for TBR and TCALL Depends on
instructions, referenced
Instruction execution of instruction
(taddr)(taddr+1)
Note: When executing the IN/OUT instruction, MBE = 0, or MBE = 1, and MBS = 15.
Remarks: The TBR and TCALL instructions are the assembler pseudo-instructions for the table definition
of GETI instruction.
Subroutine/
Stack
Control
......................................................... .............................
......................................................... .............................
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10. SELECTION OF MASK OPTION
The following mask operations are available and can be specified for each pin.
Pin Mask Option
P40-P43, • With pull-up resistor (Specification in bit units)
P50-P53 • Without pull-up resistor (Specification in bit units)
VLC0-VLC2, • With dividing resistor for LCD drive power source (Specification in 4-bit units)
BIAS • Without dividing resistor for LCD drive power source (Specification in 4-bit units)
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11. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Parameter Symbol Conditions Ratings Unit
Supply Voltage VDD -0.3 to +7.0 V
VI1 Other than ports 4, 5 -0.3 to VDD+0.3 V
Input Voltage VI2 Ports 4, 5 w/pull-up -0.3 to VDD+0.3
V
resistor
Open drain -0.3 to +11 V
Output Voltage VO -0.3 to VDD+0.3 V
High-Level Output IOH 1 pin Peak -10 mA
Current rms -5 mA
All pins Peak -30 mA
rms -5 mA
Low-Level Output IOL* 1 pin Peak 10 mA
Current rms 5 mA
Other than ports 0, 2, 3, 5 Peak 100 mA
rms 60 mA
Total of ports 4, 6, 7 Peak 100 mA
rms 50 mA
Operating Temperature Topt -40 to +85 °C
Storage Temperature Tstg -65 to +150 °C
*: rms = Peak value x √Duty
CAPACITANCE (Ta = 25°C, VDD = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Input Capacitance CIN f = 1 MHz 15 pF
Output Capacitance COUT Pins other than thosemeasured are at 0 V 15 pF
Input/Output CIO
15 pF
Capacitance
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MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(T
a = -40 to +85°C, VDD = 2.7 to 6.0 V)
Oscillator
Recommended
Item Conditions MIN. TYP. MAX. Unit
Constants
Ceramic *
3
Oscillation
1.0 5.0
*
3
MHz
frequency(fX)*
1
Oscillation stabiliza- After VDD came to
tion time*
2
MIN. of oscillation
voltage range
4ms
Crystal *
3
Oscillation
1.0 4.19 5.0
*
3
MHz
frequency (fX)*
1
Oscillation stabiliza- VDD = 4.5 to 6.0 V 10 ms
tion time*
2
30 ms
External Clock X1 input frequency
1.0 5.0
*
3
MHz
(fX)*
1
X1 input high-,
low-level widths
(tXH, tXL) 100 500 ns
*1: The oscillation frequency and X1 input frequency are indicated only to express the characteristics
of the oscillator circuit.
For instruction execution time, refer to AC Characteristics.
2: Time required for oscillation to stabilize after V
DD reaches the minimum value of the oscillation
voltage range or the STOP mode has been released.
3: When the oscillation frequency is 4.19 MHz < fx ≤ 5.0 MHz, do not select PCC = 0011 as the
instruction execution time: otherwise, one machine cycle is set to less than 0.95
µ
s, falling short
of the rated minimum value of 0.95
µ
s.
SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS
(T
a = -40 to +85°C, VDD = 2.7 to 6.0 V)
Oscillator
Recommended
Item Conditions MIN. TYP. MAX. Unit
Constants
Crystal Oscillation
32 32.768 35 kHz
frequency (fXT)
Oscillation stabiliza- VDD = 4.5 to 6.0 V 1.0 2 s
tion time*
10 s
External Clock XT1 input frequency
32 100 kHz
(fXT)*
XT1 input high-,
low-level widths 5 15
µ
s
(tXTH, tXTL)
X1 X2
C1 C2
V
DD
X1 X2
C1 C2
V
DD
X1 X2
PD74HCU04
µ
XT1 XT2
R
C3 C4
V
DD
XT1 XT2
Open
*: Time required for oscillation to stabilize after VDD reaches the minimum value of the oscillation
voltage range.
★
Page 45
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45
Note: When using the oscillation circuit of the main system clock and subsystem clock, wire the portion
enclosed in dotted line in the figures as follows to avoid adverse influences on the wiring capacity:
• Keep the wiring length as short as possible.
• Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines
through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillator circuit at the same potential as V
DD.
Do not connect the power source pattern through which a high current flows.
• Do not extract signals from the oscillation circuit.
The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the
current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise more
easily than the main system clock oscillation circuit. When using the subsystem clock, therefore,
exercise utmost care in wiring the circuit.
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DC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
High-Level Input VIH1 Ports 2, 3 0.7VDD VDD V
Voltage
VIH2 Ports 0, 1, 6, 7, RESET 0.8VDD VDD V
VIH3 Ports 4, 5 w/pull-up resistor 0.7VDD VDD V
Open-drain 0.7VDD 10 V
VIH4 X1, X2, XT1 VDD-0.5 VDD V
Low-level Input VIL1 Ports 2, 3, 4, 5 0 0.3VDD V
Voltage
VIL2 Ports 0, 1, 6, 7, RESET 0 0.2VDD V
VIL3 X1, X2, XT1 0 0.4 V
High-Level Output VOH1 VDD = 4.5 to 6.0 V VDD-1.0 V
Voltage IOH = -1 mA
IOH = -100 µAVDD-0.5 V
VOH2 VDD = 4.5 to 6.0 V VDD-2.0 V
IOH = -100 µA
IOH = -30 µAVDD-1.0 V
Low-Level Output VOL1 Ports 3, 4, and 5
0.2 1.0 V
Voltage VDD = 4.5 to 6.0 V
IOL = -15 mA
VDD = 4.5 to 6.0 V 0.4 V
IOL = 1.6 mA
IOL = 400 µA 0.5 V
SB0, 1 Open-drain Pull-up
0.2VDD V
resistor ≥ 1 kΩ
VOL2 VDD = 4.5 to 6.0 V 1.0 V
IOL = 100 µA
IOL = 50 µA 1.0 V
High-Level Input ILIH1 VIN = VDD Other than below 3
µ
A
Leakage Current
ILIH2 X1, X2, XT1 20
µ
A
ILIH3 VIN = 10 V Ports 4, 5
20
µ
A
(open-drain)
Low-Level Input ILIL1 VIN = 0 V Other than below -3
µ
A
Leakage Current
ILIL2 X1, X2, XT1 -20
µ
A
High-Level Output ILOH1 VOUT = VDD Other than below 3
µ
A
Leakage Current
ILOH2 VOUT = 10 V Ports 4, 5
20
µ
A
(open-drain)
Low-Level Output ILOL VOUT = 0 V
-3
µ
A
Leakage Current
Internal Pull-Up Resistor RL1
Ports 0, 1, 2, 3, 6, 7
VDD = 5.0 V±10% 15 40 80 kΩ
(except P00) VIN = 0V
VDD = 3.0 V±10% 30 300 kΩ
RL2 Ports 4, 5 VDD = 5.0 V±10% 15 40 70 kΩ
V
OUT
= VDD-2.0 V
VDD = 3.0 V±10% 10 60 kΩ
LCD Drive Voltage VLCD 2.5 VDD V
LCD Step-down Resistor RLCD 60 100 150 kΩ
LCD Output Voltage VODC IO = ±5 µA0±0.2 V
Deviation (Common) *
1
LCD Output Voltage VODS IO = ±1 µA0±0.2 V
Deviation (Segment)
Ports 0, 2, 3, 4, 5,
6, 7, and 8
BP0-7
(with two IOH
outputs)
Ports 0, 2, 3, 6, 7
and BIAS
BP0-7
(with two IOL
outputs)
VLCD0 = VLCD
VLCD1 = VLCD×2/3
VLCD2 = VLCD×1/3
2.7 V ≤ VLCD ≤ VDD
(to be cont'd)
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Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply Current *2IDD1 4.19 MHz*3 crystal VDD = 5 V±10%*
4
2.5 8 mA
oscillator
VDD = 3 V±10%*
5
0.35 1.2 mA
IDD2
C1 = C2 = 22pF
HALT mode VDD = 5 V±10% 500 1500
µ
A
VDD = 3 V±10% 150 450
µ
A
IDD3 32 kHz*6 crystal VDD = 3 V±10% 30 90
µ
A
IDD4
oscillato
HALT mode VDD = 3 V±10% 5 15
µ
A
IDD5 XT1 = 0 V VDD = 5 V±10% 0.5 20
µ
A
STOP mode
V
DD
= 3 V±10%
0.1 10
µ
A
Ta = 25°C 0.1 5
µ
A
*1: "Voltage deviation" means the difference between the ideal segment or common output value
(V
LCDn: n = 0, 1, 2) and output voltage.
2: Currents for the built-in pull-up resistor and the LCD step-down resistor are not included.
3: Including when the subsystem clock is operated.
4: When operand in the high-speed mode with the processor clock control register (PCC) set to 0011.
5: When operated in the low-speed mode with the PCC set to 0000.
6: When operated with the subsystem clock by setting the system clock control register (SCC) to 1001
to stop the main system clock operation.
(cont'd)
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AC CHARACTERISTICS (Ta = -40 to +85°C, VDD = 2.7 to 6.0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
CPU Clock Cycle Time tCY w/main system clock VDD = 4.5 to 6.0 V 0.95 64
µ
s
(Minimum Instruction
3.8 64
µ
s
Execution Time
w/sub-system clock
114 122 125
µ
s
= 1 Machine Cycle)*
1
TI0 Input Frequency fTI VDD = 4.5 to 6.0 V 0 1 MHz
0 275 kHz
TI0 Input High-, Low- tTIH,VDD = 4.5 to 6.0 V 0.48
µ
s
Level Widths t
TIL
1.8
µ
s
Interrupt Input High-, tINTH, INT0 *2
µ
s
Low-Level Widths t
INTL
INT1, 2, 4 10
µ
s
KR0-7 10
µ
s
RESET Low-Level Width tRSL 10
µ
s
0123 456
0.5
1
2
3
4
5
6
30
Supply voltage V
DD
[V]
Cycle time t
CY
[ s]
tCY vs V
DD
(with main system clock)
µ
64
70
Operation
guaranteed
range
*1: The CPU clock (Φ) cycle time is
determined by the oscillation frequency
of the connected oscillator, system clock
control register (SCC), and processor
clock control register (PCC).
The figure on the right is cycle time t
CY
vs. supply voltage VDD characteristics
at the main system clock.
2: 2tCY or 128/fX depending on the setting
of the interrupt mode register (IM0).
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SERIAL TRANSFER OPERATION
Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY1 VDD = 4.5 to 6.0 V 1600 ns
3800 ns
SCK High-, Low-Level tKL1 VDD = 4.5 to 6.0 V tKCY1/2-50 ns
Widths
tKH1 tKCY1/2-150 ns
SI Set-Up Time (vs. SCK ↑) tSIK1 150 ns
SI Hold Time (vs. SCK ↑ )tKSI1 400 ns
SCK ↓→ SO Output tKSO1 RL = 1 kΩ,VDD = 4.5 to 6.0 V 250 ns
Delay Time CL = 100 pF*
1000 ns
TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY2 VDD = 4.5 to 6.0 V 800 ns
3200 ns
SCK High-, Low-Level tKL2 VDD = 4.5 to 6.0 V 400 ns
Widths
tKH2 1600 ns
SI Set-Up Time (vs. SCK ↑) tSIK2 100 ns
SI Hold Time (vs. SCK ↑)tKSI2 400 ns
SCK ↓→ SO Output tKSO2 RL = 1 kΩ, CL = 100 pF* VDD = 4.5 to 6.0 V 300 ns
Delay Time
1000 ns
*: RL and CL are load resistance and load capacitance of the SO output line.
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SBI MODE (SCK: internal clock output (master))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY3 VDD = 4.5 to 6.0 V 1600 ns
3800 ns
SCK High-, Low-Level tKL3 VDD = 4.5 to 6.0 V tKCY3/2-50 ns
Widths t
KH3
tKCY3/2-150 ns
SB0, 1 Set-Up Time tSIK3
150 ns
(vs. SCK ↑ )
SB0, 1 Hold Time tKSI3
tKCY3/2 ns
(vs. SCK ↑ )
SCK ↓→ SB0, 1 Output tKSO3 RL = 1 kΩ,VDD = 4.5 to 6.0 V 0 250 ns
Delay Time CL = 100 pF*
0 1000 ns
SCK ↑→ SB0, 1 ↓ tKSB tKCY3 ns
SB0,1 ↓→ SCK tSBK tKCY3 ns
SB0, 1 Low-Level Width tSBL tKCY3 ns
SB0, 1 High-Level Width tSBH tKCY3 ns
SBI MODE (SCK: external clock input (slave))
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK Cycle Time tKCY4 VDD = 4.5 to 6.0 V 800 ns
3200 ns
SCK High-, Low-Level tKL4 VDD = 4.5 to 6.0 V 400 ns
Widths tKH4
1600 ns
SB0, 1 Set-Up Time tSIK4
100 ns
(vs. SCK ↑ )
SB0, 1 Hold Time tKSI4
tKCY4/2 ns
(vs. SCK ↑ )
SCK ↓→ SB0, 1 Output tKSO4 RL = 1 kΩ,VDD = 4.5 to 6.0 V 0 300 ns
Delay Time CL = 100 pF*
0 1000 ns
SCK ↑→ SB0, 1 ↓ tKSB tKCY4 ns
SB0,1 ↓→ SCK ↓ tSBK tKCY4 ns
SB0, 1 Low-Level Width tSBL tKCY4 ns
SB0, 1 High-Level Width tSBH tKCY4 ns
*: RL and CL are load resistance and load capacitance of the SB0 and SB1 output lines.
Page 51
µ
PD75312(A), 75316(A)
51
AC TIMING TEST POINT (excluding X1 and XT1 inputs)
X1 input
V
DD
–0.5V
0.4 V
t
XL
t
XH
1/f
X
XT1 input
V
DD
–0.5V
0.4 V
t
XTL
t
XTH
1/f
XT
TI0
t
TIL
t
TIH
1/f
TI
CLOCK TIMING
TI0 TIMING
Test points
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Page 52
µ
PD75312(A), 75316(A)
52
SERIAL TRANSFER TIMING
THREE-LINE SERIAL I/O MODE:
SCK
t
KL1
t
KH1
t
KCY1
Output data
t
SIK1
t
KSI1
t
KSO1
Input data
SI
SO
TWO-LINE SERIAL I/O MODE:
SCK
t
KL2
t
KH2
t
KCY2
t
SIK2
t
KSI2
SB0,1
t
KSO2
Page 53
µ
PD75312(A), 75316(A)
53
SERIAL TRANSFER TIMING
BUS RELEASE SIGNAL TRANSFER:
SCK
t
KL3,4
t
KCY3,4
t
SIK3,4
t
KSI3,4
t
KSO3,4
SB0,1
t
KH3,4
t
SBK
t
SBH
t
SBL
t
KSB
COMMAND SIGNAL TRANSFER:
RESET INPUT TIMING:
SCK
t
KL3,4
t
KCY3,4
t
SIK3,4
t
KSI3,4
t
KSO3,4
SB0,1
t
KH3,4
t
SBK
t
KSB
INTERRUPT INPUT TIMING:
INT0, 1, 2, 4
KR0-7
t
INTL
t
INTH
RESET
t
RSL
Page 54
µ
PD75312(A), 75316(A)
54
LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE
(T
a = –40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data Retention Supply VDDDR
2.0 6.0 V
Voltage
Data Retention Supply IDDDR VDDDR = 2.0 V
0.1 10
µ
A
Current*
1
Release Signal Set Time tSREL 0
µ
s
Oscillation Stabilization tWAIT Released by RESET 217/fX ms
Wait Time*
2
Released by interrupt *3 ms
*1: Does not include current flowing through internal pull-up resistor
2: The oscillation stabilization wait time is the time during which the CPU is stopped to prevent
unstable operation when oscillation is started.
3: Depends on the setting of the basic interval timer mode register (BTM) as follows:
BTM3 BTM2 BTM1 BTM0 WAIT time ( ): fX = 4.19 MHz
– 0002
20
/fX (approx. 250 ms)
– 0112
17
/fX (approx. 31.3 ms)
– 1012
15
/fX (approx. 7.82 ms)
– 1112
13
/fX (approx. 1.95 ms)
DATA RETENTION TIMING (releasing STOP mode by RESET)
DATA RETENTION TIMING (standby release signal: releasing STOP mode by interrupt)
STOP mode
Data retention mode
STOP instruction
execution
V
DD
RESET
V
DDDR
t
SREL
t
WAIT
Operation
mode
Internal reset operation
HALT mode
STOP mode
Data retention mode
STOP instruction execution
V
DD
V
DDDR
t
SREL
t
WAIT
Operation
mode
HALT mode
Standby release signal
(interrupt request)
Page 55
µ
PD75312(A), 75316(A)
55
12. PACKAGE DRAWINGS
N
A
M
F
B
64
65
40
K
L
80 PIN PLASTIC QFP (14×20)
80
1
25
24
41
G
D
C
P
detail of lead end
S
Q
5°±5°
M
I
H
J
P80GF-80-3B9-2
ITEM MILLIMETERS INCHES
A
B
C
D
F
G
H
I
J
K
L
23.6±0.4
14.0±0.2
0.8
0.35±0.10
0.15
20.0±0.2
0.929±0.016
0.039
0.031
0.006
0.031 (T.P.)
0.795
NOTE
M
N
0.15
0.15
1.8±0.2
0.8 (T.P.)
0.006
0.006
+0.004
–0.003
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
0.071
0.014
0.551
0.8±0.2
0.031
P 2.7 0.106
0.693±0.016
17.6±0.4
1.0
+0.009
–0.008
Q
0.1±0.1
0.004±0.004
S 3.0 MAX. 0.119 MAX.
+0.10
–0.05
+0.009
–0.008
+0.004
–0.005
+0.009
–0.008
+0.008
–0.009
Page 56
Page 57
µ
PD75312(A), 75316(A)
57
13. RECOMMENDED SOLDERING CONDITIONS
It is recommended that µPD75316(A) be soldered under the following conditions.
For details on the recommended soldering conditions, refer to Information Document "Semiconductor
Devices Mounting Manual" (IEI-616).
The soldering methods and conditions are not listed here, consult NEC.
A model that can be soldered under the more stringent conditions (infrared reflow peak
temperature: 235°C, number of times: 2, and an extended number of days) is also available.
For details, consult NEC.
Notice
Table 13-1 Soldering Conditions
µ
PD75312GF(A) - xxx - 3B9: 80-pin plastic QFP (14×20 mm)
µ
PD75316GF(A) - xxx - 3B9: 80-pin plastic QFP (14×20 mm)
Soldering Method Soldering Conditions
Symbol for Recommended
Condition
Infrared Reflow Package peak temperature: 230°C, IR30-00-1
time: 30 seconds max. (210°C min.),
number of times: 1
VPS Package peak temperature: 215°C, VP15-00-1
time: 40 seconds max. (200°C min.),
number of times: 1
Wave Soldering Soldering bath temperature: 260°C max., WS60-00-1
time: 10 seconds max., number of times: 1,
pre-heating temperature: 120°C max. (package surface
temperature)
Pin Partial Heating Pin temperature: 300°C max., —
time: 3 seconds max. (per side)
Caution: Do not use two or more soldering methods in combination (except the pin partial heating
method).
Page 58
µ
PD75312(A), 75316(A)
4
APPENDIX A. COMPARISION OF FEATURES AMONG THIS SERIES PRODUCTS
Product
µ
PD75304(A)µPD75306(A)µPD75308(A)µPD75312(A)µPD75316(A)µPD75P308µPD75P316µPD75P316A
Item
ROM Configuration Mask ROM EPROM/One-time PROM*
1
ROM (bits) 000H-FFFH 0000H-177FH 0000H-1F7FH 0000H-2F7FH 0000H-3F7FH 0000H-1F7FH 0000H-3F7FH 0000H-3F7FH
4096 × 8 6016 × 8 8064 × 8 12160 × 8 16256 × 8 8064 × 8 16256 × 8 16256 × 8
RAM (bits) 512 × 4 (bank 0, 1 : 256 × 4) *2
3-byte
Instruc- Branch None Provided
tion Instruction
Set
Others Commonly provided
Program Counter 12 bits 13 bits 14 bits 13 bits 14 bits
Mask Option • Pull-up resistor for Ports 4, 5 Not offered
• Dividing resistor for LCD driving supply voltage
V
PP, PROM
Programming Pin None Offered
Connections
Directly Driving LED Not offered Offered
Operating
Supply 2.7 to 6.0 V 5 V ± 5% 5 V ± 5% 2.7 to 6.0 V
Voltage
Range
Electrical
Charac- Absolute
teristics Maximum Differ in high-level output current and low-level output current
Ratings
DC Charac- Differ in low-level output voltage
teristics
Quality Grade Special Standard
• 80-pin plastic QFP (14 × 20 mm) • 80-pin • 80-pin • 80-pin
plastic plastic plastic
QFP QFP QFP
(14 × 20 (14 × 20 (14 × 20
Package mm) mm) mm)
• 80-pin • 80-pin
ceramic ceramic
LCC w/ LCC w/
window window
*1: For the µPD75P316, only the one-time PROM is provided.
2: 1024 × 4 (Banks 0, 1, 2, 3, 15 : 256 × 4)
58
Page 59
µ
PD75312(A), 75316(A)
59
Hardware IE-75000-R *
1
In-circuit emulator for 75X series
IE-75001-R
IE-75000-R-EM *
2
Emulation board for IE-75000-R and IE-75001-R
EP-75308GF-R Emulation prove for µPD75312GF(A) and 75316GF(A), provided with 80-pin
conversion socket EV-9200G-80.
PG-1500 PROM programmer
PA-75P308GF PROM programmer adapter solely used for µPD75P316GF and 75P316AGF.
It is connected to PG-1500.
Software IE Control Program
PG-1500 Controller
RA75X Relocatable
Assembler
*1: Maintenance product
2: Not provided with IE-75001-R.
3: Ver.5.00/5.00A has a task swap function, but this function cannot be used with this function.
Remarks:
For development tools from other companies, refer to 75X Series Selection Guide (IF-151).
★
APPENDIX B. DEVELOPMENT TOOLS
The following development support tools are readily available to support development of systems using
µ
PD75312(A) and 75316(A):
EV-9200G-80
Host machine
PC-9800 series (MS-DOSTM Ver.3.30 to Ver.5.00A*3)
IBM PC/ATTM (PC DOSTM Ver.3.1)
Page 60
µ
PD75312(A), 75316(A)
60
APPENDIX C. RELATED DOCUMENTS
Page 61
µ
PD75312(A), 75316(A)
61
➀
STATIC ELECTRICITY (ALL MOS DEVICES)
Exercise care so that MOS devices are not adversely influenced by static electricity while being
handled.
The insulation of the gates of the MOS device may be destroyed by a strong static charge.
Therefore, when transporting or storing the MOS device, use a conductive tray, magazine case,
or conductive buffer materials, or the metal case NEC uses for packaging and shipment, and use
grounding when assembling the MOS device system. Do not leave the MOS device on a plastic
plate and do not touch the pins of the device.
Handle boards on which MOS devices are mounted similarly .
➁
PROCESSING OF UNUSED PINS (CMOS DEVICES ONLY)
Fix the input level of CMOS devices.
Unlike bipolar or NMOS devices, if a CMOS device is operated with nothing connected to its
input pin, intermediate level input may be generated due to noise, and an inrush current may flow
through the device, causing the device to malfunction. Therefore, fix the input level of the device
by using a pull-down or pull-up resistor. If there is a possibility that an unused pin serves as an
output pin (whose timing is not specified), each pin should be connected to V
DD or GND through
a resistor.
Refer to “Processing of Unused Pins” in the documents of each devices.
➂
STATUS BEFORE INITIALIZATION (ALL MOS DEVICES)
The initial status of MOS devices is undefined upon power application.
Since the characteristics of an MOS device are determined by the quantity of injection at the
molecular level, the initial status of the device is not controlled during the production process. The
output status of pins, I/O setting, and register contents upon power application are not guaranteed.
However, the items defined for reset operation and mode setting are subject to guarantee after
the respective operations have been executed.
When using a device with a reset function, be sure to reset the device after power application.
GENERAL NOTES ON CMOS DEVICES
Page 62
µ
PD75312(A), 75316(A)
62
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which
may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other
intellectual property rights of third parties b y or arising from use of a device described herein or any
other liability arising from use of such device. No license, either express, implied or otherwise, is granted
under any patents, copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for uses in aerospace equipment, submarine cables,
nuclear reactor control systems and life support systems. If customers intend to use NEC devices for
above applications or they intend to use "Standard" quality grade NEC devices for the applications not
intended by NEC, please contact our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special: Automotive and Transportation equipment, Traffic control systems, Antidisaster systems,
Anticrime system, etc.
MS-DOS is a trademark of Microsoft Corporation.
PC DOS and PC/AT are trademarks of IBM Corporation.
M4 92.6
[MEMO]
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