Page 1
DATA SHEET
MOS INTEGRATED CIRCUIT
µµµµ
PD7225
PROGRAMMABLE LCD CONTROLLER/DRIVER
The
PD7225 is a software-programmable LCD (Liquid Crystal Display) controller/driver. The µPD7225 can be
µ
serially interfaced with the CPU in a microcomputer and can directly drive 2, 3, or 4-time division LCD. The µPD7225
contains a segment decoder which can generate specific segment patterns. In addition, the µPD7225 can be used to
control on/off (blinking) operation of a display.
FEATURES
•Can directly drive LCD
•Programmable time-division multiplexing
•
Static drive
•
Divide-by-2, 3, or -4 time division multiplexing
•Number of digits displayed
•
7-segment
Divide-by-4 time division...............16 digits
Divide-by-3 time division...............10 2/3 digits
Divide-by-2 time division...............8 digits
Static.................................................4 digits
•
14-segment
Divide-by-4 time division...............8 digits
•Bias method
Static, 1/2, 1/3
•Segment decoder output
•
7-segment: Numeric characters 0 to 9, six symbols
•
14-segment: 36 alphanumeric characters, 13 symbols
•Blinking operation
•Multi-chip configuration possible
•8-bit serials interface
75X series and 78K series compatible
•CMOS
•Single power supply
ORDERING INFORMATION
Part Number Package
µ
PD7225G00 52-pin plastic QFP (14 × 14 mm)
µ
PD7225G01 52-pin plastic QFP (straight) ( 14 m m )
µ
PD7225GB-3B7 56-pin plastic QFP (10 × 10 mm)
µ
PD7225GC-AB6 52-pin plastic QFP (14 × 14 mm)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14308EJ6V0DS00 (6th edition)
(O.D. No. IC-1555)
Date Published June 1999 N CP (K)
Printed in Japan
The mark shows major revised points.
©
1986, 1999
Page 2
PIN CONFIGURATION: (Top View)
µµµµ
PD7225
PD7225G00 52-pin plastic QFP (14
µµµµ
PD7225G01 52-pin plastic QFP (straight) ( 14 mm)
µµµµ
PD7225GC-AB6 52-pin plastic QFP (14
µµµµ
CL1
S31
S30
51 50 49 48 47 46 45 44 43 42 41 40
CL2
/SYNC
V
LC1
VLC2
VLC3
VSS
VDD
/SCK
/CS
/BUSY
SI
1
2
3
4
5
6
7
8
9
10
11
52
S29
14 mm)
××××
14 mm)
××××
S28
S27
S26
S25
S24
S23
S22
S21
S20
39
38
37
36
35
34
33
32
31
30
29
S19
S18
S17
S16
S15
S14
V
DD
S13
S12
S11
S10
C, /D
/RESET
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
S0
S1
S2
S3
S4
NC
COM0
COM1
COM2
COM3
S5
S6
28
27
S7
SI : Serial Input CL1 : External Resistor 1 (External Clock)
/SCK : Serial Clock CL2 : External Resistor 2
C, /D : Command/Data RESET : Reset
/CS : Chip Select V
/BUSY : Busy V
SYNC : Sync V
LC1-VLC3
DD
SS
: Power Supply For LCD Drive
: Power Supply
: Ground
S0-S31 : Segment IC : Internally Connected
COM0-COM3 : Common
NC : Non-connection
/
Remark
indicates active low signal.
×××
S9
S8
2
Data Sheet S14308EJ6V0DS00
Page 3
µµµµ
PD7225
PD7225GB-3B7 56-pin plastic QFP (10
µµµµ
IC
S19
S18
S17
56 55 54 53 52 51 50 49 48 47 46 45 44 43
S20
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
1
2
3
4
5
6
7
8
9
10
11
10 mm)
××××
S16
S15
S14
VDDS13
S12
S11
S10
S9
S8
42
41
40
39
38
37
36
35
34
33
32
IC
S7
S6
S5
S4
S3
S2
S1
S0
COM3
COM2
Note
S31
CL1
IC
12
13
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
CL2
/SYNC
IC Pin must be connected to V
LC1VLC2VLC3
V
DD
or left unconnected.
31
30
29
SS
DD
V
V
/SCK
SI
/CS
/BUSY
C, /D
IC
/RESET
COM1
COM0
NC
Data Sheet S14308EJ6V0DS00
3
Page 4
BLOCK DIAGRAM
V
LC1
LCD DRIVER
COM
3S1S29S30S31
COM
2S0
µµµµ
PD7225
COM
COM
1
0
VLC2
VLC3
/SYNC
CL1
CL2
V
VSS
/RESET
/CS
C, /D
/BUSY
LCD
TIMING
CONTROL
OSC
DD
WRITE
CONTROL
SEGMENT
DECODER
DISPLAY DATA LATCH
DATA
MEMORY
COMMAND/DATA REGISTER
SERIAL INTERFACE
DATA
POINTER
BLINKING
DATA
MEMORY
COMMAND
DECODER
/SCKSI
4
Data Sheet S14308EJ6V0DS00
Page 5
1. PIN FUNCTIONS
µµµµ
PD7225
1.1 SI (Serial Input)
This pin is used for inputting serial data (commands/data). Data to be displayed as well as 19 deffernet
commands for controlling the operation of the µPD7225 can be input to this pin.
1.2 /SCK (Serial Clock)
This pin is used for inputting the shift clock for serial data (SI input). The content of the SI input is read into the
serial register at the rising edge of this clock one bit at a time. /SCK input is effective when /CS = 0 and /BUSY = 1.
If /BUSY = 0, this input is ignored. If /CS = 1, this signal is ignored regardless of the /BUSY status.
1.3 C, /D (Command/Data)
This input indicates whether the signal input from the SI pin is a command or data. A low level indicates data; a
high level indicates a command.
1.4 /BUSY
This is an active-low output pin that is used to control serial data input disable/enable. A low level disables serial
data input; a high level enables serial data input. This pin becomes high impedance when /CS = 1.
Tri-state output
……
……
…………
……
……
…………
Input
……
……
…………
Input
……
……
…………
Input
1.5 /CS (Chip Select)
When /CS is changed from high level to low level, the SCK counter in the µPD7225 is cleared and serial data
input is enabled. At the same time, the data pointer is initialized to address 0. When /CS is set to high level after
serial data is input, the contents of the data memory are transferred to the display latch and displayed on the LCD.
1.6 /SYNC (SYNChronous)
The /SYNC pin is used to make a wired-OR connection when the common pins are shared or when blinking
operation is synchronized in a multi-chip configuration.
When the µPD7225 is reset (/RESET = 0), the /SYNC pin outputs the clock frequency (fCL) divided by four (refer to
Figure 1-1
display timing of each µPD7225 is synchronized with the common drive signal timing shown in Figure 1-2.
), and synchronizes the system clock (fCL/4) of the µPD7225. When the reset is released (/RESET =1), the
f
CL
/SYNC
Input
……
……
…………
Input/Output
……
……
…………
Figure 1-1. /SYNC Pin Status During Reset (/RESET = 0)
Data Sheet S14308EJ6V0DS00
5
Page 6
Figure 1-2. /SYNC Pin Status after Reset (/RESET = 1)
µµµµ
PD7225
Static
COM0
/SYNC
Divie-by-2
time division
COM0
/SYNC
Divie-by-3
time division
COM0
/SYNC
Divie-by-4
time division
1 frame
1 frame
1 frame
1 frame
COM0
/SYNC
1.7 /RESET
……
……
…………
Input
This is an active low reset input pin.
1.8 S0-S31 (Segment)
……
……
…………
Output
These pins output segment drive signals.
1.9 COM0-COM3 (COMmon)
……
……
…………
Output
These pins output common drive signals.
1.10 CL1, CL2 (Clock)
A resistor is connected across these pins for internal clock generation. When inputting an external clock, use the
CL1 pin for input.
LC1
LC2
1.11 V
, V
, V
LC3
LCD driver power supply pin.
6
Data Sheet S14308EJ6V0DS00
Page 7
DD
1.12 V
Positive power supply pin. Either pin 7 or pin 33 can be used.
SS
1.13 V
GND pin.
µµµµ
PD7225
Data Sheet S14308EJ6V0DS00
7
Page 8
µµµµ
PD7225
2. INTERNAL SYSTEM CONFIGURATION
2.1 Serial Interface
The serial interface consists of an 8-bit serial register and a 3-bit SCK counter.
The serial register clocks in the serial data from the SI pin at the rising edge of /SCK. At the same time, the SCK
counter increments (+1) the serial clock. As a result, if an overflow occurs (when eight pulses are counted), input
from the SI pin is disabled (/BUSY = 0), and the contents of the serial register is output to the command/data register.
The /SCK should be set to high before serial data is input and after the data has been input (after eight clocks are
input to /SCK).
Serial data must be input to the SI pin beginning with MSB first.
LSB
µ
PD7225
SI pin
MSB
D7
D6 D5 D4 D3 D2 D1 D0
2.2 Command/Data Register
The command/data register latches the contents of the serial register in order to process the serial data clocked
into the serial register. After the serial data is latched, if the clocked in data is specified as command, the
command/data register transfers its contents to the command decoder. If specified as data the command/data
register transfers its contents to data memory or the segment decoder.
2.3 Command Decoder
When the contents of the command/data register are specified as a command (C, /D was high when data was
input), the command decoder, clocks in the contents of the command/data register and controls the µPD7225.
2.4 Segment Decoders
The µPD7225 has a 7-segment decoder for use with divide-by-3 and divide-by-4 time division, and a 14-segment
decoder for use divide-by-4 time division.
The 7-segment decoder can generate signals for numeric characters 0 to 9 and six different symbols. The 14segment decoder can generate signals for 36 alphanumeric characters and 13 different symbols. When the WITH
SEGMENT DECODER command is executed, if the contents of the command/data register are specified as data, the
contents will be input to the segment decoder, and converted to display codes, and then automatically written to the
data memory. Whether to select the 7-segment decoder or 14-segment decoder is determined by the most
significant bit (bit 7) of the data input to the segment decoder. It the most significant bit is 0, the 7-segment decoder
will be selected. If it is 1, the 14-segment decoder will be selected. If the 7-segment decoder is selected (however,
divide-by-3 and divide-by-4 time division), the lower 4 bits (bit 3 to bit 0) of the input data (C, /D = 0) will be decoded
and written to the data memory.
If the 14- segment decoder is selected (however, divide-by-4 time division), the lower 7 bits of the input data (C, /D
= 0) will be decoded and written to the data memory.
8
Data Sheet S14308EJ6V0DS00
Page 9
µµµµ
PD7225
703
0
Decode data
Specifies 7-segment
decoder
706
1
Decode data
Specifies 14-segment
decoder
When displaying the output of the segment decoder (display data) on the LCD, use an LCD configured as shown
in Figure 2-1 or Figure 2-2.
If another type of LCD is used, the displayed pattern will be different.
Figure 2-1. 7-Segment Type LCD
When configuring the LCD for divide-by-3 time division mode, connect as follows:
SEGn + 1
SEGn + 2
SEGn
COM0
COM1
COM2
a
b
f
g
e
c
DP
d
SEGn
SEGn +1
SEGn + 2
COM0
COM1
COM2
: b, c, DP
: a, d, g
: e, f
: a, b, f
: c, e, g
: d, DP
Data Sheet S14308EJ6V0DS00
9
Page 10
When configuring the LCD for divide-by-4 time division mode, connect as follows:
SEGn
µµµµ
PD7225
SEGn + 1
f
e
d
COM0
COM2
a
b
g
c
DP
SEGn
SEGn + 1
COM0
COM1
COM2
COM3
: a, b, c, DP
: d, e, f, g
: a, f
: b, g
: c, e
: d, DP
COM1
COM3
10
Data Sheet S14308EJ6V0DS00
Page 11
µµµµ
PD7225
Figure 2-2. 14-Segment LCD
The 14-segment type LCD can be used only in the divide-by-4 time division mode. For the 14-segment LCD type,
connect segments and commons as follows:
SEGn + 3 SEGn + 2
COM0
COM1
COM2
SEGn + 1 SEGn
e
a
bihgf
kj
cnml
d
DP
SEGn
SEGn + 1
SEGn + 2
SEGn + 3
COM0
COM1
COM2
COM3
: h, i, k, n
: d, e, f
: a, b, c, DP
: g, j, l, m
: a, g, h
: b, i, j, f
: c, e, k, l
: d, m, n, DP
COM3
The following shows the input data and display pattern, and the configuration of the display data which is
automatically written into the data memory. For the 7-segment type, the lower 4 bits (D3 to D0) are decoded. For the
14-segment type, the input data and display pattern correspond to 8-bit ASCII code. The first address to which the
display data is written is indicated as address N.
Data Sheet S14308EJ6V0DS00
11
Page 12
Figure 2-3. 7-Segment LCD
µµµµ
PD7225
Data
(HEX)
00
01
02
03
04
Display
pattern
Data memory
Divide-by-3
time division
5
3
0
0
7
2
7
0
2
1
time division
NN +1 NN +1N +2
3
3
1
3
3
Divide-by-4
7
D
6
0
3
E
7
A
6
3
Data
(HEX)
08
09
0A
0B
0C
Display
pattern
Data memory
Divide-by-3
time division
7
3
7
1
2
0
7
3
5
3
time division
NN +1 NN +1N +2
3
3
0
0
0
Divide-by-4
7
F
7
B
0
2
1
F
1
D
05
06
07
2
7
1
2
7
3
3
1
0
5
B
5
F
7
0
0D
0E
0F
0
2
0
0
6
2
6
0
0
0
A
4
E
0
0
12
Data Sheet S14308EJ6V0DS00
Page 13
Figure 2-4. 14-Segment LCD
Upper bit
µµµµ
PD7225
Data
(HEX)
0
1
2
3
4
5
6
Display
pattern
A
Data memory
N+2N+1 N
N+3
0
0
B
Display
pattern
0
0
Data memory
N+3N+2N+1 N
E
7
4
0
6
0
C
3
2
8
7
2
2
6
2
A
5
2
5
2
E
Display
pattern
2
0
4
4
4
4
4
C
Data memory
N+3N+2N+1 N
C
7
A
6
7
2
8
7
8
E
1
0
8
7
8
E
1
2
6
1
2
Display
pattern
0
4
5
0
1
4
4
D
Data memory
N+3N+2N+1 N
6
3
2
E
7
0
6
3
2
8
5
1
0
1
8
E
6
0
0
4
6
4
8
C
4
1
0
2
7
Lower bits
8
9
A
B
C
D
E
F
6
7
0
0
0
0
0
0
5
0
F
0
A
0
2
0
4
2
0
A
0
0
0
F
0
5
0
4
0
2
0
7
2
7
2
0
4
0
2
0
1
0
0
4
E
4
A
2
8
4
8
8
8
0
4
6
6
2
1
8
1
8
0
C
6
0
A
6
0
2
0
E
0
0
6
1
6
1
7
0
2
6
8
6
0
E
4
E
5
4
0
5
0
9
1
4
0
1
8
6
A
0
2
0
2
8
8
0
Data Sheet S14308EJ6V0DS00
13
Page 14
µµµµ
PD7225
2.5 Data Memory/Data Pointer
The data memory is a memory which stores display data (32 × 4 bits). Data input by serial transfer, command
immediate data, etc., is written to the data memory.
Specified by data pointer
Address
012345678910 293031
0
Bit
In the data memory, either data from the serial register (when the segment decoder is not used) or data from the
segment decoder (when the segment decoder is used) is written as display data.
When the segment decoder is not used, all bits or the lower 4 bits of the serial data (C, /D = 0) input to the serial
register are assigned and written to the specific bits in location 2 to location 4 in the data memory according to the
specified time division. When the segment decoder is used, the contents of the serial register (C, /D = 0) are
decoded by the segment decoder, and the corresponding display data are allocated to the location specified in data
memory by the time division specification (devide-by-3, -4 time division) and the MSB (Most Significant Bit) of the
serial data. (1) to (4) below describe these operations.
The contents of the data memory can be modified in 4-bit units or in bit units using a command.
1
2
3
(1) Static
The lower 4 bits of the contents of the serial register are written to bit 0 in each address (the upper 4 bits are
ignored).
bit3 bit0
D3 D2 D1 D0
n + 3 n + 2 n + 1 Address n
Only the content of bit 0 in each address are effective as display data.
After the data is written, the data pointer points to address n + 4.
(2) Divide-by-2 time division
The contents of the 4 even bits of the serial register are written to bit 0 in the four addresses, and the contents
of 4 odd bits of the serial register are written to bit 1.
bit3 bit0
D7 D6 D5 D4 D3 D2 D1 D0
n + 3 n + 2 n + 1 Address n
The contents of bits 0 and 1 of each address are effective as display data.
After the data is written, the data pointer points to address n + 4.
14
Data Sheet S14308EJ6V0DS00
Page 15
µµµµ
PD7225
(3) Divide-by-3 time division
The contents of the 8 bits of the serial register of the segment decoder output (8 bits) are written to bits 0, 1, and
2 of each address. In this case, 0 will be automatically written to bit 2 of address n + 2. For segment decoder
output, 0 will also be automatically written to bit 2 (D2) of address n.
bit3 bit0
0D7D6 D5D4D3
n + 2 n + 1 Address n
D2
D1 D0
0
The contents of bits 0, 1, and 2 of each address are effective as display data.
After the data is written, the data pointer points to address n + 3.
The segment decoder output written to the data memory corresponds to segments (a to g, DP) shown in Figure
2-1 as follows:
bit3 bit0
ef dga DPcb
n + 2 n + 1 Address n
(4) Divide-by-4 time division
The contents of the 8 bits of the serial register or the segment decoder output (8 bits) are written to bits 0, 1, 2,
and 3 of each address. For segment decoder output, 0 is automatically written to bit 3 (D3) of address n.
bit3 bit0
D7 D6 D5 D4
n + 1 Address n
D3
D2 D1 D0
0
The contents of all bits of each address are effective as display data.
After the data is written, the data pointer points to address n + 2.
When 7 segments are used, the segment decoder output written to the data memory corresponds to segments
(a to g, DP) shown in Figure 2-1 as follows:
bit3 bit0
degf DPcba
n + 1 Address n
When 14 segments are used, the segment decoder output is written to bits 0, 1, 2, and 3 of each address. In
this case, 0s are automatically written to bit 3 of address n + 2, and bit 0 of address n+ 1.
D15 D14 D13 D12
n + 3 n + 2 n + 1 Address n
D11
D10 D9 D8 D7 D6 D5
0
Data Sheet S14308EJ6V0DS00
D4
0
bit3 bit0
D3 D2 D1 D0
15
Page 16
µµµµ
PD7225
All bits of each address are effective. After the data is written, the data pointer points to address n + 4.
The segment decoder output written to the data memory corresponds to segments (a to n, DP) shown in Figure
2-2 as follows:
ml jg DPcba def0 nki h
n + 3 n + 2 n + 1 Address n
All contents of the 32 × 4-bit data memory are transferred to the 32 × 4-bit display data latch when the /CS is set
to high. In this case, if the DISPLAY ON command has been set, the contents of the display data latch are
converted to the segment drive signal in 32-bit units in synchronization with COM0-COM3 signals, and output
from the segment pins.
The figure below shows the relationship of the data memory, segment pins, and common signal selection
timing.
Figure 2-5. Data Memory, Segment Pins, and Common Signal Selection Timing
COM 0
COM 1
COM 2
COM 3
S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10
012345678
9 10 28293031
Address
S28S29 S30S31
0
1
Bit
2
3
The data pointer (5 bits) specifies the address (0-31) of the data memory to which the display data will be
written (at the same time, the data pointer specifies the blinking data memory address (0-31)). The LOAD
DATA POINTER command is used to set the address to the data pointer (the data pointer can be initialized by
setting the /CS to low). When the data pointer is counted up to 31, it then becomes 0 at the next count, and
thus it repeats the operation shown below.
031
It should be noted that, if display data is written sequentially from address 0 in the divide-by-3 time division
mode, addresses 30 and 31 will not be written. However, if the data is written in the divide-by-3 time division
mode again, data will be written from addresses 30, 31, followed by 0 so that the display data previously written
to address 0 will be modified.
16
Data Sheet S14308EJ6V0DS00
Page 17
µµµµ
PD7225
2.6 Blinking Data Memory
The blinking data memory stores blinking data used to control display on/off operation (blinking). Blinking
operation can be performed in segment units. Each bit in blinking data memory corresponds to a bit in the data
memory; if a bit in the blinking data memory is set to 1, the corresponding segment will blink.
The blinking data memory is addressed by the data pointer at the same time the data memory is addressed. Data
is written by using the WRITE BLINKING DATA MEMORY command, and bit manipulation can be performed by
using the AND BLINKING DATA MEMORY, or OR BLINKING DATA MEMORY command. The BLINKING ON
command is used to initiate blinking operation or select the blinking interval (refer to
Setting
)
3.2 Blinking Frequency
2.7 Display Data Latch
The display data latch stores the data of the 32 × 4-bit segment driver. Each bit of the display data latch
corresponds to a bit in the data memory. All contents of the data memory are transferred to the display data latch at
the rising edge of /CS, and the contents displayed on the LCD are modified. If blinking is set, the contents of data
memory are modified by the contents of blinking data memory and the resulting values are transferred to the display
data latch.
The display data written to the display data latch is successively selected by the control function performed by the
LCD timing control, and converted to segment drive signal before output.
2.8 LCD Driver
The LCD driver consists of the segment driver and the common driver, and generates the segment drive signal
and common drive signal.
The segment driver outputs a segment signal so that the relationship with the common drive signal is select level if
the drive data stored in the display data latch is 1. If the drive data stored in the display data latch is 0, the output of
the segment driver will be non-select level.
The common drive signal sequentially drives the LCD common poles according to the time divison specificaion.
2.9 LCD Timing Control
The LCD timing control generates the LCD drive timing according to the number of time divisions, the frequency
division ratio, and bias method, and supplies it to the LCD driver. In addition, the LCD timing control outputs a /SYNC
signal from the /SYNC pin in order to synchronize the display timing of each µPD7225 when configured in a multichip configuration.
In a multi-chip configuration, the common signal can be used in common or blinking operation can be
synchronized by making a wired-OR connection with the /SYNC pin of each µPD7225.
Data Sheet S14308EJ6V0DS00
17
Page 18
µµµµ
3. FRAME FREQUENCY AND BLINKING FREQUENCY SETTING
3.1 Frame Frequency Setting
The frame frequency is set according to M1, M0 (number of time-divisions setting), and F1, F0 (frequency division
ratio) as indicated in the figure below.
Figure 3-1. Frame Frequency Setting
PD7225
F1,F0
00
01
10
11
CL
= Clock oscillation frequency
Remark
f
M1, M0
Static
Divide- by-2 time
division
01111000
CL
f
7
2
CL
f
8
2
CL
f
9
2
CL
f
11
2
CL
f
27 × 2
CL
f
28 × 2
CL
f
29 × 2
CL
f
211 × 2
Divide- by-3 time
division
CL
f
27 × 3
CL
f
28 × 3
CL
f
29 × 3
CL
f
211 × 3
3.2 Blinking Frequency Setting
The blinking frequency can be set in two settings by K0 in the BLINKING ON command.
Figure 3-2. Blinking Frequency Setting
Divide- by-4 time
division
CL
f
27 × 4
CL
f
28 × 4
CL
f
29 × 4
CL
f
211 × 4
18
K0 Blinking frequency
0
1
CL
= Clock oscillation frequency
Remark
f
Data Sheet S14308EJ6V0DS00
CL
f
17
2
CL
f
16
2
Page 19
µµµµ
PD7225
4. LCD DRIVE POWER SUPPLY PIN VOLTAGE SETTING
The bias method for setting the LCD drive power supply pin allows a different voltage to be supplied to each pin.
Figure 4-1. Voltage Setting
Static V
1/2 bias VDD − V
1/3 bias VDD − V
LCD
: LCD voltage
Remark
V
LC1
V
DD
1
LCD
2
1
LCD
3
LC2
V
VDD − V
1
VDD − V
2
1
VDD − V
3
LCD
LCD
LCD
LC3
V
VDD − V
VDD − V
VDD − V
LCD
LCD
LCD
The following shows a circuit example which supplies voltages between VDD and VSS as the LCD drive reference
voltage.
(1) Static
LCD
V
VDD − V
LCD
: LCD drive voltage
LCD
2
R
×
PD7225
µ
V
DD
V
DD
V
LC1
V
LC2
V
LC3
V
SS
R
1
R
2
R1 =
•
V
•
R2 is used for contrast adjustment.
GND
(2) Divide-by-2, -3 time division (1/2 bias)
V
DD
V
PD7225
µ
DD
V
LC1
V
LC2
V
LC3
V
SS
R
1
R
1
R
2
GND
R1 =
Data Sheet S14308EJ6V0DS00
LCD
V
2(VDD − V
LCD
2
R
×
)
19
Page 20
(3) Divide-by-3, -4 time division (1/3 bias)
V
DD
V
PD7225
µ
DD
V
LC1
V
LC2
V
LC3
V
SS
R
1
R
1
R
1
R
2
GND
R1 =
LCD
V
3(VDD − V
LCD
µµµµ
PD7225
2
R
×
)
20
Data Sheet S14308EJ6V0DS00
Page 21
µµµµ
PD7225
5. CLOCK CIRCUIT
The clock oscillator can be configured by connecting a resistor (R) across the CL1 and CL2 clock pins. When
using the external clock, CL1 can be used to input the external clock (CL2: Open).
Figure 5-1. External Circuit for Clock Oscillation Pins
f
CL
To LCD timing
control
Remark
µ
PD7225
CL1
OSC
CL2
CL
= Clock oscillation frequency (when using the external clock, this frequency is same as that of the
f
R
CL
f
To LCD timing
control
µ
PD7225
OSC
CL1
CL2
External clock
Open
external clock frequency.)
When configuring a multi-chip system using the /SYNC pin, a clock with the same frequency and same phase
must be supplied to the CL1 pin of each µPD7225.
Data Sheet S14308EJ6V0DS00
21
Page 22
µµµµ
6. RESET FUNCTION
When a low level of 12 clock cycles or more is input to the /RESET pin, the µPD7225 will be reset to the following
conditions:
• This condition is the same as when M2 − M0 = 0, F1, F0 = 0 are executed by the MODE SET command.
• Display data transfer from the data memory to the display data latch
the UNSYNCHRONIZED TRANSFER command is executed.
• Command/data register output
This condition is the same as when the WITHOUT SEGMENT DECODER
−−−
command is executed.
• LCD display
This condition is the same as when the DISPLAY OFF or the BRINKING OFF command is
−−−
executed.
Function when the µPD7225 is reset
This condition is the same as when
−−−
PD7225
• S0-S31 and COM0-COM3 pins output V
• Serial data input
Disabled (/BUSY = 0) (However, /CS = 0)
−−−
DD
When used in a multi-chip system, the reset state must be released (rising edge of /RESET) within 5 µs.
Figure 6-1. Reset Signal in Multi-Chip System
DD
/RESET
12 clock cycles 5 s max.
0.7V
0.3V
DD
µ
22
Data Sheet S14308EJ6V0DS00
Page 23
µµµµ
PD7225
7. SERIAL DATA INPUT
Serial data is input to the SI pin with MSB first in synchronization with the serial clock in 8-bits units. When /CS is
set to low, the µPD7225 sets the /BUSY to low (this initializes the SCK counter and the data pointer to 0) in order to
perform internal processing. Therefore, after the µPD7225 completes internal processing, the first bit (MSB) should
be input in synchronization with the /SCK after the /BUSY signal is set to high. The serial data is transferred to the
serial register in bit units at the rising edge of /SCK. Inputting eight serial clocks completes the transfer of all 8 bits of
data to the serial register. At the rising edge of the eighth serial clock, the /BUSY is set to low, and the status of the
C, /D pin is clocked in to specify whether the data is a command or data. Afterwards, the contents of the serial
register are clocked into the command/data register.
When successively inputting 2 or more bytes of serial data, /CS must be set to low until all bytes of data are input.
The /BUSY is set to low each time a byte of data is input. The /BUSY becomes high when the serial data is clocked
in from the serial register to the command/data register, so that the next serial data can be input.
When input of all serial data is complete, the data memory contents can be displayed by setting /CS to high. /CS
must not be set to high while display data is being transferred (before eight clocks has elapsed.) If it becomes
necessary to interrupt serial data transfer when transferring two or more bytes of data due to an interrupt for the CPU
interrupt, execute the PAUSE TRANSFER command after checking that the byte has been transferred, then set /CS
to high. In this case, even if /CS is set to high, the contents of the data memory will not be transferred to the display
data latch.
To resume serial data transfer, set /CS to low in the same way as when initiating a normal transfer. However, in
this case, the contents of the data pointer are not cleared so that data write operation starts from the next data
memory address when serial data transfer is resumed (C, /D = 0).
Note
Serial data
(SI pin)
/SCK
/BUSY
C, /D
In a multi-chip system in which the /BUSY pins of chips are made a wired-OR connection, avoid setting the
/CS pins of two or more chips simultaneously.
Figure 7-1. Inputting Byte
D7 D6 D5 D0D1D2
/CS
High
impedance
High
impedance
Data Sheet S14308EJ6V0DS00
23
Page 24
Figure 7-2. Inputting 5 Bytes Successively
Serial data Byte 2Byte 1 Byte 3 Byte 4 Byte 5
/CS
/BUSY
µµµµ
PD7225
24
Data Sheet S14308EJ6V0DS00
Page 25
µµµµ
PD7225
8. COMMAND
8.1 MODE SET
010M2M1M0F1F0
This command sets the number of time divisions for the LCD display static drive or the time-division drive, bias
method, and frame frequency.
(1) M1 and M0 specify the number of time divisions for static drive or time-division drive.
M1 M0
0 0------------------- Divide-by-4 time division drive
1 0------------------- Divide-by-3 time division drive
1 1------------------- Divide-by-2 time division drive
0 1------------------- Static drive
(2) M2 specifies the bias method.
M2
0-------------------------- 1/3 bias method
1-------------------------- 1/2 bias method
0/1------------------------- Static
(3) F1 and F0 specify the frequency division ratio which determines the frame frequency (refer to Figure 3-1).
F1 F0 Frequency division ratio
0 0------------------- 1/2
0 1------------------- 1/2
1 0------------------- 1/2
1 1------------------- 1/2
7
8
9
11
8.2 SYNCHRONIZED TRANSFER
00110001
This command controls display data modification.
Normally, modification of display data is performed at the rising edge of the /CS signal (transferring display data
from the data memory to the display data latch). However, after this command is executed, display data is modified
at the first alternate current drive cycle (Frame frequency x Number of time divisions) after the /CS signal is set to
high.
Data Sheet S14308EJ6V0DS00
25
Page 26
µµµµ
PD7225
8.3 UNSYNCHRONIZED TRANSFER
00110000
This command controls display data modification.
After this command is executed, display data is modified at the rising edge of the /CS pin.
8.4 PAUSE TRANSFER
00111000
This command disables display data modification.
After this command is executed, display data can not be modified at the first rising edge of the /CS pin; instead,
modification is put off until the second rising edge of the /CS pin. In addition, the data pointer is not cleared at the
first rising edge of the /CS pin (refer to
2.5 Data Memory/Data Pointer
This command is used when it becomes necessary to set the /CS pin to high due to an interrupt for the CPU in the
middle of serial data input operation.
).
8.5 BLINKING ON
0001101K0
This command sets the blinking operation status. The blinking frequency is set by the least significant bit of the
command (bit K0).
K0 Blinking frequenc y (Hz)
17
0f
1f
CL
: Clock oscillation frequency
Remark
f
CL
/2
16
CL
/2
8.6 BLINKING OFF
00011000
This command stops blinking operation.
8.7 DISPLAY ON
00010001
After this command is executed, LCD display operation starts according to the display data contained in the
display data latch.
26
Data Sheet S14308EJ6V0DS00
Page 27
µµµµ
PD7225
8.8 DISPLAY OFF
00010000
When this command is executed, the relationship of all common drive signals and segment drive signals enters
the non-select state. As a result, the display is turned off. Transferring display data from the data memory to the
display data latch is not affected by this command execution.
8.9 WITH SEGMENT DECODER
00010101
After this command is executed, input data is sent to the segment decoder, and the decoded code is written to the
data memory.
8.10 WITHOUT SEGMENT DECODER
00010100
After this command is executed, input data is written to the data memory without going through the segment
decoder.
8.11 LOAD DATA POINTER
1 1 1 D4D3D2D1D0
This command sets immediate data D4-D0 to the data pointer.
8.12 WRITE DATA MEMORY
1 1 0 1 D3 D2 D1 D0
This command stores immediate data D3-D0 to the data memory addressed by the data pointer, and increments
(+1) the contents of the data pointer.
8.13 OR DATA MEMORY
1 0 1 1 D3 D2 D1 D0
This command ORs the contents of the data memory addressed by the data pointer and immediate data D3-D0,
and stores the result to the data memory, then increments (+1) the contents of the data pointer.
Data Sheet S14308EJ6V0DS00
27
Page 28
µµµµ
8.14 AND DATA MEMORY
1 0 0 1 D3 D2 D1 D0
This command ANDs the contents of the data memory addressed by the data pointer and immediate data D3-D0,
and stores the result to the data memory, then increments (+1) the contents of the data pointer.
8.15 CLEAR DATA MEMORY
00100000
This command clears the contents of the data memory and the data pointer.
8.16 WRITE BLINKING DATA MEMORY
1 1 0 0 D3 D2 D1 D0
PD7225
This command stores immediate data D3-D0 to the blinking data memory addressed by the data pointer, and
increments (+1) the contents of the data pointer.
8.17 OR BLINKING DATA MEMORY
1 0 1 0 D3 D2 D1 D0
This command ORs the contents of the blinking data memory addressed by the data pointer and immediate data
D3-D0, and stores the result to the blinking data memory, then increments (+1) the contents of the data pointer.
8.18 AND BLINKING DATA MEMORY
1 0 0 0 D3 D2 D1 D0
This command ANDs the contents of the blinking data memory addressed by the data pointer and immediate data
D3-D0, and stores the result to the blinking data memory, then increments (+1) the contents of the data pointer.
8.19 CLEAR BLINKING DATA MEMORY
00000000
This command clears the contents of the blinking data memory and the data pointer.
28
Data Sheet S14308EJ6V0DS00
Page 29
µµµµ
PD7225
9. DISPLAY OUTPUT
The following describes the serial data organization, display data organization in the data memory, segment drive
signal, and common drive signal when the display is active in the static and divide-by-2, -3, -4 time division modes.
9.1 Static
When displaying just the digit “6” in the static mode:
(1) Serial data organization: 0D, 07
(2) Display data organization in the data memory
Address
n + 7 n + 6 n + 5 n + 4 n +3 n + 2 n + 1 n
BitContents of bit 001111101
(3) Power supply (static)
LC0
LC1
V
= V
LC2
V
= V
(4) Relationship between common and segment
= V
LC3
= VDD − V
DD
LCD
SEGn + 5
SEGn + 4
COM0
SEGn
SEGn + 1
SEGn + 6
SEGn + 2
SEGn +7
SEGn + 3
Data Sheet S14308EJ6V0DS00
29
Page 30
(5) Segment and common drive signals
SEGn, SEGn + 2 − SEGn + 6
SEGn + 1, SEGn + 7
COM0
µµµµ
PD7225
V
LC0
V
LC3
V
LC0
V
LC3
V
LC0
V
LC3
COM0 − SEGn
COM0 − SEGn + 1
V
0
−V
0
LC0
LC0
30
Data Sheet S14308EJ6V0DS00
Page 31
9.2 Divide-by-2 Time Division
When displaying just the digit “6” in the divide-by-2 time division mode:
(1) Serial data organization: F5
(2) Display data organization in the data memory
n +3 n + 2 n + 1 n
Contents of bit 0 1 1 1 1
Bit
Contents of bit 1 1 1 0 0
(3) Power supply (1/2 bias)
LC0
= V
LC1
= V
LC3
= VDD − V
DD
LC2
= VDD − 1/2 V
LCD
LCD
V
V
V
(4) Relationship between common and segment
Address
µµµµ
PD7225
SEGn + 3
SEGn + 2
SEGn
SEGn + 1
COM0
COM1
Data Sheet S14308EJ6V0DS00
31
Page 32
(5) Segment and common drive signals
µµµµ
PD7225
SEGn
SEGn + 1
SEGn + 2
SEGn + 3
t0 t1 t2 t3 t0 t1 t2 t3 t0 t1
V
LC0
V
LC3
LC0
V
V
LC3
V
LC0
V
LC3
V
LC0
V
LC3
V
LC0
COM0
COM1
COM0 − SEGn + 3
COM1 − SEGn
V
V
V
V
V
V
V
0
−V
−V
V
0
−V
LC1
LC3
LC0
LC1
LC3
LC0
LC1
LC1
LC0
LC1
LC1
32
Data Sheet S14308EJ6V0DS00
Page 33
9.3 Divide-by-3 Time Division
When displaying the digit “6.” in the divide-by-3 time division mode:
(1) Serial data organization
• Without segment decoder: FE
• With segment decoder : 06
(However, the floating point is set to “1” by command.)
(2) Display data organization in the data memory
n + 2 n + 1 n
Contents of bit 0 1 1 0
Bit Contents of bit 1 1 1 1
Contents of bit 2 0 1 1
(3) Power supply (1/3 bias)
LC0
V
V
V
V
(4) Relationship between common and segment
DD
= V
LC1
= VDD − 1/3 V
LC2
= VDD − 2/3 V
LC3
= VDD − V
LCD
LCD
LCD
Address
µµµµ
PD7225
SEGn + 2
SEGn + 1
SEGn
COM0
COM1
COM2
Data Sheet S14308EJ6V0DS00
33
Page 34
(5) Segment and common drive signals
µµµµ
PD7225
SEGn
SEGn + 1
SEGn + 2
COM0
COM1
COM2
t0 t1 t2 t3 t4 t5 t0 t1 t2 t3
V
LC0
V
LC1
V
LC2
V
LC3
V
LC0
V
LC1
V
LC2
V
LC3
LC0
V
V
LC1
V
LC2
V
LC3
V
LC0
V
LC1
V
LC2
V
LC3
V
LC0
V
LC1
V
LC2
V
LC3
V
LC0
V
LC1
V
LC2
V
LC0
34
COM1 − SEGn + 2
COM2 − SEGn + 2
Data Sheet S14308EJ6V0DS00
V
V
0
−V
−V
V
0
−V
LC0
LC2
LC2
LC0
LC2
LC2
Page 35
9.4 Divide-by-4 Time Division
When displaying the digit “6.” in the divide-by-4 time division mode:
(1) Serial data organization
• Without segment decoder: FD
• With segment decoder : 06
(However, the floating point is set to “1” by command.)
Contents of bit 0 1 1
Contents of bit 1 1 0
Bit
Contents of bit 2 1 1
Contents of bit 3 1 1
(2) Power supply (1/3 bias)
LC0
V
V
V
V
(3) Relationship between common and segment
DD
= V
LC1
= VDD − 1/3 V
LC2
= VDD −2/3 V
LC3
= VDD − V
LCD
LCD
LCD
Address
n + 1 n
µµµµ
PD7225
COM0
COM2
SEGn
SEGn + 1
COM1
COM3
Data Sheet S14308EJ6V0DS00
35
Page 36
(4) Segment and common drive signals
µµµµ
PD7225
SEGn
SEGn + 1
COM0
COM3
COM1
COM2
t7 t0 t1 t2
t3 t4 t5 t6
t7 t0 t1 t2
V
LC0
V
LC1
V
LC2
V
LC3
V
LC0
LC1
V
V
LC2
V
LC3
V
LC0
V
LC1
V
LC2
V
LC3
V
LC0
V
LC1
V
LC2
V
LC3
V
LC0
V
LC1
V
LC2
V
LC3
V
LC0
V
LC1
V
LC2
V
LC3
36
COM0 − SEGn + 1
COM1 − SEGn
Data Sheet S14308EJ6V0DS00
V
V
0
−V
−V
V
0
−V
LC0
LC2
LC2
LC0
LC2
LC2
Page 37
10. ELECTRICAL CHARACTERISTICS
µµµµ
PD7225
Absolute Maximum Rating (TA = 25
C)
°°°°
Item Symbol Condition Rating Units
Power supply voltage V
Input voltage V
Output voltage V
Operating ambient temperature T
Storage temperature T
DD
I
O
A
stg
0.3 to +7.0 V
−
DD
DD
10 to +70
−
65 to +150
+0.3 V
+0.3 V
0.3 to V
−
0.3 to V
−
−
C
°
C
°
Caution If the absolute maximum rating of even one of the above parameters is exceeded
even momentarily, the quality of the product may be degraded. Absolute maximum
ratings, therefore, specify the values exceeding which the product may be physically
damaged. Be sure to use the product within the range of the absolute maximum
ratings.
Capacitance (TA = 25
Item Symbol Condition MIN. TYP. MAX. Units
Input capacitance C
Output capacitance C
Output capacitance C
Input/output capacit ance C
Clock capacitance C
C, VDD = 0 V)
°°°°
IN
OUT1
OUT2
IO
C
Except /BUSY 20 pF
/BUSY 15 pF
/SYNC 15 pF
CL1 30 pF
other than those
used for
measurement
are 0 V.
f = 1 MHz pins
10 pF
Data Sheet S14308EJ6V0DS00
37
Page 38
µµµµ
PD7225
DC Characteristics (TA =
10 to +70
−−−−
Item Symbol Condition MIN. TYP. MAX. Unit
High level input voltage V
Low level input voltage V
High level output voltage V
Low level output voltage V
Output short-circuit current I
High level input leakage current I
Low level input leakage current I
High level output leakage current I
Low level output leakage current I
Common output impedance R
Segment output impedance R
Power supply voltage I
Notes 1.
Applies to Static, 1/2 bias, 1/3 bias
Abnormal current will flow if the external clock supply is removed.
2.
C, VDD = 5 V
°°°°
IH
IL
OH
/SYNC, /BUSY, IOH = −10 µAV
OL1
/BUSY, IOL = 100 µA0.5V
OL2
V
LOH
LOL
/SYNC, IOL = 900 µA1.0V
OS
/SYNC, VO = 1 V
LIH
VI = V
LIL
VI = 0 V
VO = V
VO = 0 V
COM0 to COM3
COM
S0 to S31
SEG
CL1 external clock, fC = 200 kHz
DD
±±±±
DD
DD
10%)
Note 1
Note 1
, VDD ≥ V
, VDD ≥ V
LCD
LCD
Note 2
DD
0.7 V
0 0.3 V
DD
− 0.5 V
−
V
300
DD
DD
2
2
−
2
2
−
57k
714k
100 250
V
V
A
µ
A
µ
A
µ
A
µ
A
µ
Ω
Ω
A
µ
DC Characteristics (TA = 0 to +70
Item Symbol Condition MIN. TYP. MAX. Units
High level input voltage V
Low level input voltage V
High level output voltage V
Low level output voltage V
Output short-circuit current I
High level input leakage current I
Low level input leakage current I
High level output leakage current I
Low level output leakage current I
Common output impedance R
Segment output impedance R
Power supply voltage I
C, VDD = 2.7 to 5.5 V)
°°°°
IH1
Except /SCK 0.7 V
IH2
V
V
V
LOH
LOL
/SCK 0.8 V
IL1
Except /SCK 0 0.3 V
IL2
/SCK 0 0.2 V
OH
/SYNC, /BUSY, IOH = −7 µAV
OL1
/BUSY, IOL = 100 µA0.5V
OL2
/SYNC, IOL = 400 µA0.5V
OS
/SYNC, VO = 0.5 V
LIH
LIL
VI = V
VI = 0 V
VO = V
DD
DD
VO = 0 V
Note 1
, VDD ≥ V
Note 2
Note 1
COM0 to COM3
COM
S0 to S31
SEG
DD
CL external clock, VDD = 3 V ± 10%,
C
= 140 kHz
f
, VDD ≥ V
LCD
LCD
DD
DD
DD
− 0.75 V
−
V
V
200
DD
DD
DD
DD
2
2
−
2
2
−
6k
12 k
30 100
V
V
V
V
A
µ
A
µ
A
µ
A
µ
A
µ
Ω
Ω
A
µ
Notes 1.
38
Applies to Static and 1/3 bias
Abnormal current will flow if the external clock supply is removed.
2.
Data Sheet S14308EJ6V0DS00
Page 39
µµµµ
PD7225
AC Characteristics (TA =
10 to +70
−−−−
C, VDD = 5 V
°°°°
Item Symbol Condition MIN. TYP. MAX. Units
OSC
WHC
WLC
WHK
WLK
t
C
CYK
HBK
SIK
HKI
DKB
Operating frequency f
Oscillation frequency f
High level clock pulse width t
Low level clock pulse width t
/SCK frequency t
High level /SCK puls e wi dth t
Low level /SCK pulse wi dth t
/BUSY ↑→ /SCK ↓ hold time t
SI set time (against /SCK ↑)t
SI hold time (against / S CK ↑)t
8th pulse of /SCK ↑→ /BUSY
↓
delay time
/CS ↓→ /BUSY ↓ delay time t
/BUSY low level time t
C, /D set time (against 8th pulse
DCSB
WLB
SDK
t
of SCK ↑)
C, /D hold time (against 8t h pul se
HKD
t
of SCK ↑)
/CS hold time (against 8t h pul s e of
HKCS
t
SCK ↑)
High level /CS pulse width t
Low level /CS pulse widt h t
/SYNC load capacitanc e C
WHCS
WLCS
LSY
10%)
±±±±
50 200 kHz
R = 180 kΩ ± 5% 85 130 175 kHz
CL1, external clock 2 16
CL1, external clock 2 16
s
µ
s
µ
900 ns
400 ns
400 ns
0ns
100 ns
200 ns
CL = 50 pF 3
CL = 50 pF 1.5
≥ 48/f
Note 1
C
CL = 50 pF
4 44 (57)
Note 2
WHCS
t
9
1
1
Note 3
Note 3
CYC
t
= 5 µs50pF
1/f
s
µ
s
µ
C
s
µ
s
µ
s
µ
s
µ
s
µ
Notes 1.
UNSYNCHRONIZED TRANSFER MODE
For SYNCHRONIZED TRANSFER MODE,
WHCS
≥ (48/fC + AC driver frequency)
t
BLINKING ON
2.
8/fc
3.
Data Sheet S14308EJ6V0DS00
39
Page 40
µµµµ
PD7225
AC Characteristics (TA = 0 to +70
C, VDD = 2.7 V to 5.5 V)
°°°°
Item Symbol Condition MIN. TYP. MAX. Unit
WHC
WLC
WHK
t
C
OSC
CYK
WLK
HBK
SIK
HKI
DKB
R = 180 kΩ ± 5%, VDD = 3 V ± 10 % 50 100 140 kHz
CL1, external clock 3 16
CL1, external clock 3 16
CL = 50 pF 5
Operating frequency f
Oscillation frequency f
High level clock pulse width t
Low level clock pulse width t
/SCK frequency t
High level /SCK puls e wi dth t
Low level /SCK pulse wi dth t
/BUSY ↑→ /SCK hold time t
SI set time (against /SCK ↑)t
SI hold time (against / S CK ↑)t
8th pulse of /SCK ↑→ /BUSY
↓
delay time
/CS ↓→ /BUSY ↓ delay time t
/BUSY low level time t
C, /D set time (against 8th pulse
DCSB
WLB
SDK
t
CL = 50 pF 5
t
of SCK ↑)
C, /D hold time (against 8t h pul se
HKD
t
of SCK ↑)
/CS hold time (against 8t h pul s e of
HKCS
t
SCK ↑)
High level /CS pulse width t
Low level /CS pulse widt h t
/SYNC load capacitanc e C
WHCS
WLCS
LSY
t
50 140 kHz
s
µ
s
µ
4
1.8
1.8
s
µ
s
µ
s
µ
0ns
1
1
≥ 48/f
Note 1
C
CL = 50 pF
4 44 (57)
Note 2
WHCS
18
1
1
Note 3
Note 3
CYC
= 7.1 µs50pF
1/f
s
µ
s
µ
s
µ
s
µ
C
s
µ
s
µ
s
µ
s
µ
s
µ
Notes 1.
UNSYNCHRONIZED TRANSFER MOD
For SYNCHRONIZED TRANSFER MODE,
WHCS
t
≥ (48/fC + AC driver frequency)
2.
BLINKING ON
8/fc
3.
AC Timing Measurement Voltage
40
0.7V
0.3V
DD
DD
Measurement
points
Data Sheet S14308EJ6V0DS00
0.7V
0.3V
DD
DD
Page 41
Timing Wave-Form
CL1
t
WLC
t
CYC (1/fe)
t
WHC
µµµµ
PD7225
/CS
/BUSY
/SCK
t
WHCS
t
DCSB
t
WLCS
t
HKCS
Note 1
0.5 V 0.5 V
t
HBK
t
WLK
CYK
t
t
DKBtWLR
Note 2
Note 3
t
WHK
t
SIK
t
HKI
SI
t
SDK
t
HKD
C, /D
Notes 1.
DD
V
− 0.5 V when VDD = 5 V ± 10 %, VDD − 0.75 V when VDD = 2.7 to 5.5 V
2.
0.8 V when VDD = 2.7 V to 5.5 V
3.
0.2 V when VDD = 2.7 V to 5.5 V
Data Sheet S14308EJ6V0DS00
41
Page 42
µµµµ
PD7225
Typical Characteristic Curve (Ta = 25
External resistor and oscillation frequency
V
DD
= 5 V
200
100
Oscillation frequency (kHz)
50
External resistor R (k ohms)
Power supply voltage and operating current
200
V
DD
= 3 V
C)
°°°°
CL2 CL1
R
500100
Power supply voltage and oscillation frequency
CL2 CL1
140
R
120
100
Oscillation frequency (kHz)
80
Power supply voltage VDD (V)
R = 180 kΩ
45
63
CL2 CL1
External clock
100
µ
50
Operating current ( A)
20
Power supply voltage VDD (V)
fC = 200 kHz
f
C
= 140 kHz
4
563
42
Data Sheet S14308EJ6V0DS00
Page 43
11. PACKAGE DRAWINGS
PD7225G00
µµµµ
52 PIN PLASTIC QFP (14x14)
A
B
µµµµ
PD7225
39
40
27
26
CD
52
1
14
13
F
G
M
H
I
P
J
K
S
S
N
L
NOTES
1. Controlling dimension millimeter.
2. Each lead centerline is located within 0.20 mm of
its true position (T.P.) at maximum material condition.
M
detail of lead end
S
Q
ITEM MILLIMETERS INCHES
A 21.0±0.4 0.827±0.016
B 14.0±0.2 0.551
C 14.0±0.2 0.551
D 21.0±0.4 0.827±0.016
F 1.0 0.039
G 1.0 0.039
H 0.42±0.08 0.017
I 0.20 0.008
J 1.0 (T.P.) 0.039
K 3.5±0.2 0.138
L 2.2±0.2 0.087
M 0.17 0.007
N 0.15 0.006
P 2.6 0.102
Q 0.1±0.1 0.004±0.004
S 3.0 MAX. 0.119 MAX.
+0.08
−0.07
+0.2
−0.1
+0.009
−0.008
+0.009
−0.008
+0.003
−0.004
+0.008
−0.009
+0.008
−0.009
+0.003
−0.004
+0.009
−0.004
P52G-100-00-3
Data Sheet S14308EJ6V0DS00
43
Page 44
PD7225G01
µµµµ
52PIN PLASTIC QFP (STRAIGHT) ( 14)
µµµµ
PD7225
A
B
39
40
52
F
1
G
H
M
I
UT
P
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
27
26
C
D
14
13
J
K
M
ITEM MILLIMETERS INCHES
A 22.0±0.4 0.866±0.016
B 14.0±0.2 0.551
C 14.0±0.2 0.551
D 22.0±0.4 0.866±0.016
F 1.0 0.039
G 1.0 0.039
H 0.40±0.10 0.016
I 0.20 0.008
J 1.0 (T.P.) 0.039 (T.P.)
K 4.0±0.2 0.157
M 0.15 0.006
P 2.6 0.102
T 1.0 0.039
U 1.45 0.057
+0.10
–0.05
+0.2
–0.1
+0.009
–0.008
+0.009
–0.008
+0.004
–0.005
+0.009
–0.008
+0.004
–0.003
+0.009
–0.004
P52G-100-01-2
44
Data Sheet S14308EJ6V0DS00
Page 45
PD7225GB-3B7
µµµµ
56 PIN PLASTIC QFP (10 10)
µµµµ
PD7225
A
B
39
40
27
26
CD
52
1
14
13
F
J
G
H
P
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
M
I
K
N
L
detail of lead end
S
Q
R
M
ITEM MILLIMETERS INCHES
A 13.2±0.4 0.520±0.016
B 10.0±0.2 0.394±0.008
C 10.0±0.2 0.394±0.008
D 13.2±0.4 0.520±0.016
F 0.75 0.030
G 0.75 0.030
H 0.30±0.10 0.012
I 0.13 0.005
J 0.65 (T.P.) 0.026 (T.P.)
K 1.6±0.2 0.063±0.008
L 0.8±0.2 0.031
M 0.15 0.006
N 0.10 0.004
P 2.7 0.106
Q 0.1±0.1 0.004±0.004
R5°±5° 5°±5°
S 3.0 MAX. 0.119 MAX.
+0.10
–0.05
+0.004
–0.005
+0.009
–0.008
+0.004
–0.003
S56GB-65-3B7-3
Data Sheet S14308EJ6V0DS00
45
Page 46
PD7225GC-AB6
µµµµ
52 PIN PLASTIC QFP (14×14)
µµµµ
PD7225
A
B
39
40
27
26
CD
52
1
14
13
F
G
M
H
I
P
J
K
M
N
NOTE
Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.
L
detail of lead end
S
Q
ITEM MILLIMETERS INCHES
A 17.6±0.4 0.693±0.016
B 14.0±0.2 0.551
C 14.0±0.2 0.551
D 17.6±0.4 0.693±0.016
F 1.0 0.039
G 1.0 0.039
H 0.40±0.10 0.016
I 0.20 0.008
J 1.0 (T.P.) 0.039 (T.P.)
K 1.8±0.2 0.071
L 0.8±0.2 0.031
M 0.15 0.006
N 0.10 0.004
P 2.6 0.102
Q 0.1±0.1 0.004±0.004
R5°±5° 5°±5°
S 3.0 MAX. 0.119 MAX.
R
+0.10
–0.05
P52GC-100-AB6-4
+0.009
–0.008
+0.009
–0.008
+0.004
–0.005
+0.008
–0.009
+0.009
–0.008
+0.004
–0.003
46
Data Sheet S14308EJ6V0DS00
Page 47
µµµµ
PD7225
12. RECOMMENDED SOLDERING CONDITIONS
When mounting the µPD7225 by soldering, soldering should be performed under the following recommended
conditions.
Should other than recommended conditions be used, consult with our sales personnel.
Surface Mount Type
PD7225G00 : 52-pin plastic QFP (14 × 14 mm)
µ
PD7225G01 : 52-pin plastic QFP (straight) ( 14 mm)
µ
PD7225GC-AB6 : 52-pin plastic QFP (14 × 14 mm)
µ
Symbol of
Soldering Method Soldering Condition
Recommended
Soldering Condition
Partial Heating Pin temperature: 300 °C MAX., Time: 3 seconds MAX. (Per side of device)
PD7225GB-3B7 : 56-pin plastic QFP (10 × 10 mm)
µ
Soldering Method Soldering Condition
Infrared reflow Package peak t em perature: 235 °C, Time: 30 seconds MAX. (210 °C MIN.),
Number of times: 3 MAX .
VPS Package peak tem perature: 215 °C, Time: 40 seconds MAX. (200 °C MIN),
Number of times: 3 MAX .
Wave soldering Solder bath temperat ure: 260 °C MAX., Time: 10 seconds MAX., Number of
times: 1, Preheating t emperature: 120 °C MAX. (Package s urface)
Soldering Condition
−
Symbol of
Recommended
IR35-00-3
VP-15-00-3
WS-60-00-1
Caution Do not use two or more soldering methods in combination (except the partial heating method).
Reference Documents
NEC Semiconductor Device Reliability / Quality Control System (C10983E)
Quality Grades to NEC’s Semiconductor Devices (C11531E)
Semiconductor Device Mounting Technology Manual (C10535E)
Data Sheet S14308EJ6V0DS00
47
Page 48
[MEMO]
µµµµ
PD7225
48
Data Sheet S14308EJ6V0DS00
Page 49
[MEMO]
µµµµ
PD7225
Data Sheet S14308EJ6V0DS00
49
Page 50
[MEMO]
µµµµ
PD7225
50
Data Sheet S14308EJ6V0DS00
Page 51
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
DD
pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
or GND with a resistor, if it is considered to have a possibility of
µµµµ
PD7225
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14308EJ6V0DS00
51
Page 52
µµµµ
PD7225
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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