NameFunction
Bus interfaceAn interface between the µPD72107 and external memory or external host processor
Internal controllerManages LAP-B protocol including control of the DMAC block, transmitter block, and receiver block
DMACControls the transfer of data on the external memory to the internal controller or transmitter block,
(Direct Memoryand controls the writing of data in the internal controller or receiver block to the external memory
Access Controller)
TxFIFOA 16-byte buffer for when transmit data is sent from the DMAC to the transmitter block
RxFIFOA 32-byte buffer for when receive data is sent from the receiver block to the DMAC
TransmitterConverts the contents of TxFIFO into an HDLC frame and transmits it as serial data
ReceiverReceives HDLC frame and writes internal data to RxFIFO
Internal busAn 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block,
512816Note that there is more than one ground pin.
7455
CLK132614I–System clock input
(Clock)Input clock of 1 MHz to 8.2 MHz.
RESET82210ILInitializes the internal
(Reset)more than 7 CLK clock cycles is required (clock
PU122513I–Pull up to high level when using in normal operation.
(Pull Up)
CS487152ILWhen bus master
(Chip Select)Set to disable.
MRD527556OLWhen bus master
(Memory Read)3-stateReads the data of the external memory at low level.
MWR537657OLWhen bus master
(Memory Write)3-stateWrites the data to the external memory at low level.
IORD497253ILThis pin is used when the external host processor
(I/O Read)reads the contents of the internal registers of the
IOWR507354ILThis pin is used when the external host processor
(I/O Write)writes the data to the internal registers of the
ASTB60564OHThis pin is used to latch the address output from
(Address Strobe)the
I/OPin NameFunction
µ
PD72107. Active width of
input is required).
After reset, this pin becomes a bus slave.
When bus slave
Read/write operation from the host processor at low
level is enabled.
When bus slave
High impedance
When bus slave
High impedance
µ
PD72107.
µ
PD72107.
µ
PD72107 externally.
6
Page 7
µ
PD72107
SDIPQFPQFJActive
Pin No.Pin No.Pin No.Level
NC91, 7,1––Use this pin open.
(No Connection)11, 15,5
20, 21,35
29, 40,
41, 50,
51, 55,
61, 69,
80
IC1122––Do not connect anything to this pin.
(Internally7199
Connected)102311
UBE547758I/OL/HWhen bus master (output)
(Upper Byte3-stateThe signal output from this pin changes according
Enable) to the input value of the B/W pin.
I/OPin NameFunction
• Byte transfer mode (B/W = 0)
UBE is always high impedance.
• Word transfer mode (B/W = 1)
Indicates that valid data is either in pins D0 to D7
or pins A16D8 to A23D15 (or both).
UBEA0D0 to D7 A16D8 to A23D15
00
01 ×
10×
11 ××
When bus slave (input)
UBE pin becomes input, and indicates that valid
data is either in pins D0 to D7 or pins A16D8 to
A23D15.
UBEA0D0 to D7 A16D8 to A23D15
00×
01 ×
10×
11×
7
Page 8
µ
PD72107
SDIPQFPQFJActive
Pin No.Pin No.Pin No.Level
B/W112412IL/HSpecifies the data bus that accesses the external
(Byte/Word)memory when bus master.
READY59463IHAn input signal that is used to extend the MRD and
(Ready)MWR signal widths output by the µPD72107 to
HLDRQ57261OHA hold request signal to the external host processor.
(Hold Request)When a DMA operation is performed in the µPD72107,
HLDAK58362IHA hold acknowledge signal from the external host
(Hold Acknowledge)
AEN61665OHWhen bus master, this signal enables the latched
(Address Enable)higher addresses and outputs them to system ad-
A2 to A1517 to 30 32 to 47 19 to 32O–When bus master
(except3-stateOutput bit 2 to bit 15 of memory access addresses.
40, 41)When bus slave
I/OPin NameFunction
B/W = 0Byte units (8 bits)
B/W = 1Word units (16 bits)
After power-on, fix the status of the B/W pin.
In the case of word access, the lower data bus is the
contents data of even addresses.
adapt to low-speed memory. When the READY
signal is low level, the MRD and MWR signals
maintain active low. Do not change the READY
signal at any time other than the specified setup/
hold time.
this signal is activated to switch from bus slave to
bus master.
processor. When the µPD72107 detects that this
signal is active, the bus slave switches to bus
master, and a DMA operation is started.
dress bus. This signal is also used for disabling
other system bus drivers.
3-stateWhen bus master (output)
Indicate the lower 2-bit addresses of memory access.
When bus slave (input)
Input addresses when the external host processor
I/O accesses the µPD72107.
Become high impedance.
8
Page 9
µ
PD72107
SDIPQFPQFJActive
Pin No.Pin No.Pin No.Level
A16D8 to A23D15 31 to 38 48 to 58 33 to 41I/O–Bidirectional 3-state address/data buses. Multiplex
(except 50, (except 35)
51, 55)and the higher 8 bits to 15 bits of data.
D0 to D739 to 46 59 to 67 42 to 49I/O–Bidirectional 3-state data buses.
(except 61)
CRQ62866IHA signal requesting command execution to the
(Command
Request)
INT557859OHAn interrupt signal from the µPD72107 to the
(Interrupt)external host processor.
CLRINT567960IHA signal inactivating the INT signal being output by
(Clear Interrupt)the µPD72107. The µPD72107 generates the CLRINT
CTS6188I–A general-purpose input pin.
(Clear To Send)The µPD72107 reports the “CTS pin change detection
I/OPin NameFunction
3-statepins of the higher 16 bits to 23 bits of addresses
3-stateWhen bus master
When writing to external memory, these pins become
input if reading at output.
When bus slave
Usually, these pins become high impedance. When
the external host processor reads I/O of the µPD72107,
the internal register data is output.
µ
PD72107 by the external host processor. The
µ
PD72107 starts fetching commands from on the
external memory at the rising edge of this signal.
signal in the LSI internal circuit at the rising edge of
this signal, and forcibly makes the INT output signal
low.
status” to the external host processor when the
input level of this pin is changed in the generalpurpose input/output pin support (setting RSSL to
1 by the “system initialization command”). The
change of input level is recognized only when the
same level is sampled twice in succession after
sampling in 8-ms cycles and detecting the change.
Moreover, when the external host processor issues
a “general-purpose input/output pin read command”
to the µPD72107, the µPD72107 reports the pin
information of this pin to the external host processor
by a “general-purpose input/output pin read response
status”.
The change can be detected even in the clock input
stop status of TxC and RxC.
TxD5177O–A serial transmit data output pin.
(Transmit Data)
TxC4166I/O–When CLK is set to 01 or 10 by “operation mode
(Transmit Clock)3-statesetting LCW” (output)
I/OPin NameFunction
The output value of this pin can be changed by
issuing an “RTS pin write command” from the external
host processor to the µPD72107. Moreover, when
the external host processor issues a “general-purpose
input/output pin read command” to the µPD72107,
the µPD72107 reports the pin information of this pin
to the external host processor by a “general-purpose
input/output pin read response status”.
status” to the external host processor when the
input level of this pin is changed in the generalpurpose input/output pin support (setting RSSL to
1 by the “system initialization command”). The
change of input level is recognized only when the
same level is sampled twice in succession after
sampling in 8-ms cycles and detecting the change.
Moreover, when the external host processor issues
a “general-purpose input/output pin read command”
to the µPD72107, the µPD72107 reports the pin
information of this pin to the external host processor
by a “general-purpose input/output pin read response
status”.
The change can be detected even in the clock input
stop status of TxC and RxC.
Outputs a clock that divides by 16 the input signal
of the RxC pin or CLK pin made by the µPD72107.
Caution TxC becomes input because CLK = 00
is the default after reset. It becomes
output after setting CLK to 01 or 10 by
“operation mode setting LCW”.
When CLK is set to 00 by “operation mode setting
LCW” (input)
Inputs transmit clock externally.
Remark LCW: abbreviation for Link Command Word
10
Page 11
µ
PD72107
SDIPQFPQFJActive
Pin No.Pin No.Pin No.Level
RxD3144I–A serial receive data input pin.
(Receive Data)
RxC2133I–When CLK is set to 01 or 10 by “operation mode
(Receive Clock)setting LCW”
I/OPin NameFunction
Sixteen times the clock input of the transmit/receive
clock for the on-chip DPLL of the
When CLK is set to 00 by “operation mode setting
LCW”
One time the clock input of the receive clock
µ
PD72107
Remark LCW: abbreviation for Link Command Word
1.2 Pin Status after Reset of µPD72107
The status of the output pins and input/output pins after reset in the µPD72107 is as shown in Table 1-1.
Remarks 1. The status after reset is released is the same as the status during reset.
2. Input low level to the RESET pin for more than 7 clocks of the system clock.
11
Page 12
µ
PD72107
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = +25°C)
ParameterSymbolConditionsRatingsUnit
Power supply voltageVDD–0.5 to +7.0V
Input voltageVI–0.5 to VDD + 0.3V
Output voltageVO–0.5 to VDD + 0.3V
Operating ambient temperatureTA–40 to +85°C
Storage temperatureTstg–40 to +125°C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
Caution If the load capacitance exceeds 50 pF due to the configuration of the circuit, keep the load
capacitance of this device to within 50 pF by inserting a buffer or by some other means.
Remark DUT: device under test
AC test input/output waveform (except clock)
2.4 V
2.2 V
Test points
0.8 V
0.4 V
2.2 V
0.8 V
System clock
CLK
tKFtKR
tKKL
1.5 V
tCYK
3.0 V
tKKH
13
Page 14
µ
PD72107
When bus master (2)
ParameterSymbolConditionsMIN.MAX.Unit
HLDRQ ↑ delay time (vs. CLK ↓)tDHQH100ns
HLDRQ ↓ delay time (vs. CLK ↑)tDHQL100ns
HLDAK setup time (vs. CLK ↑)tSHA35ns
HLDAK hold time (vs. CLK ↑)tHHA20ns
AEN ↑ delay time (vs. CLK ↓)tDAEH100ns
AEN ↓ delay time (vs. CLK ↑)tDAEL100ns
ASTB ↑ delay time (vs. CLK ↑)tDSTH70ns
ASTB high-level widthtSTSTHtKKH–15ns
ASTB ↓ delay time (vs. CLK ↓)tDSTL100ns
ADR/UBE/MRD/MWR delay timetDA100ns
(vs. CLK ↑)
ADR/UBE/MRD/MWR float timetFA70ns
(vs. CLK ↑)
ADR setup time (vs. ASTB ↓)tSASTtKKH–35ns
ADR hold time (vs. ASTB ↓)tHSTAtKKL–20ns
MRD ↓ delay time (vs. ADR float) tDAR0ns
MRD ↓ delay time (vs. CLK ↑)tDRL70ns
MRD low-level widthtRRL22t CYK–50ns
MRD ↑ delay time (vs. CLK ↑)tDRH70ns
Data setup time (vs. MRD ↑)tSDR100ns
Data hold time (vs. MRD ↑)tHRD0ns
MWR ↓ delay time (vs. CLK ↑)tDWL70ns
MWR low-level widthtWWL22tCYK–50ns
MWR ↑ delay time (vs. CLK ↑)tDWH70ns
READY setup time (vs. CLK ↑)tSRY35ns
READY hold time (vs. CLK ↑)tHRY20ns
14
Page 15
tDHQH
tSHA
tHHA
tDAEH
tDSTH
tDSTL
tDA
tSTSTH
tSASTtHSTA
tDWL
tFA
tSRYtSRY
tDA
tDAR
tDRL
tRRL2
tDRH
tSDR
tHRD
tFA
tHRYtDWHtHRY
tWWL2
tDAEL
tDHQL
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-ZHi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Address
Input data
Output data
Address
CLK
HLDRQ
HLDAK
AEN
ASTB
A16D8-A23D15
A0, A1/A2-A15
UBE
MWR
READY
A16D8-A23D15
MRD
Address
tHHA
When bus master
15
µ
PD72107
Page 16
µ
PD72107
When bus slave (1)
ParameterSymbolConditionsMIN.MAX.Unit
IOWR low-level widthtWWL100ns
CS low-level hold timetHWCS0ns
(vs. IOWR ↑)
ADR/UBE/CS low-level setup time tSAW0ns
(vs. IOWR ↓)
ADR/UBE hold time (vs. IOWR ↑)tHWA0ns
Data setup time (vs. IOWR ↑)tSDW100ns
Data hold time (vs. IOWR ↑)tHWD0ns
IORD low-level widthtRRL150ns
ADR/CS low-level setup timetSAR35ns
(vs. IORD ↓)
ADR/CS low-level hold timetHRA0ns
(vs. IORD ↑)
Data delay time (vs. IORD ↓)tDRD120ns
Data float time (vs. IORD ↑)tFRD10100ns
RESET low-level widthtRSTL7tCYKns
VDD setup time (vs. RESET ↑)tSVDD1000ns
RESET ↑ –1st • IOWR/IORDtSYWR2tCYKns
IOWR/IORD recovery timetRVWR200ns
(vs. HLDAK ↑)
IOWR/IORD high-level hold timet HWR100ns
(vs. AEN ↓)
HLDAK
tSWR
IOWR/IORD
AEN
tHWR
IOWR/IORD
When bus slave (3)
ParameterSymbolConditionsMIN.MAX.Unit
CLRINT high-level widthtCLCLH100ns
INT ↑ delay time (vs. CLK ↑)tDIH100ns
INT ↓ delay time (vs. CLRINT ↑)tDIL100ns
CRQ high-level widthtCRCRH100ns
CLK
CLRINT
tCLCLH
18
INT
CRQ
tDIH
tDIL
tCRCRH
Page 19
µ
PD72107
Serial block (1)
ParameterSymbolConditionsMIN.MAX.Unit
TxC/RxC cycle timetCYSWhen on-chip DPLL is not used250DCns
TxC/RxC low-level timetSSL110ns
TxC/RxC high-level timetSSH110ns
TxC/RxC rise timetSR20ns
TxC/RxC fall timetSF12ns
TxD delay time (vs. TxC ↓)tDTXD100ns
RxD setup time (vs. RxC ↑)tSRXD50ns
RxD hold time (vs. RxC ↑)tHRXD70ns
Serial clock (when on-chip DPLL is not used)
TxC/RxC
TxC (input)
TxD
RxC
RxD
tSFtSR
0.8 V
tSRXDtHRXD
tSSL
tCYS
tDTXDtDTXD
t
2.2 V
SSH
19
Page 20
µ
PD72107
Serial block (2)
ParameterSymbolConditionsMIN.MAX.Unit
RxC cycle timetCYRWhen on-chip DPLL is used (source clock = RxC)30.3ns
When on-chip DPLL is used (source clock = CLK)1251000
RxC low-level timetSSRLWhen on-chip DPLL is used (source clock = RxC)10ns
When on-chip DPLL is used (source clock = CLK)50
RxC high-level timetSSRHWhen on-chip DPLL is used (source clock = RxC)10ns
When on-chip DPLL is used (source clock = CLK)50
RxC rise timetSRRWhen on-chip DPLL is used (source clock = RxC)5ns
When on-chip DPLL is used (source clock = CLK)10
RxC fall timetSRFWhen on-chip DPLL is used (source clock = RxC)5ns
When on-chip DPLL is used (source clock = CLK)10
Transmit/receive data cycletCYDWhen on-chip DPLL is used (source clock = RxC)500ns
When on-chip DPLL is used (source clock = CLK)200016000
TxC low-level timetTCTCLWhen on-chip DPLL is used
TxC high-level timetTCTCH
TxD delay time (vs. TxC ↓)tDTCTD50ns
TxD hold time (vs. TxC ↑)tHTCTD
0.5tCYD–25
0.5tCYD–25
0.5tCYD–25
ns
ns
ns
Serial clock (when on-chip DPLL is used)
tCYR
tSSRL
tSRF
RxC
TxC
tTCTCL
tDTCTD
TxD
tSSRH
tSRR
tTCTCH
tHTCTD
tCYD
20
Page 21
µ
PD72107
Serial block (3)
ParameterSymbolConditionsMIN.MAX.Unit
RTS ↑ delay time (vs. CLK ↑)tDRTH100ns
RTS ↓ delay time (vs. CLK ↑)tDRTL100ns
CD setup time (vs. CLK ↑)tSCD35ns
CD hold time (vs. CLK ↑)tHCD20ns
CTS setup time (vs. CLK ↑)tSCT35ns
CTS hold time (vs. CLK ↑)tHCT20ns
CLK
RTS
tDRTL
tHCD
tDRTH
CD
CTS
tSCD
tHCT
tSCT
21
Page 22
3. APPLICATION CIRCUIT EXAMPLE
(1) Connection with SIFC (µPD98201)
µµ
PD72107PD98201
TxDBINA
µ
PD72107
RxD
TxC
RxC
BOUT1
SIFCLAP-B
BCLK
22
Page 23
µ
PD72107 System Configuration Example (Local Memory Type)
Local memory 64 Kbytes
Host processorPD72107
RDWRCSUBEA0-A15D0-D15
µ
4. SYSTEM CONFIGURATION EXAMPLES
MEMR
MEMW
IOR
IOW
AB0-AB7
AB8-AB15
AB16-AB19
BHE
DB0-DB15
INT
Local
bus request
WAIT
A B
µ
PD71086
OE
A B
µ
PD71086
OE
A B
µ
PD71086
OE
A B
µ
PD71086
OE
Access
contention
resolution
circuit
Decoder
A0-A15
D0-D15
MRD
MWR
IORD
IOWR
CS
A0-A15
D0-D7
A16D8-A23D15
UBE
AEN
INT
HLDRQ
HLDAK
µ
PD72107
23
Page 24
24
µ
PD72107 System Configuration Example (Main Memory Sharing Type)
Host processorPD72107
INTP
µ
PD70116
AD8-AD15
INT
INTAK
RD
WR
HLDRQ
HLDAK
ASTB
A16-A19
AD0-AD7
UBE
BUF R/W
BUFEN
INT
INTAK
PD71059
µ
RD WR D0-D7
STB OE
µ
PD71082×3
CS
A0
A16-A19
Decoder
A0-A15
D8-D15
OE STB
µ
PD71082
µ
INT
IORD
IOWR
CS
MRD
MWR
HLDRQ
HLDAK
AEN
ASTB
D0-D7
A16D8-A23D15
A0-A15
UBE
µ
PD71086×2
TOE
D0-D7
RD WRCS UBE
Memory
D0-D7 D8-D15
µ
PD72107
Page 25
I
J
G
H
F
D
N
M
CB
M
R
6433
321
K
L
NOTES
1. Controlling dimension millimeter.
P64C-70-750A,C-3
ITEM MILLIMETERSINCHES
B
C
D
F
G
H
J
K
1.778 (T.P.)
3.2±0.3
0.51 MIN.
1.78 MAX.
L
M
0.17
0.25
19.05 (T.P.)
5.08 MAX.
17.0±0.2
N
0 to 15°
0.50±0.10
0.9 MIN.
R
0.070 MAX.
0.020
0.035 MIN.
0.126±0.012
0.020 MIN.
0.200 MAX.
0.750 (T.P.)
0.669
0.010
0.007
0 to 15°
+0.004
–0.003
0.070 (T.P.)
+0.10
–0.05
+0.004
–0.005
64 PIN PLASTIC SHRINK DIP (750 mil)
2. Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
3. Item "K" to center of leads when formed parallel.
A58.02.283
+0.028
–0.008
+0.68
–0.20
I4.050.159
+0.011
–0.008
+0.26
–0.20
A
+0.009
–0.008
5. PACKAGE DRAWINGS
µ
PD72107
25
Page 26
80 PIN PLASTIC QFP (14x14)
µ
PD72107
A
B
61
60
41
40
CD
80
1
20
21
F
G
M
H
I
P
J
K
N
L
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
detail of lead end
S
Q
R
M
ITEM MILLIMETERSINCHES
A17.2±0.40.677±0.016
B14.0±0.20.551
C14.0±0.20.551
D17.2±0.40.677±0.016
F0.8250.032
G0.8250.032
H0.30±0.100.012
I0.130.005
J0.65 (T.P.)0.026 (T.P.)
K1.6±0.20.063±0.008
L0.8±0.20.031
M0.150.006
N0.100.004
P
Q0.1±0.10.004±0.004
R5°±5°5°±5°
S3.0 MAX.0.119 MAX.
+0.10
–0.05
2.7±0.10.106
+0.009
–0.008
+0.009
–0.008
+0.004
–0.005
+0.009
–0.008
+0.004
–0.003
+0.005
–0.004
S80GC-65-3B9-5
26
Page 27
68 PIN PLASTIC QFJ (950 x 950 mil)
A
B
68
1
CD
µ
PD72107
G
H
J
F
S
K
M
M
N
P
I
NOTES
1. Controlling dimension millimeter.
2. Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
E
Q
U
T
S
ITEM MILLIMETERSINCHES
A25.2±0.20.992±0.008
B24.20±0.10.953
C24.20±0.10.953
D25.2±0.20.992±0.008
E1.94±0.150.076
F0.60.024
G4.4±0.20.173
H2.8±0.20.110
I0.9 MIN.0.035 MIN.
J3.4±0.10.134
K1.27 (T.P.)0.050 (T.P.)
M0.42±0.080.017
N0.120.005
P23.12±0.20.910
Q0.150.006
TR 0.8R 0.031
U0.220.009
+0.08
−0.07
+0.004
−0.005
+0.004
−0.005
+0.007
−0.006
+0.009
−0.008
+0.009
−0.008
+0.004
−0.005
+0.003
−0.004
+0.009
−0.008
+0.003
−0.004
P68L-50A1-3
27
Page 28
µ
PD72107
6. RECOMMENDED SOLDERING CONDITIONS
The µPD72107 should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales representative.
Surface mounting type
µ
PD72107GC-3B9: 80-pin plastic QFP (14 × 14 mm)
•
Soldering MethodSoldering ConditionsRecommended Condition Symbol
Infrared reflowPackage peak temperature: 235°C, Time: 30 sec. Max.IR35-00-3
(at 210°C or higher), Count: three times or less
VPSPackage peak temperature: 215 °C, Time: 40 sec. Max.VP15-00-3
(at 200°C or higher), Count: three times or less
Wave solderingSolder bath temperature: 260°C, Time: 10 sec. Max.,WS60-00-1
Count: one time, Preheating temperature: 120°C Max.
(package surface temperature)
Soldering Method Soldering Conditions
Wave soldering (pin only)Solder bath temperature: 260°C Max., Time: 10 sec. Max.
Partial heatingPin temperature: 300°C Max., Duration: 3 sec. Max. (per a pin)
Caution Wave soldering must be applied only to pins. Be sure to avoid jet soldering the package body.
28
Page 29
[MEMO]
µ
PD72107
29
Page 30
[MEMO]
µ
PD72107
30
Page 31
µ
NOTES FOR CMOS DEVICES
1PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
PD72107
2HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
31
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PD72107
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
2
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