Datasheet UPD70F3040YGM-UEU, UPD70F3040GM-UEU Datasheet (NEC)

PRELIMINARY PRODUCT INFORMATIONPRELIMINARY DATA SHEET

DATA SHEET

MOS INTEGRATED CIRCUIT

µµµµ

PD70F3040, 70F3040Y

V850/SV1

TM

32-/16-BIT SINGLE-CHIP MICROCONTROLLERS

DESCRIPTION

The µPD70F3040 and µPD70F3040Y are products that substitute flash memory for the mask ROM of the

PD703039, 703040, 703041 and µPD703039Y, 703040Y, 703041Y, respectively. Since the µPD70F3040 and

µ

70F3040Y can be read and written while mounted on the board, these products are ideal for evaluation during
system development, multiple-version small-scale production or quick product release.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

V850/SV1 User’s Manual Hardware: U14462E
V850 Family

FEATURES

Pin compatible with

•

For mass production, these can be replaced by a mask ROM version.

•

PD70F3040 → µPD703039, 703040, 703041

µ

PD70F3040Y → µPD703039Y, 703040Y, 703041Y

µ

PD703039, 703040, 703041, 703039Y, 703040Y, and 703041Y

µ

TM

User’s Manual Architecture: U10243E

ORDERING INFORMATION

Part Number Package

PD70F3040GM-UEU

µ

PD70F3040YGM-UEU

µ

DIFFERENCES BETWEEN V850/SV1 PRODUCTS

Internal ROM Internal RAM I2CV

µ

PD70F3040 None

µ

PD70F3040Y

µ

PD703039 None

µ

PD703039Y

µ

PD703040 None

µ

PD703040Y

µ

PD703041 None

µ

PD703041Y

The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

256 KB (flash memory) 16 KB

256 KB (mask ROM)

192 KB (mask ROM) 8 KB

176-pin plastic LQFP (fine-pitch) (24 × 24 mm)
176-pin plastic LQFP (fine-pitch) (24 × 24 mm)

8 KB

16 KB

Provided

Provided

Provided

Provided

PP

Pin

Provided

None

Document No. U14622EJ1V0DS00 (1st edition)
Date Published March 2000 N CP(K)
Printed in Japan

©

2000

PIN CONFIGURATION

176-pin plastic LQFP (fine-pitch) (24 × 24 mm)

PD70F3040GM-UEU

µ

PD70F3040YGM-UEU

µ

Note 2

µµµµ

PD70F3040, 70F3040Y

P12/SCK0/SCL0

P13/SI1/RXD0

P14/SO1/TXD0

P15/SCK1/ASCK0

P20/SI2/SDA1

P22/SCK2/SCL1

P23/SI3/RXD1

P24/SO3/TXD1

P25/SCK3/ASCK1

P126/TI10/TO10
P127/TI11/TO11

Note 2

Note 2

P21/SO2

Note 2

P26/TI2/TO2
P27/TI3/TO3

V

V
P30/TI000
P31/TI001
P32/TI010
P33/TI011

P34/TO0

P35/TO1
P36/TI4/TO4
P37/TI5/TO5

P120/SI4

P121/SO4

P122/SCK4

P123/CLO
P124/TI6/TO6
P125/TI7/TO7

P180
P181
P182
P183
P184
P185
P186
P187

V

V
P190
P191
P192
P193

P11/SO0

P10/SI0/SDA0

P113

P112

P111

P110

WAIT

CLKOUT

P65/A21

P64/A20

P63/A19

P62/A18

P61/A17

P60/A16

P57/AD15

P56/AD14

P55/AD13

P54/AD12

P53/AD11

P52/AD10

P51/AD9

P50/AD8

BVSSBVDDP47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P96/HLDRQ

P95/HLDAK

P94/ASTB

P93/DSTB/RD

P92/R/W/WRH

P91/UBEN

P90/LBEN/WRL

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

1
2
3
4
5
6
7
8
9
10
11
12
13

DD

14

SS

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

DD

40

SS

41
42
43
44

45464748495051525354555657585960616263646566676869707172737475767778798081828384858687

138

REF

VSSVDDAVDDAVSSAV

137

136

135

134

133

132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100

99
98
97
96
95
94
93
92
91
90
89

88

P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
P147
P146
P145/RTPTRG1
P144/TI9/INTTI9
P143/INTCP93
P142/INTCP92
P141/INTCP91
P140/INTCP90
P137/TO81
P136/TO80
P135/TCLR8/INTTCLR8
P134/TI8/INTTI8
P133/INTCP83
P132/INTCP82
P131/INTCP81
P130/INTCP80
V

SS

V

DD

P07/INTP6
P06/INTP5/RTPTRG0
P05/INTP4/ADTRG
P04/INTP3
P03/INTP2
P02/INTP1
P01/INTP0
P00/NMI
P157/RTP17
P156/RTP16

2

Notes 1.

P194

P195

P196

P197

P170/KR0

P171/KR1

P172/KR2

P173/KR3

P174/KR4

P175/KR5

P176/KR6

P177/KR7

P160/PWM0

P161/PWM1

P162/PWM2

Note 1

PP

V

P163/PWM3

P165/VSOUT

P166/HSOUT0

P167/HSOUT1

P164/CSYNCIN

RESET

P100/RTP00

P101/RTP01

P102/RTP02

P103/RTP03

P104/RTP04

SS

DD

X2

X1

V

V

XT1

XT2

Connect to VSS in normal operation mode.
SCL0, SCL1, SDA0, and SDA1 are valid only for the µPD70F3040Y.

2.

Preliminary Data Sheet U14622EJ1V0DS00

SS

DD

V

V

P105/RTP05

P106/RTP06

P107/RTP07

P150/RTP10

P151/RTP11

P152/RTP12

P153/RTP13

P154/RTP14

P155/RTP15

µµµµ

PD70F3040, 70F3040Y

PIN IDENTIFICATION

A16 to A21: Address Bus P120 to P127: Port 12
AD0 to AD15: Address/Data Bus P130 to P137: Port 13
ADTRG: AD Trigger Input P140 to P147: Port 14
ANI0 to ANI15: Analog Input P150 to P157: Port 15
ASCK0, ASCK1: Asynchronous Serial Clock P160 to P167: Port 16
ASTB: Address Strobe P170 to P177: Port 17
AVDD: Analog Power Supply P180 to P187: Port 18

REF

AV

: Analog Reference Voltage P190 to P197: Port 19
AVSS: Analog Ground PWM0 to PWM3: Pulse Width Modulation
BVDD: Bus Interface Power Supply RD: Read
BVSS: Bus Interface Ground RESET: Reset
CLKOUT: Clock Output RTP00 to RTP07,: Real-time Output Port
CLO: Clock Output (divided) RTP10 to RTP17
CSYNCIN: Csync Input RTPTRG0, RTPTRG1: RTP Trigger Input
DSTB: Data Strobe R/W: Read/Write Status
HLDAK: Hold Acknowledge RXD0, RXD1: Receive Data
HLDRQ: Hold Request SCK0 to SCK4: Serial Clock
HSOUT0, HSOUT1: Hsync Output SCL0, SCL1: Serial Clock
INT CP 80 to IN T CP 83 ,: Interrupt Request from Peripherals SDA0, SDA1: Serial Data
INTCP90 to INTCP93, SI0 to SI4: Serial Input
INTP0 to INTP6, SO0 to SO4: Serial Output
INTTCLR8, TCLR8: Timer Clear
INTTI8, INTTI9 TI000, TI001, TI010,: Timer Input
KR0 to KR7: Key Return TI011, TI2 to TI11
LBEN: Lower Byte Enable TO0 to TO7, TO80,: Timer Output
NMI: Non-Maskable Interrupt Request TO81, TO10, TO11
P00 to P07: Port 0 TXD0, TXD1: Transmit Data
P10 to P15: Port 1 UBEN: Upper Byte Enable
P20 to P27: Port 2 VDD: Power Supply
P30 to P37: Port 3 VPP: Programming Power Supply
P40 to P47: Port 4 VSOUT: Vsync Output
P50 to P57: Port 5 VSS: Ground
P60 to P65: Port 6 WAIT: Wait
P70 to P77: Port 7 WRH: Write Strobe High Level Data
P80 to P87: Port 8 WRL: Write Strobe Low Level Data
P90 to P96: Port 9 X1, X2: Crystal for Main System Clock
P100 to P107: Port 10 XT1, XT2: Crystal for Subsystem Clock
P110 to P113: Port 11

Preliminary Data Sheet U14622EJ1V0DS00

3

INTERNAL BLOCK DIAGRAM

µµµµ

PD70F3040, 70F3040Y

INTP0 to INTP6

NMI

INTCP80 to INTCP83,

INTCP90 to INTCP93

INTTCLR8

INTTI8, INTTI9

TI000, TI001,

TI010, TI011

TO0, TO1

TO80, TO81

TI8, TI9

TCLR8

TI2/TO2, TI3/TO3
TI4/TO4, TI5/TO5
TI6/TO6, TI7/TO7

TI10/TO10, TI11/TO11

CSYNCIN

HSOUT0, HSOUT1,

VSOUT

SO0

SI0/SDA0

SCK0/SCL0

SI2/SDA1

SCK2/SCL1

Note 2
Note 2

SO2

Note 2
Note 2

SO1/TXD0

SI1/RXD0

SCK1/ASCK0

SO3/TXD1

SI3/RXD1

SCK3/ASCK1

SO4

SI4

SCK4

KR0 to KR7

PWM0 to PWM3

INTC

Timer/counter

16-bit timers:

TM0, TM1

8-bit timers

:
TM2 to TM7,
TM10, TM11

24-bit timers:

TM8, TM9

Vsync/Hsync

SIO

Note 3

CSI0/I2C0

Note 3

CSI2/I2C1

CSI1/UART0

CSI3/UART1

Variable

length CSI4

Key return function

DMAC: 6 ch

PWM

ROM CPU

Note 1

PC

32-bit barrel

shifter

RAM

System
register

General registers

16 KB

32 bits × 32

Ports

P190 to P197

P180 to P187

P170 to P177

P160 to P167

P150 to P157

P140 to P147

P130 to P137

P120 to P127

P110 to P113

P100 to P107

Watch timer

Watchdog timer

RTP00 to RTP07,

RTP

RTP10 to RTP17
RTPTRG0,

RTPTRG1

ROM correction

Multiplier

16 × 16 → 32

ALU

P90 to P96

P80 to P87

P70 to P77

P60 to P65

P50 to P57

Instruction

P40 to P47

P30 to P37

P20 to P27

P10 to P15

queue

BCU

A/D

converter

SS

DD

REF

AV

AV

AV

P00 to P07

HLDRQ
HLDAK

ASTB
DSTB/RD
R/W/WRH
UBEN
LBEN/WRL
WAIT
A16 to A21
AD0 to AD15

CG

ADTRG

ANI0 to ANI15

CLKOUT
CLO
X1
X2
XT1
XT2
RESET

V

DD

V

SS

BV

DD

BV

SS

V

PP

Notes 1.

4

256 KB (Flash memory)
SDA0, SDA1, SCL0, and SCL1 are valid only for the

2.

The I2C function is valid only for the µPD70F3040Y.

3.

Preliminary Data Sheet U14622EJ1V0DS00

PD70F3040Y.

µ

µµµµ

PD70F3040, 70F3040Y

CONTENTS

1. PIN FUNCTIONS.................................................................................................................................. 6

1.1 Port Pins.................................................................................................................................................... 6

1.2 Non-Port Pins...........................................................................................................................................10

1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins.......................14

2. ELECTRICAL SPECIFICATIONS...................................................................................................... 18

3. PACKAGE DRAWING....................................................................................................................... 39

4. RECOMMENDED SOLDERING CONDITION.................................................................................. 40

Preliminary Data Sheet U14622EJ1V0DS00 5

µµµµ

PD70F3040, 70F3040Y

1. PIN FUNCTIONS

1.1 Port Pins

Pin Name I/O PULL Function Alternate Function

(1/4)

P00 NMI
P01 INTP0
P02 INTP1
P03 INTP2
P04 INTP3
P05 INTP4/ADTRG
P06 INTP5/RTPTRG0
P07
P10 SI0/SDA0
P11 SO0
P12 SCK0/SCL0
P13 SI1/RXD0
P14 SO1/TXD0
P15
P20 SI2/SDA1
P21 SO2
P22 SCK2/SCL1
P23 SI3/RXD1
P24 SO3/TXD1
P25 SCK3/ASCK1
P26 TI2/TO2
P27
P30 TI000
P31 TI001
P32 TI010
P33 TI011
P34 TO0
P35 TO1
P36 TI4/TO4
P37
P40 AD0
P41 AD1
P42 AD2
P43 AD3
P44

I/O Yes Port 0

8-bit I/O port
Input/output mode can be specified in 1-bit units.

INTP6

I/O Yes Port 1

6-bit I/O port
Input/output mode can be specified in 1-bit units.

SCK1/ASCK0

I/O Yes Port 2

8-bit I/O port
Input/output mode can be specified in 1-bit units.

TI3/TO3

I/O Yes Port 3

8-bit I/O port
Input/output mode can be specified in 1-bit units.

TI5/TO5

I/O No Port 4

8-bit I/O port
Input/output mode can be specified in 1-bit units.

AD4

Remark

PULL: On-chip pull-up resistor

6 Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Pin Name I/O PULL Function Alternate Function

(2/4)

P45 AD5
P46 AD6
P47
P50 AD8
P51 AD9
P52 AD10
P53 AD11
P54 AD12
P55 AD13
P56 AD14
P57
P60 A16
P61 A17
P62 A18
P63 A19
P64 A20
P65
P70 ANI0
P71 ANI1
P72 ANI2
P73 ANI3
P74 ANI4
P75 ANI5
P76 ANI6
P77
P80 ANI8
P81 ANI9
P82 ANI10
P83 ANI11
P84 ANI12
P85 ANI13
P86 ANI14
P87
P90 LBEN/WRL
P91 UBEN
P92 R/W/WRH
P93

I/O No Port 4

8-bit I/O port
Input/output mode can be specified in 1-bit units.

AD7

I/O No Port 5

8-bit I/O port
Input/output mode can be specified in 1-bit units.

AD15

I/O No Port 6

6-bit I/O port
Input/output mode can be specified in 1-bit units.

A21

Input No Port 7

8-bit input port

ANI7

Input No Port 8

8-bit input port

ANI15

I/O No Port 9

7-bit I/O port
Input/output mode can be specified in 1-bit units.

DSTB/RD

Remark

PULL: On-chip pull-up resistor

Preliminary Data Sheet U14622EJ1V0DS00 7

µµµµ

PD70F3040, 70F3040Y

Pin Name I/O PULL Function Alternate Function
P94 ASTB
P95 HLDAK
P96
P100 RTP00
P101 RTP01
P102 RTP02
P103 RTP03
P104 RTP04
P105 RTP05
P106 RTP06
P107
P110 –
P111 –
P112 –
P113
P120 SI4
P121 SO4
P122 SCK4
P123 CLO
P124 TI6/TO6
P125 TI7/TO7
P126 TI10/TO10
P127
P130 INTCP80
P131 INTCP81
P132 INTCP82
P133 INTCP83
P134 TI8/INTTI8
P135 TCLR8/INTTCLR8
P136 TO80
P137
P140 INTCP90
P141 INTCP91
P142 INTCP92
P143 INTCP93
P144 TI9/INTTI9
P145 RTPTRG1
P146 –
P147

I/O No Port 9

7-bit I/O port
Input/output mode can be specified in 1-bit units.

HLDRQ

I/O Yes Port 10

8-bit I/O port
Input/output mode can be specified in 1-bit units.

RTP07

I/O No Port 11

4-bit I/O port
Input/output mode can be specified in 1-bit units.

–

I/O No Port 12

8-bit I/O port
Input/output mode can be specified in 1-bit units.

TI11/TO11

I/O No Port 13

8-bit I/O port
Input/output mode can be specified in 1-bit units.

TO81

I/O No Port 14

8-bit I/O port
Input/output mode can be specified in 1-bit units.

–

(3/4)

Remark

PULL: On-chip pull-up resistor

8 Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Pin Name I/O PULL Function Alternate Function
P150 RTP10
P151 RTP11
P152 RTP12
P153 RTP13
P154 RTP14
P155 RTP15
P156 RTP16
P157
P160 PWM0
P161 PWM1
P162 PWM2
P163 PWM3
P164 CSYNCIN
P165 VSOUT
P166 HSOUT0
P167
P170 KR0
P171 KR1
P172 KR2
P173 KR3
P174 KR4
P175 KR5
P176 KR6
P177
P180 –
P181 –
P182 –
P183 –
P184 –
P185 –
P186 –
P187
P190 –
P191 –
P192 –
P193 –
P194 –
P195 –
P196 –
P197

I/O No Port 15

8-bit I/O port
Input/output mode can be specified in 1-bit units.

RTP17

I/O No Port 16

8-bit I/O port
Input/output mode can be specified in 1-bit units.

HSOUT1

I/O Yes Port 17

8-bit I/O port
Input/output mode can be specified in 1-bit units.

KR7

I/O No Port 18

8-bit I/O port
Input/output mode can be specified in 1-bit units.

–

I/O No Port 19

8-bit I/O port
Input/output mode can be specified in 1-bit units.

–

(4/4)

Remark

PULL: On-chip pull-up resistor

Preliminary Data Sheet U14622EJ1V0DS00 9

µµµµ

PD70F3040, 70F3040Y

1.2 Non-Port Pins

Pin Name I/O PULL Function Alternate Function
A16 to A21 Output No Address bus 16 to 21 P60 to P65
AD0 to AD7 P40 to P47
AD8 to AD15
ADTRG Input Yes A/D converter external t ri gger i nput P05/INTP4
ANI0 to ANI7 Input No P70 to P77
ANI8 to ANI15 Input No
ASCK0 P15/SCK1
ASCK1
ASTB Output No External address strobe signal output P94

DD

AV

REF

AV

SS

AV

DD

BV

SS

BV

CLKOUT Output – Internal system clock output –
CLO Output No CLO output signal P123
CSYNCIN Input No Csync si gnal input P164
DSTB Output No External data strobe signal output P93/RD
HLDAK Output No Bus hold acknowledge output P95
HLDRQ Input No Bus hold request input P96
HSOUT0 Hsync signal output before compensation P166
HSOUT1
INTCP80 to

INTCP83
INTCP90 to

INTCP93
INTP0 to INTP3 External interrupt request i nput (anal og noi se elimination) P01 to P04
INTP4 P05/ADTRG
INTP5
INTP6

I/O No Address/data multiplexed bus 0 to 15

P50 to P57

Analog input to A/D converter

P80 to P87

Input Yes Baud rate clock input for UART0 and UART1

P25/SCK3

– – Posi t i ve power supply for A/D converter and ports used for

alternate functions

Input – Reference voltage input for A/D c onv erter –

– – Ground potenti al f or A/D converter and ports used for alternate

functions

– – Posi t i ve power supply for bus interface and ports used for

alternate functions

– – Ground potenti al f or bus interface and ports used for alternat e

functions

Output No

Hsync signal output af ter compensation P167

Input No Ext ernal capture input for CC80 to CC83 P130 to P133

Input No Ext ernal capture input for CP90 to CP93 P140 to P143

Input Yes

External interrupt request i nput (di gi tal noise elimination)

P06/RTPTRG0

External interrupt request i nput (di gi tal noise elimination
supporting remote controller)

P07

(1/4)

–

–

–

–

Remark

PULL: On-chip pull-up resistor

10 Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Pin Name I/O PULL Function Alternate Function

(2/4)

INTTCLR8 Input No P135/TCLR8
INTTI8 P134/TI8
INTTI9
KR0 to KR7 Input Yes Key return input P170 to P177
LBEN Output No Lower byte enabl e signal output for external data bus P90/WRL
NMI Input Yes Non-maskable interrupt request input P00
PWM0 to PWM3 Output No Output of PWM channels 0 to 3 P160 to P163
RD Output No Bus read strobe si gnal output P93/DSTB
RESET I nput – System reset input –
RTP00 to RTP07 P100 to P107
RTP10 to RTP17
RTPTRG0 Yes P06
RTPTRG1
R/W Output No External read/write status output P92/WRH
RXD0 P13/SI1
RXD1
SCK0 P12/SCL0
SCK1 P15/ASCK0
SCK2 P22/SCL1
SCK3
SCK4
SCL0 P12/SCK0
SCL1
SDA0 P10/SI0
SDA1
SI0 P10/SDA0
SI1 P13/RXD0
SI2 P20/SDA1
SI3
SI4
SO0 P11
SO1 P14/TXD0
SO2 P21
SO3
SO4
TCLR8 Input No External clear input for TM 8 P135/INTTCLR8

Input No

Output Yes Real-time output port

Input

Input Yes Serial receive data input for UART0 and UART1

I/O

I/O Yes Serial clock I/O for I

I/O Yes Serial transmit/receive data I/O for I

Input

Output

Yes Serial clock I/O for CSI0 to CSI3 (3-wire mode)

Yes Serial receive data input for CSI0 to CSI3 (3-wire mode)

Yes Serial transmi t data output for CSI0 to CSI3

External interrupt request i nput (di gi tal noise elimination)

P144/TI9

P150 to P157

RTP external trigger input

No

No Variable-lengt h CSI4 serial clock I/ O P122

2

C0 and I2C1

(

PD70F3040Y)

µ

2

C0 and I2C1

(

PD70F3040Y)

µ

No Variable-length CS I4 serial receive data input (3-wire mode) P120

No Variable-length CS I4 serial transmit data output P121

P146

P23/SI3

P25/ASCK1

P22/SCK2

P20/SI2

P23/RXD1

P24/TXD1

Remark

PULL: On-chip pull-up resistor

Preliminary Data Sheet U14622EJ1V0DS00 11

µµµµ

PD70F3040, 70F3040Y

Pin Name I/O PULL Function Alternate Function

(3/4)

TI000 External count clock input/ external capture trigger input for TM0 P30
TI001 External capture trigger input for TM0 P31
TI010 External count clock input/ external capture trigger input for TM1 P32
TI011 External capture trigger input for TM1 P33
TI2 External count clock input for TM2 P26/TO2
TI3 External count clock input for TM3 P27/TO3
TI4 External count clock input for TM4 P36/TO4/A15
TI5
TI6 External count clock input for TM6 P124/TO6
TI7 External count clock input for TM7 P125/TO7
TI8 External count clock input for TM8 P134/INTTI8
TI9 External count clock input for TM9 P144/INTTI9
TI10 External count clock i nput for TM10 P126/TO10
TI11
TO0 Pulse s ignal output for TM0 P34
TO1 Pulse s ignal output for TM1 P35
TO2 Pulse s ignal output for TM2 P26/TI2
TO3 Pulse s ignal output for TM3 P27/TI3
TO4 Pulse s ignal output for TM4 P36/TI4
TO5
TO6 Pulse s ignal output for TM6 P124/TI6
TO7 Pulse s ignal output for TM7 P125/TI7
TO80 Pulse signal output 0 for TM 8 P136
TO81 Pulse signal output 1 for TM 8 P137
TO10 Pulse signal output for TM 10 P126/TI10
TO11
TXD0 P14/SO1
TXD1
UBEN Output No Higher byte enable signal output f or external data bus P91

DD

V

PP

V
VSOUT Output No Vsync signal output P165

SS

V
WAIT Input No External WAIT signal i nput –
WRH Higher byte write strobe signal output for external data bus P92/R/W
WRL

Input

Output

Output Yes Serial transmit data output f or UA RT0 and UART1

– – Posi t i ve power supply pin –
– – High voltage application pin for program write/veri fy –

– – Ground potenti al –

Output No

Yes

External count clock i nput for TM5 P37/TO5

No

External count clock i nput for TM11 P127/TO11

Yes

Pulse signal output for TM5 P37/TI5

No

Pulse signal output for TM11 P127/TI11

P24/SO3

Lower byte write strobe signal output for external data bus P90/LBEN

Remark

PULL: On-chip pull-up resistor

12 Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Pin Name I/O PULL Function Alternate Function

(4/4)

X1 Input –
X2 –
XT1 Input –
XT2 –

Remark

PULL: On-chip pull-up resistor

No Resonator connec tion for main system clock

No Resonator connec tion for subsystem clock

–

–

Preliminary Data Sheet U14622EJ1V0DS00 13

µµµµ

PD70F3040, 70F3040Y

1.3 Pin I/O Circuits, I/O Buffer Supply, and Recommended Connection of Unused Pins

Table 1-1 shows the input/output circuit type of each pin and the recommended connection of unused pins.
For the input/output configuration of each type, refer to Figure 1-1.

Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (1/2)

Pin Alternate Function I/O Circ ui t

P00 NMI

Type

5-W V

Power Supply

P01 to P04 INTP0 to INTP3
P05 INTP4/ADTRG
P06 INTP5/RTPTRG0
P07 INTP6
P10 SI0/SDA0 10-F

V
P11 SO0 10-E
P12 SCK0/SCL0 10-F
P13 SI1/RXD0 5-W
P14 SO1/TXD0 10-E
P15 SCK1/ASCK0 10-F
P20 SI2/SDA1 10-F

V
P21 SO2 10-E
P22 SCK2/SCL1 10-F
P23 SI3/RXD1 5-W
P24 SO3/TXD1 10-E
P25 SCK3/ASCK1 10-F
P26, P27 TI2/TO2, TI3/TO3 5-W
P30, P31 TI000, TI001

5-W

V
P32, P33 TI010, TI011
P34, P35 TO0, TO1 5-A
P36 TI4/TO4

5-W
P37 TI5/TO5
P40 to P47 AD0 to AD7 5 BV
P50 to P57 AD8 to AD15 5 BV
P60 to P65 A16 to A21 5 BV
P70 to P77 ANI0 to ANI7 9 AV
P80 to P87 ANI8 to ANI15 9 AV
P90 LBEN/WRL

5BV
P91 UBEN
P92 R/W/WRH
P93 DSTB/RD
P94 ASTB
P95 HLDAK
P96 HLDRQ
P100 to P107 RTP00 to RTP07 10-E V
P110 to P113 – 5 V
P120 SI4 5-K V

I/O Buffer

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

Recommended Connection Method

Input: Independently connect t o VDD or V

SS

via a resistor

Output: Leave open

Input: Independently connect t o BVDD or BV

via a resistor

Output: Leave open

Connect to AV

SS

Input: Independently connect t o BVDD or BV

via a resistor

Output: Leave open

Input: Independently connect t o VDD or V

SS

via a resistor

Output: Leave open

SS

SS

14 Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Table 1-1. Types of Pin I/O Circuit and Recommended Connection of Unused Pins (2/2)

Pin Alternate Function I/O Circuit

Type

P121 SO4 10-G

Power Supply

V
P122 SCK4 10-H
P123 CLO 5
P124 TI6/TO6

5-K
P125 TI7/TO7
P126 TI10/TO10
P127 TI11/TO11
P130 to P133 INTCP80 to INTCP83

5-K

V
P134 TI8/INTTI8
P135 TCLR8/INTTCLR8
P136, P137 TO80, TO81 5
P140 to P143 INTCP90 to INTCP93

5-K

V
P144 TI9/INTTI9
P145 RTPTRG1
P146, P147 – 5
P150 to P157 RTP10 to RTP17 5 V
P160 to P163 PWM0 to PWM3 5

V
P164 CSYNCIN 5-K
P165 VSOUT

5
P166 HSOUT0
P167 HSOUT1
P170 to P177 KR0 to KR7 5-K V
P180 to P187 – 5 V
P190 to P197 – 5 V
CLKOUT – 4 BV
WAIT – 1 BV
RESET – 2 V
X1 – – V
X2 – – V
XT1 – – V
XT2 – – V

REF

AV
V
V
V
AV
AV
BV
BV

PP

DD

SS

DD

SS

DD

SS

– – – Connect to AV
– – – Connect to V
––– –
––– –
– – – Connect to V
– – – Connect to V
– – – Connect to V
– – – Connect to V

I/O Buffer

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

DD

Recommended Connection Method

Input: Independently connect t o VDD or V

via a resistor

Output: Leave open

Leave open
Connect to VDD via a resistor

–

–
Leave open
Connect to V

SS

Leave open

SS

SS

DD

SS

DD

SS

SS

Preliminary Data Sheet U14622EJ1V0DS00 15

Figure 1-1. Pin Input/Output Circuits (1/2)

Type 1 Type 5

V

DD

P-ch

IN

N-ch

Data

Output

disable

Input

enable

µµµµ

PD70F3040, 70F3040Y

V

DD

P-ch

IN/OUT

N-ch

Type 2 Type 5-A

Pullup

enable

Data

IN

Output

disable

Input

Schmitt-triggered input with hysteresis characteristics

enable

Type 4 Type 5-K

V

DD

Data

P-ch

Data

OUT

Output

disable

N-ch

Output

disable

V

V

DD

P-ch

N-ch

DD

P-ch

N-ch

V

DD

P-ch

IN/OUT

IN/OUT

Input

Push-pull output that can be set for high impedance output

enable

(both P-ch and N-ch are off)

16 Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Figure 1-1. Pin Input/Output Circuits (2/2)

Type 5-W Type 10-F

Pullup

enable

Data

V

DD

P-ch

V

DD

P-ch

Pullup

enable

Data

IN/OUT

Output

disable

Input

enable

N-ch

Open

Output

disable

Input

enable

Type 9 Type 10-G

P-ch

Comparator

IN

N-ch

+
–

Data

Open drain

V

REF

(Threshold voltage)

Output

disable

V

DD

P-ch

N-ch

V

V

DD

P-ch

N-ch

DD

P-ch

IN/OUT

IN/OUT

Input enable

Input

enable

Type 10-E Type 10-H

Pullup

enable

Data

Open

Output

disable

Input

V

DD

P-ch

N-ch

V

DD

P-ch

Data

Open drain

IN/OUT

Output

disable

Input

enable

enable

V

DD

P-ch

IN/OUT

N-ch

Preliminary Data Sheet U14622EJ1V0DS00 17

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)

Parameter Symbol Conditions Ratings Unit

DD

AV
BV
AV
BV

V

DD

DD

SS

SS

I1

V

I2

V

I3

V

K

IAN

REF

OL

(V

Note 1

(BV

Note 2

PP

V
X1, XT1, VDD = 2.7 to 3.6 V

(AV

Note 3

REF

AV

pin
Per pin 4.0 mA
Total for P00 to P07 and P150 to P157 25 mA
Total for P100 to P107 and P160 to P167 25 mA
Total for P170 to P177 and P190 to P197 25 mA
Total for P124 to P127 and P180 to P187 25 mA
Total for P30 to P37 and P120 to P123 25 mA
Total for P12 to P15, P20 to 27, and P110

to P113
Total for P50 to P57, P60 to P65, and

CLKOUT
Total for P40 to P47 and P90 to P96 25 mA
Total for P130 to P137 and P140 to P147 25 mA

OH

Per pin –4.0 mA
Total for P00 to P07 and P150 to P157 –25 mA
Total for P100 to P107 and P160 to P167 –25 mA
Total for P170 to P177 and P190 to P197 –25 mA
Total for P124 to P127 and P180 to P187 –25 mA
Total for P30 to P37 and P120 to P123 –25 mA
Total for P12 to P15, P20 to 27, and P110

to P113
Total for P50 to P57, P60 to P65, and

CLKOUT
Total for P40 to P47 and P90 to P96 –25 mA
Total for P130 to P137 and P140 to P147 –25 mA

O1

V

O2

V

A

Note 1
Note 2

Normal operation mode –40 to +85 °COperating ambient temperature T

(V
(BV

Flash programming mode +10 to +40 °C

stg

Supply voltage

Input voltage

Clock input voltage V

Analog input voltage V
Analog reference input voltage AV
Output current, low I

Output current, high I

Storage temperature T

µµµµ

PD70F3040, 70F3040Y

–0.5 to +4.6 V
–0.5 to +4.6 V
–0.5 to +4.6 V
–0.5 to +0.5 V
–0.5 to +0.5 V

DD

) –0.5 to VDD + 0.5

DD

) –0.5 to BVDD + 0.5

–0.5 to +8.5 V

–0.5 to V

DD

) –0.5 to AVDD + 0.5

–0.5 to AV

DD

DD

25 mA

25 mA

–25 mA

–25 mA

DD

) –0.5 to VDD + 0.5

DD

) –0.5 to BVDD + 0.5

–40 to +125 °C

+ 1.0

+ 0.5

Note 4

Note 4

Note 4

Note 4

Note 4

Note 4

Note 4

V
V

V
V
V

VOutput voltage
V

Notes 1.

18

Ports 0, 1, 2, 3, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, RESET (including alternate-function pins)

Ports 4, 5, 6, 9, WAIT (including alternate-function pins)

2.

Ports 7, 8 (including alternate-function pins)

3.

Be sure not to exceed each absolute maximum rating (MAX.).

4.

Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Cautions 1. Avoid direct connections among the IC device output (or I/O) pins and between VDD or V

and GND. However, direct connections among open-drain and open-connector pins are
possible, as are direct connections to external circuits that have timing designed to prevent
output contention with pins that become high-impedance.

2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions indicated for DC characteristics and AC characteristics represent
the quality assurance range during normal operation.

A

Capacitance (T

Input capacitance C
I/O capacitance C
Output capacitance C

= 25°C, VDD = VSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

I

fC = 1 MHz
Unmeasured pins returned to 0 V

IO

O

15 pF
15 pF
15 pF

Operating Conditions

CC

(1) CPU Operation Frequency

Parameter Symbol Conditions MIN. TYP. MAX. Unit

CPU

When main system clock is operating 0.5 16 MHzCPU operation frequency f
When subsystem clock is operating 32.768 kHz

(2) Supply Voltage

Parameter Symbol Conditions MIN. TYP. MAX. Unit

DD

Supply voltage

V
AV
BV

DD

DD

2.7 3.6 V

2.7 3.6 V

2.7 3.6 V

(3) Operating Frequency for Each Supply Voltage

Internal Operating Clock Frequency Supply Voltage (VDD = AVDD = BVDD)
4 MHz ≤ fXX ≤ 16 MHz 2.7 to 3.6 V
fXT = 32.768 kHz 2.7 to 3.6 V

Preliminary Data Sheet U14622EJ1V0DS00

19

Recommended Oscillator

µµµµ

PD70F3040, 70F3040Y

(1) Main System Clock Oscillator (T

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Oscillation frequency f
Oscillation stabil ization

time

Values vary depending on the settings of the oscillation stabilization selection register (OSTS).

Note

Remarks 1.

Place the oscillator as close as possible to X1 and X2.
Do not wire other signal lines within the broken lines.

2.

For resonator selection and oscillation constants, customers are advised to either evaluate the

3.

XX

oscillation themselves, or apply to the resonator manufacturer for evaluation.

A

=

40 to +85

−−−−

After reset release 219/f
After STOP mode release

C)

°°°°

X2 X1

416MHz

Note

XX

s
s

20

Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

(2) Subsystem Clock Oscillator (TA =

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Oscillation frequency f
Oscillation stabil ization time 10 s

Remarks 1.

Place the oscillator as close as possible to XT1 and XT2.
Do not wire other signal lines within the broken lines.

2.

3.For resonator selection and oscillation constants, customers are advised to either evaluate the
oscillation themselves, or apply to the resonator manufacturer for evaluation.

XT

40 to +85

−−−−

C)

°°°°

XT1 XT2

32 32.768 35 kHz

Preliminary Data Sheet U14622EJ1V0DS00

21

µµµµ

PD70F3040, 70F3040Y

DC Characteristics (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input voltage, high V

Input voltage, low V

V
V

Output voltage, low

V
V

V

Output leakage current, high I
Output leakage current, low I
Supply current

Pull-up resistor R

V
V
V
V

V
V
V
V

I

I
I

I

I
I
I
I

Pins in

IH1

Pins in

IH2

Pins in

IH3

Pins in

IH4

IH5

X1, XT1, XT2 0.8V
Pins in

IL1

Pins in

IL2

Pins in

IL3

Pins in

IL4

IL5

X1, XT1, XT2 V

Note 1

OH1

Notes 2, 3

OH2

Note 1

OL1

Notes 2, 3

OL2

, WAIT

Note 1
Note 2

, RESET

Note 3
Note 4

, WAIT

Note 1
Note 2

, RESET

Note 3
Note 4

, CLKOUT

, CLKOUT

(excluding

OH

I

= –3 mA 0.8BV

OH

= –1 mA 0.8V

I

DD

0.7BV

DD

0.7V

DD

0.75V

DD

0.7AV

DD

SS

BV

– 0.5 0.3BV

SS

– 0.5 0.3V

V

SS

V

– 0.5 0.3V

SS

– 0.5 0.3AV

AV

SS

DD

DD

P10, 12, 20, 22)

OL3

P10, 12, 20, 22 0.4 V

LIH1

LIH2

LIL1

VI = VDD = AVDD =

DD

BV

VI = 0 V

Other than X1,

XT1, XT2

X1, XT1, XT2 20

Other than X1,

XT1, XT2

LIL2

LOH

VO = VDD = AVDD = BV

LOL

VO = 0 V –5

DD1

DD2

DD3

DD4

Normal operation (fXX = 16 MHz) 45 65 mA
HALT mode (fXX = 16 MHz) 20 35 mA
IDLE mode (fXX = 16 MHz) 6 14 mA
STOP mode (subsystem clock

operation: f

XT

= 32.768 kHz, watch

X1, XT1, XT2 –20

DD

13 115

timer operation

STOP mode (subsystem clock stopped) 1 100

L

10 30 100 k

DD

BV

DD

V

DD

V

DD

AV

DD

V

DD

DD

DD

DD

DD

0.2V

0.4 V

0.4 V

5

–5

5

V
V
V
V
V
V
V
V
V
V
VOutput voltage, high
V

AInput leakage current, hi gh

µ

A

µ

AInput leakage current, l ow

µ

A

µ

A

µ

A

µ

A

µ

A

µ

Ω

Notes 1.

Ports 4, 5, 6, 9 (including alternate-function pins)
P11, P14, P21, P24, P34, P35, P100 to P107, P110 to P113, P121, P123, P136, P137, P146, P147 , P150 to

2.

P157, P160 to P163, P165 to P167, P180 to P187, P190 to P197 (including alternate-function pins)
P00 to P07, P10, P12, P13, P15, P20, P22, P23, P25 to P27, P30 to P33, P36, P37, P120, P122, P124

3.

to P127, P130 to P135, P140 to P145, P164, P170 to P177 (including alternate-function pins)

Ports 7, 8 (including alternate-function pins)

4.

Caution The TYP. value of V

22

DD

is 3.3 V. The current that is consumed at output buffers is not included.

Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Data Retention Characteristics (TA = –40 to +85°C, VDD = AV

Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention voltage V
Data retention current I
Supply voltage rise time t
Supply voltage fall time t
Supply voltage hold time

(from STOP mode setting)
STOP release signal input time t
Data retention high-level input voltage V
Data retention low-level input voltage V

Remark

n = 1 to 5

Setting STOP mode

V

DD

DDDR

DDDR

RVD

FVD

HVD

t

DREL

IHDR

ILDR

STOP mode 1.8 3.6 V

DDDR

V

[V] 1 100

All input ports V
All input ports 0 V

t

FVD

t

HVD

DD

= BV

V

DD

= 2.7 to 3.6 V, VSS = AV

200
200

0ms

0ms

IHn

t

RVD

DDDR

t

SS

DREL

= BV

DDDR

V

ILn

SS

= 0 V )

A

µ

s

µ

s

µ

V
V

RESET

V

(input)

NMI, INTP0 to INTP3

(input)

IHDR

V

IHDR

STOP release interrupt (NMI)

(when STOP mode is released

at rising edge)

V

ILDR

Caution Be sure to shift to and return from STOP mode when VDD is 2.7 V or higher.

Preliminary Data Sheet U14622EJ1V0DS00

23

AC Characteristics

DD

AC Test Input Waveforms (V

V

DD

0 V

, BVDD, AVDD)

AC Test Output Test Point (BVDD)

µµµµ

PD70F3040, 70F3040Y

V

IH

Test points

V

IL

V

OH

V

IH

V

IL

V

OH

Test points

V

OL

V

OL

Load Conditions

DUT

(Device under test)

CL = 50 pF

Caution If the load capacitance exceeds 50 pF due to the circuit configuration, bring the load

capacitance of the device to 50 pF or less by inserting a buffer or by some other means.

24

Preliminary Data Sheet U14622EJ1V0DS00

Clock Timing

µµµµ

PD70F3040, 70F3040Y

Operating Condition (T

A

= –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, V

SS

= AVSS = BVSS = 0 V)

Parameter Symbol Conditions MIN. MAX. Unit
X1 input cycle 62.5 250 ns
XT1 input cycle
X1 input high-level width 31.2 125 ns
XT1 input high-level width
X1 input low-level width 31.2 125 ns
XT1 input low-level width
X1 input rise time t
X1 input fall time t
CLKOUT output cycle t
CLKOUT high-level width t
CLKOUT low-level width t
CLKOUT rise time t
CLKOUT fall time t

CYK

Remark

T = t

CYX

t

<1>

28.6 31.2

WXH

t

<2>

14.3 15.6

WXL

t

<3>

14.3 15.6

XR

<4>

XF

<5>

CYK

<6> 62.5 ns 31.2 µs

WKH

<7> 0.4 (T–20) ns

WKL

<8> 0.4 (T–20) ns

KR

<9> 10 ns

KF

<10> 10 ns

(<1>–<2>–<3>)/2
(<1>–<2>–<3>)/2

Clock Timing

µ

µ

µ

ns
ns

s

s

s

X1, XT1 (input)

<4> <5>

CLKOUT (output)

Timing of Pins Other Than X1 and CLKOUT Pins
(TA = –40 to +85

C, VDD = AV

°°°°

DD

= BV

DD

= 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V, Output Pin Load Capacitance: C

= 50 pF)

Parameter Symbol Conditions MIN. MAX. Unit
Output rise time t
Output fall time t

OR

OF

<2>

<1>

<3>

<6>

<7>

<9> <10>

<8>

L

20 ns
20 ns

Preliminary Data Sheet U14622EJ1V0DS00

25

Bus Timing (CLKOUT Asynchronous)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

Parameter Symbol Conditions MIN. MAX. Unit

µµµµ

PD70F3040, 70F3040Y

Address setup time (to ASTB↓)t
Address hold time (from ASTB↓)t
Address float from DSTB

↓

Setup time from address to data input t
Setup time from DSTB↓ to data input t
Delay time from ASTB↓ to DSTB

↓

Data input hold time (from DSTB↑)t
Address output time from DSTB
Delay time from DSTB↑ to ASTB
Delay time from DSTB↑ to ASTB

↑

↑
↓

DSTB low-level width t
ASTB high-level width t
Data output time from DSTB

↓

Data output setup time (to DSTB↑)t
Data output hold time (from DSTB↑)t

HLDRQ high-level width t
HLDAK low-level width t
Delay time from HLDAK↑ to bus output t
Delay time from HLDRQ↓ to HLDAK
Delay time from HLDRQ↑ to HLDAK

↓
↑

SAST

HSTA

FDA

t

DAID

DDID

DSTD

t

HDID

DDA

t

DDST1

t

DDST2

t

WDL

WSTH

DDOD

t

SODD

HDOD

SAWT1

t

SAWT2

t

HAWT1

t

HAWT2

t

SSTWT1

t

SSTWT2

t

HSTWT1

t

HSTWT2

t

WHQH

WHAL

DHAC

DHQHA1

t

DHQHA2

t

<11> 0.5T – 20 ns
<12> 0.5T – 15 ns
<13> 2 ns
<14> (2 + n)T – 30 ns
<15> (1 + n)T – 30 ns
<16> 0.5T – 15 ns
<17> 0 ns
<18> (1 + i)T – 15 ns
<19> 0.5T – 15 ns
<20> (1.5 + i)T – 15 ns
<21> (1 + n)T – 15 ns
<22> T – 15 ns
<23> 15 ns
<24> (1 + n)T – 20 ns
<25> T – 15 ns
<26> 1.5T – 30 nsWAIT setup time (to address)
<27>
<28> (0.5 + n)T nsWAIT hold time (from address)
<29>
<30> 1.5T – 25 nsWAIT setup time (to ASTB↓)
<31>
<32> nT + 5 nsWAIT hold time (from ASTB↓)
<33>
<34> T + 10 ns
<35> T – 15 ns
<36> 0 ns
<37> 1.5T (2n + 7.5)T + 25 ns
<38> 0.5T 1.5T + 25 ns

n ≥ 1

(1.5 + n)T – 30 ns

n ≥ 1

(1.5 + n)T ns

n ≥ 1

(1 + n)T – 5 ns

n ≥ 1

(1 + n)T + 5 ns

Remarks 1.

26

CPU

CPU

(f

T = 1/f
n: Number of wait clocks inserted in the bus cycle.

2.

: CPU operation clock frequency)

Sampling timing changes when a programmable wait is inserted.
i: Number of idle states inserted after the read cycle (0 or 1).

3.

The specifications described above are the values of when a clock with a duty ratio of 1:1 is input

4.

from X1.

Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Bus Timing (CLKOUT Synchronous)
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

Parameter Symbol Conditions MIN. MAX. Unit
Delay time from CLKOUT↑ to address t
Delay time from CLKOUT↑ to address

DKA

<39> 0 19 ns

FKA

t

<40> –12 7 ns

float
Delay time from CLKOUT↓ to ASTB t
Delay time from CLKOUT↑ to DSTB t
Data input setup time (to CLKOUT↑)t
Data input hold time (from CLKOUT↑)t
Delay time from CLKOUT↑ to data

DKST

DKOD

t

<41> –12 7 ns

DKD

<42> –5 14 ns

SIDK

<43> 15 ns

HKID

<44> 5 ns
<45> 19 ns

output
WAIT setup time (to CLKOUT↓)t
WAIT hold time (from CLKOUT↓)t
HLDRQ setup time (to CLKOUT↓)t
HLDRQ hold time (from CLKOUT↓)t
Delay time from CLKOUT↑ to address

SWTK

<46> 15 ns

HKWT

<47> 5 ns

SHQK

<48> 15 ns

HKHQ

<49> 5 ns

DKF

t

<50> 19 ns

float
Delay time from CLKOUT↑ to HLDAK t

Remark

The specifications described above are the values of when a clock with a duty ratio of 1:1 is input from

DKHA

<51> 19 ns

X1.

Preliminary Data Sheet U14622EJ1V0DS00

27

Read Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)

T1 T2 TW T3

CLKOUT (output)

<39>

A16 to A21 (output), Note

µµµµ

PD70F3040, 70F3040Y

AD0 to AD15 (I/O)

ASTB (output)

DSTB (output),

RD (output)

WAIT (input)

<11>

<22>

Address

<41>

<14>

<40>

Hi-Z

<12>

<42> <19>

<13>

<16>

<30> <46>

<32>
<31>
<33>

<15>

<21>

<47> <46> <47>

<43> <44>

Data

<42>

<41>

<17>

<18>

<20>

28

<26>
<28>
<27>
<29>

Note R/W (output), UBEN (output), LBEN (output)

Remark WRL and WRH are high level.

Preliminary Data Sheet U14622EJ1V0DS00

Write Cycle (CLKOUT Synchronous/Asynchronous, 1 Wait)

T1 T2 TW T3

CLKOUT (output)

<39>

A16 to A21 (output), Note

<45>

µµµµ

PD70F3040, 70F3040Y

AD0 to AD15 (I/O)

ASTB (output)

DSTB (output),

WRL (output),
WRH (output)

WAIT (input)

<11>

<22>

<41>

<26>
<28>
<27>
<29>

<12>

<42>

<30> <46>

<32>
<31>
<33>

<23>

<47> <46> <47>

<24>

<21>

DataAddress

<41>

<19>

<42>

<25><16>

Note R/W (output), UBEN (output), LBEN (output)

Remark RD is high level.

Preliminary Data Sheet U14622EJ1V0DS00

29

Bus Hold

CLKOUT (output)

µµµµ

PD70F3040, 70F3040Y

TH TH TH TI

HLDRQ (input)

HLDAK (output)

A16 to A21 (output), Note

AD0 to AD15 (I/O)

ASTB (output)

<48> <49>

<48>

<34>

<51>

<37> <38>

<50>

Hi-Z

Data

Hi-Z

Hi-Z

<51>

<36><35>

DSTB (output), RD (output),

WRL (output), WRH (output)

Note R/W (output), UBEN (output), LBEN (output)

Hi-Z

30

Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Reset/Interrupt Timing
(TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

Parameter Symbol Conditions MIN. MAX. Unit
RESET high-level width t
RESET low-level width t
NMI high-level width t
NMI low-level width t
INTPn high-level width t

INTPn low-level width t

XX

Remarks 1.

T = 1/f
Tsmp = Noise elimination sampling clock frequency

2.

Reset

RESET (input)

WRSH

WRSL

WNIH

WNIL

WITH

WITL

<52> 500 ns
<53> 500 ns
<54> 500 ns
<55> 500 ns
<56>

<57>

n = 0 to 3, analog noise elimination 500 ns
n = 4, 5, digital noise elimination 3T + 20 ns
n = 6, digital noise elimination 3Tsmp + 20 ns
n = 0 to 3, analog noise elimination 500 ns
n = 4, 5, digital noise elimination 3T + 20 ns
n = 6, digital noise elimination 3Tsmp + 20 ns

<52> <53>

Interrupt

<54> <55>

NMI (input)

<56> <57>

INTPn (input)

Remark n = 0 to 6

Preliminary Data Sheet U14622EJ1V0DS00

31

TIn Input Timing
(TA = –40 to +85°C, VDD = AVDD =BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

Parameter Symbol Conditions MIN. MAX. Unit

Tln0, Tln1 (n = 00, 01)

TIIH

t

<58>
High-level width
Tln (n = 2 to 7, 10, 11)
High-level width
Tln0, Tln1 (n = 00, 01)

TIL

t

<59>
Low-level width
Tln (n = 2 to 7, 10, 11)
Low-level width

can be selected by setting the PRMn1 and PRMn0 bits of prescaler mode registers n0, n1 (PRMn0,

T

Note

sam

PRMn1) (n = 0, 1).

TM0 (PRM00, PRM01 registers): T
TM1 (PRM10, PRM11 registers): T

However, when the TIn0 valid edge is selected as the count clock, T

= 2/fXX, 4/fXX, 16/fXX, 64/fXX, 256/fXX, 1/INTWTI period

sam

= 2/fXX, 4/fXX, 16/fXX, 32/fXX, 128/fXX, 256/f

sam

sam

µµµµ

PD70F3040, 70F3040Y

Note

sam

+ 20

2T

XX

3/f

+ 20 ns

Note

sam

+ 20

2T

XX

3/f

+ 20 ns

XX

= 4/fXX (n = 0, 1).

ns

ns

TIn

Remark

<58>

n = 000, 001, 010, 011, 10, 11, 2 to 7

<59>

32

Preliminary Data Sheet U14622EJ1V0DS00

3-Wire SIO Timing

(1) Master Mode (T

Parameter Symbol Conditions MIN. MAX. Unit

µµµµ

PD70F3040, 70F3040Y

A

= –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

SCKn cycle time t
SCKn high-level width t
SCKn low-level wid th t
SIn setup time (to SCKn↑)t
SIn hold time (from SCKn↓)t
Delay time from SCKn↓ to SOn output t

Remark

n = 0 to 3

KCY1

KH1

KL1

SIK1

KSI1

KSO1

<60> 400 ns
<61> 140 ns
<62> 140 ns
<63> 50 ns
<64> 50 ns
<65> 60 ns

(2) Slave Mode (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

Parameter Symbol Conditions MIN. MAX. Unit
SCKn cycle time t
SCKn high-level width t
SCKn low-level wid th t
SIn setup time (to SCKn↑)t
SIn hold time (from SCKn↓)t
Delay time from SCKn↓ to SOn output t

Remark

n = 0 to 3

KCY2

KH2

KL2

SIK2

KSI2

KSO2

<60> 400 ns
<61> 140 ns
<62> 140 ns
<63> 50 ns
<64> 50 ns
<65> 60 ns

Remark

SCKn (I/O)

SIn (input)

SOn (output)

n = 0 to 3

<60>

<61>

<62>

<63> <64>

<65>

Preliminary Data Sheet U14622EJ1V0DS00

33

3-Wire Variable-Length CSI Timing

A

(1) Master Mode (T

= –40 to +85

Parameter Symbol Conditions MIN. MAX. Unit

µµµµ

PD70F3040, 70F3040Y

C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

°°°°

SCK4 cycle time t
SCK4 high-level width t
SCK4 low-level wid th t
SI4 setup time (to SCK4↑)t
SI4 hold time (from SCK4↑)t
Delay time from SCK4↓ to SO4 output t

(2) Slave Mode (TA = –40 to +85

C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

°°°°

KCY1

KH1

KL1

SIK1

KSI1

KSO1

<66> 400 ns
<67> 140 ns
<68> 140 ns
<69> 50 ns
<70> 50 ns
<71> 60 ns

Parameter Symbol Conditions MIN. MAX. Unit
SCK4 cycle time t
SCK4 high-level width t
SCK4 low-level wid th t
SI4 setup time (to SCK4↑)t
SI4 hold time (from SCK4↑)t
Delay time from SCK4↓ to SO4 output t

KCY2

KH2

KL2

SIK2

KSI2

KSO2

<66> 400 ns
<67> 140 ns
<68> 140 ns
<69> 50 ns
<70> 50 ns
<71> 60 ns

<66>

SCK4 (I/O)

SI4 (input)

SO4 (output)

<67>

<68>

<69> <70>

<71>

34

Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

UART Timing (TA = –40 to +85°C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

Parameter Symbol Conditions MIN. MAX. Unit
ASCKn cycle time t
ASCKn high-level width t
ASCKn low-level width t

Remark

n = 0, 1

ASCKn (input)

Remark n = 0, 1

KCY13

<72> 200 ns

KH13

<73> 80 ns

KL13

<74> 80 ns

<72>

<73> <74>

Preliminary Data Sheet U14622EJ1V0DS00

35

µµµµ

PD70F3040, 70F3040Y

I2C Bus Mode (Only for

A

=

(T

40 to +85

−−−−

C, VDD = AVDD = BVDD = 2.7 to 3.6 V, VSS = AVSS = BVSS = 0 V)

°°°°

PD70F3040Y)

µµµµ

Standard Mode High-Speed ModeParameter Symbol

MIN. MAX. MIN. MAX.
SCLn clock frequency f
Bus free time

CLK

BUF

t

<75> 4.7 – 1.3 –

0 100 0 400 kHz

(between stop/start conditions)
Hold time
SCLn clock low-level width t
SCLn clock high-level width t
Setup time of start/restart conditi ons t

time

Data setup time t
Rising time of SDAn and SCLn signals t
Falling time of SDAn and SCLn signals t
Setup time of stop condition t
Pulse width of spike suppressed by

Note 1

CBUS-compatible master 5.0 – – –

2

I

C mode

HD : STA

t

LOW

HIGH

SU : STA

HD : DAT

t

SU : DAT

R

F

SU : STO

SP

t

<76> 4.0 – 0.6 –
<77> 4.7 – 1.3 –
<78> 4.0 – 0.6 –
<79> 4.7 – 0.6 –
<80>

Note 2

0

–
<81> 250 –
<82> – 1000
<83> – 300

Note 2

0

Note 4

100
20 + 0.1Cb
20 + 0.1Cb

<84> 4.0 – 0.6 –
<85> – – 0 50 ns

Note 5

Note 5

Note 3

0.9
–ns

300 ns
300 ns

input filter
Load capacitance of bus line Cb – 400 – 400 pF

Unit

µ

µ
µ
µ
µ
µ
µ

µ

s

s
s
s
s
sData hold
s

s

Notes 1.

Remark

The first clock pulse in the start condition is generated after the hold time.
The system must internally provide at least 300-ns hold time for the SDAn signal (at V

2.

signal) in order to fill the undefined period that appears at the SCLn falling edge.

LOW

If the system does not extend the low hold time (t

3.

hold time (tHD:
The high-speed I

4.

DAT

).

2

C bus is available in the standard mode I2C bus system. In this case, following

), it is required to satisfy only the maximum data

conditions should be satisf ied.

When the system does not extend the low-state hold time of the SCLn signal

•

SU: DAT

≥ 250 ns

t
When the system extends the low-state hold time of the SCLn signal

•

Before the SCLn line is released (t

Rmax.

+ tSU:

DAT

= 1000 + 250 = 1250 ns: Standard mode I2C bus

specification), send the next data bit to the SDAn line.

Cb: Total capacitance of one bus line (Unit: pF)

5.

n = 0, 1

IHmin.

of the SCLn

36

Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

I2C Bus Mode (

SCLn

SDAn

Remark

A/D Converter (T

PD70F3040Y only)

µµµµ

<76>

<75>

Stop
condition

Strat
condition

n = 0, 1

A

= –40 to +85°C, VDD = AVDD = AV

Capacitance: CL = 50 pF)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

<77>

<82>

<80>

<78>

<83>

<79>

<81>

<76>

Restart condition

REF

= 2.7 to 3.6 V, AVSS = VSS = 0 V, Output Pin Load

<85> <84>

Stop condition

Resolution 10 10 10 bit
Overall error
Conversion time t
Zero-scale error
Full-scale error
Integral linearity error
Differential linearity error
Analog reference voltage AV
Analog input voltage V

REF

AV
Supply current AI

Notes 1.

Remark

Note 1

CONV

Note 1

Note 1

Note 2

Note 2

REF

IAN

current AI

REF

DD

Excluding quantization error (±0.05%FSR)
Excluding quantization error (±0.5LSB)

2.

LSB: Least Significant Bit

AV

REF

= AV

0.8 %FSR

±

5 100

0.4 %FSR

±

0.4 %FSR

±

4.0 LSB

±

4.0 LSB

±

DD

2.7 3.6 V

SS

AV

AV

240 360

µ

REF

µ

13mA

FSR: Full Scale Range

s

V

A

Preliminary Data Sheet U14622EJ1V0DS00

37

Flash Memory Programming Mode

A

Write/Erase Characteristics (T

Parameter Symbol Conditions MIN. TYP. MAX. Unit

= 10 to 40

C, VDD = 3.0 to 3.6 V)

°°°°

µµµµ

PD70F3040, 70F3040Y

Unit erase time t
Total erase time t
Rewrite count

Note

I
I
I

V
V

DDW

PPW

DDE

PPE

I

ERT

ER

When VPP = V

When VPP = V

PP0

In normal operation mode 0 0.2V

PP1

In flash memory programming mode 7. 5 7. 8 8.1 V

PP1

PP1

VDD pin 67 mAWrite current
VPP pin 100 mA
VDD pin 67 mAErase current
VPP pin 200 mA

0.2 0.2 0.2 s
20 s

20 20 20 times

DD

Operation frequency 4 16 MHz

Write/erase is regarded as 1 cycle.

Note

VVPP supply voltage

38

Preliminary Data Sheet U14622EJ1V0DS00

3. PACKAGE DRAWING

176-PIN PLASTIC LQFP (FINE PITCH) (24x24)

A

B

132 89

133

88

µµµµ

PD70F3040, 70F3040Y

detail of lead end

S

P

176

144

45

F
G

NOTE

Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.

H

M

I

S

N

J

M

C D

K

T

R

L
U

Q

S

ITEM MILLIMETERS

A

26.0±0.2

B

24.0±0.2
C 24.0±0.2
D

26.0±0.2

F 1.25

G

1.25
H 0.22±0.05

I

0.08

J

0.5 (T.P.)
K

1.0±0.2

L

0.5
M 0.17

N
P
Q

R3°
S

+0.03

−0.07

0.08

1.4

0.1±0.05

+4°

−3°

1.5±0.1

S176GM-50-UEU

Preliminary Data Sheet U14622EJ1V0DS00

39

4. RECOMMENDED SOLDERING CONDITIONS

T.B.D.

µµµµ

PD70F3040, 70F3040Y

40

Preliminary Data Sheet U14622EJ1V0DS00

[MEMO]

µµµµ

PD70F3040, 70F3040Y

Preliminary Data Sheet U14622EJ1V0DS00

41

µµµµ

PD70F3040, 70F3040Y

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

DD

pin should be connected to V
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.

or GND with a resistor, if it is considered to have a possibility of

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C
system, provided that the system conf orms to the I

Related document

Reference document

This document number is that of the Japanese version.

Note

PD703039, 703039Y, 703040, 703040Y, 703041, 703041Y Data Sheet (U13953E)

µ

Electrical Characteristics for Microcomputer (IEI-601)

2

C Standard Specification as defined by Philips.

Note

The documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.

V850 Family and V850/SV1 are trademarks of NEC Corporation.

42

Preliminary Data Sheet U14622EJ1V0DS00

µµµµ

PD70F3040, 70F3040Y

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: [phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: [phone]
Fax: [phone]

J99.1

Preliminary Data Sheet U14622EJ1V0DS00

43

µµµµ

PD70F3040, 70F3040Y

• The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M5 98. 8