Datasheet UPD70433R-12, UPD70433R-16, UPD70433GJ-16-3EB, UPD70433GJ-12-3EB, UPD70433GD-16-5BB Datasheet (NEC)

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Page 1

DATA SHEET

MOS INTEGRATED CIRCUIT

PD70433

V55PI

16-BIT MICROPROCESSOR

DESCRIPTION

The µPD70433 (V55PI) is a microprocessor in which a 16-bit CPU, RAM, serial interface, parallel interface, A/D

converter, timers, DMA controller, interrupt controller, etc., are integrated in a single chip.

The V55PI is software-compatible with the µPD70320 and 70330 (V25TM and V35TM) single-chip microcontrollers. The V55PI provides a migration path from the V25. It offers higher-level functions and higher performance, and is particularly suitable for control of data processing systems associated with mechanical control, including printer and facsimile.

Detailed functions are described in the following user’s manuals, which should be read when carrying out design work.

• V55PI User’s Manual Hardware : U10514E

• V55PI User’s Manual Instruction : U10231E

FEATURES

• Internal 16-bit architecture, selectable external data bus width (16/8 bits)

• Software compatible with V20

• Minimum instruction cycle: 160 ns/12.5 MHz (external 25 MHz)

• Address space: 16M bytes: 1-Mbyte basic memory space

• Register file space (in on-chip RAM) : 512 bytes/16 register banks

• I/O space : 64K bytes

• Automatic wait control with memory space divided in variable sizes (max. 6 blocks)

• I/O line (input ports: 11 bits, input/output ports: 42 bits)

• DMA controller (DMAC): Max. 4-channel configuration possible

• Four DMA transfer modes (single transfer, demand release, single step, burst)

• Intelligent DMA modes 1 and 2

• Serial interface: 2 channels

• Asynchronous mode (UART) or clocked mode (CSI) selectable

• Parallel interface: 8 bits

• Centronics data input/output and general-purpose data input/output

• A/D converter (8 bits): 4 channels

• Real-time output port: 4 bits × 2 channels or 8 bits × 1 channel

• PMW (Pulse Width Modulation) output function : 8 bits

and V30TM (native mode) and V25 and V35 (includes additional instructions)

125 ns/16 MHz (external 32 MHz)

16-Mbyte extended memory space

Document No. U11775EJ4V0DS00 (4th edition) Previous No. IC-8257 Date Published November 1996 P Printed in Japan

The information in this document is subject to change without notice.

The mark shows major revised points.

1995

Page 2

• Interrupt controller

• Programmable priority (4 levels)

• Three interrupt servicing methods Vectored interrupt function, register bank switching function, macro service function

• 16-bit timer: 4 channels

• Watchdog timer function

• Software interval timer (16 bits)

• Address field wait insertion function and RAS/CAS switchover timing generation function

• DRAM and pseudo-SRAM refresh functions

• Standby functions (STOP mode, HALT mode)

• On-chip clock generator

APPLICATIONS

• Control of data processing systems using serial or parallel communication (Data processing terminals, printer, G3 facsimile, etc.)

ORDERING INFORMATION

PD70433

Part Number Package

PD70433GD-12-5BB 120-pin plastic QFP (28 × 28 mm) 12.5

PD70433GD-16-5BB 120-pin plastic QFP (28 × 28 mm) 16

PD70433R-12 132-pin ceramic PGA 12.5

PD70433R-16 132-pin ceramic PGA 16

PD70433GJ-12-3EB 120-pin plastic QFP (fine pitch) (20 × 20 mm) 12.5

PD70433GJ-16-3EB 120-pin plastic QFP (fine pitch) (20 × 20 mm) 16

Maximum Operating

Frequency (MHz)

Page 3

PIN CONFIGURATION (TOP VIEW)

(1) 120-Pin Plastic QFP (28 × 28 mm), 120-pin plastic QFP (fine pitch) (20 × 20 mm)

PD70433GD-xx-5BB

PD70433GJ-xx-3EB

OPEN

DEX

RAS

IORD

IOWRRDWRL

WRH

ASTB

IC (L)

D8/D16

GND

VDDA23

A22

A21

A20

A19

A18

A17

A16

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

PD70433

BUSLOCK

HLDAK HLDRQ READY

POLL

CLKOUT

RESET

WDTOUT

X1 X2

GND

REFRQ

P00 P01 P02 P03 P04 P05 P06 P07

GND

P10/NMI P11/INTP0 P12/INTP1 P13/INTP2

P14/INTP3/TI

P15/INTP4 P16/INTP5

119

117

115

113

111

109

107

105

103

120

118

116

114

112

110

108

106

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

313233343536373839404142434445464748495051525354555657585960

104

101

102

1009998979695949392

90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

AD6 AD5 AD4 AD3 AD2 AD1 AD0 IC (H) GND V

TCE1 TCE0 DMAAK1 DMAAK0 P81/DMARQ1 P80/DMARQ0 V

P77/RTPT7 P76/RTPT6 P75/RTPT5 P74/RTPT4 P73/RTPT3 P72/RTPT2 P71/RTPT1 P70/RTPT0 GND AV

REF

P63/ANI3 P62/ANI2

P51/ACK

P52/BUSY

P50/DATASTB

P60/ANI0

P61/ANI1

P20/PWM

P21/TO00

P22/TO01

P23/TO20

P24/TO21

P25/TO30

C/SCK0

P33/CTS0

D0/SB1/SI0

D0/SB0/SO0

P32/T

P31/R

P30/T

D1/SI1

D1/SO1

P35/R

P34/T

P36/SCK1/CTS1

P40/PD0

P41/PD1

P42/PD2

P43/PD3

P44/PD4

P45/PD5

GND

P46/PD6

P47/PD7

Remark IC: Internally Connected

Notes 1. The IC (H) pin should be connected to VDD with an external resistor (1 to 10 kΩ).

2. The IC (L) pin should be connected to GND with an external resistor (1 to 10 k

Ω).

3. No connection should be made to the OPEN pin.

Page 4

(2) 132-Pin Ceramic PGA

PD70433R-xx

Bottom View

Locator Pin

PD70433

Top View

14 13 12 11

9 8 7 6 5

4 3

2 1

ABCDEFGHJKLMNP

Index Mark

PNMLKJHGFEDCBA

Remark The locator pin is not included in the pin count.

No. Signal Nane Port No. Signal Name Port No. Signal Name Port

A1 ANI1 P61 B5 PD7 P47 C9 CTS0 P33

A2 AVSS –– B6 PD5 P45 C10 TO30 P25

A3 ACK P51 B7 PD2 P42 C11 TO00 P21

A4 DATASTB P50 B8 PD0 P40 C12 NC ––

A5 PD6 P46 B9 RXD1/SI1 P35 C13 INTP4 P15

A6 PD4 P44 B10 RXD0/SB1/SI0 P31 C14 INTP0 P11

A7 PD1 P41 B11 TO21 P24 D1 RTPT2 P72

A8 NC –– B12 TO01 P22 D2 GND ––

A9 SCK1/CTS1 P36 B13 NC –– D3 ANI3 P63

A10 TXD1/SO1 P34 B14 INTP3/TI P14 D12 INTP5 P16

A11 TXC/SCK0 P32 C1 RTPT1 P71 D13 INTP2 P13

A12 TXD0/SB0/SO0 P30 C2 AVREF –– D14 NMI P10

A13 TO20 P23 C3 NC –– E1 RTPT5 P75

A14 PWM P20 C4 NC –– E2 RTPT3 P73

B1 AVDD –– C5 VDD –– E3 RTPT0 P70

B2 ANI2 P62 C6 GND –– E12 INTP1 P12

B3 ANI0 P60 C7 PD3 P43 E13 GND ––

B4 BUSY P52 C8 VDD –– E14 –– P06

Page 5

No. Signal Nane Port No. Signal Name Port No. Signal Name Port

F1 RTPT7 P77 K3 AD2 ––– N3 AD9 –––

F2 RTPT6 P76 K12 POLL ––– N4 AD11 –––

F3 RTPT4 P74 K13 WDTOUT ––– N5 AD14 –––

F12 ––– P07 K14 X1 ––– N6 A18 –––

F13 ––– P05 L1 AD0 ––– N7 A21 –––

F14 ––– P04 L2 AD3 ––– N8 A23 –––

G1 NC ––– L3 AD6 ––– N9 D8/D16 –––

G2 DMARQ0 P80 L12 BUSLOCK ––– N10 ASTB –––

G3 VDD ––– L13 READY ––– N11 IOWR –––

G12 ––– P03 L14 RESET ––– N12 DEX –––

G13 ––– P02 M1 AD1 ––– N13 VDD –––

G14 ––– P01 M2 AD5 ––– N14 HLDRQ –––

PD70433

H1 DMARQ1 P81 M3 NC ––– P1 AD7 –––

H2 DMAAK0 ––– M4 AD8 ––– P2 AD10 –––

H3 DMAAK1 ––– M5 AD12 ––– P3 AD13 –––

H12 REFRQ ––– M6 A16 ––– P4 AD15 –––

H13 ––– P00 M7 A20 ––– P5 A17 –––

H14 NC ––– M8 V DD ––– P6 A19 –––

J1 TCE0 ––– M9 WRH ––– P7 NC –––

J2 TCE1 ––– M10 IORD ––– P8 A22 –––

J3 GND ––– M11 NC ––– P9 GND –––

J12 VDD ––– M12 NC ––– P10 IC (L) –––

J13 X2 ––– M13 HLDAK ––– P11 WRL –––

J14 GND ––– M14 CLKOUT ––– P12 RD –––

K1 VDD ––– N1 AD4 ––– P13 RAS –––

K2 IC (H) ––– N2 NC ––– P14 OPEN –––

Remark IC: Internally Connected

NC: Non-Connection

Notes 1. The IC (H) pin should be connected to V

2. The IC (L) pin should be connected to GND with an external resistor (1 to 10 k

3. No connection should be made to the OPEN pin.

DD with an external resistor (1 to 10 kΩ).

Ω).

Page 6

D0/SB0/SO0

GND

GENERAL

REGISTERS

DATA MEMORY

512 BYTES

ALU

EXU

D0/SB1/SI0

C/SCK0

CTS0

D1/SI1

CTS1/SCK1

D1/SO1

PD0–PD7

DATASTB

ACK

BUSY

ANI0–ANI3

REF

INTERNAL BLOCK DIAGRAM

ASTB READY RD WRH WRL

IORD IOWR

RAS DEX D8/D16 BUSLOCK POLL HLDRQ

HLDAK REFRQ

A16–A23 AD0–AD15

DMARQ0 DMAAK0 TCE0 DMARQ1

DMAAK1 TCE1

MICRO SEQUENCE

CONTROL

MICRO ROM

BCU

PREFETCH

QUEUE

6 BYTES

BUS

CONTROL

PREFETCH

CONTROL

DMAC

DMA request

PWM UNIT

• PWM

• TO00

• TO20

• TO03

TIMER/

COUNTER

UNIT

WDT

• WDTOUT

• TO01

• TO21

PIUUART/CSIUART/CSI

PROGRAMMABLE

INTERRUPT

CONTROLLER

• INTP0

• INTP1

• INTP2

• INTP3/TI

• INTP4

• INTP5

NMI

8-BIT A/D

PORT7

PORT8

SYSTEM CONTROL

PORT RTOP

PORT0

PORT1

PORT2

PORT3

PORT4

PORT5

PORT6

RTP4–RTP7

RESET CLKOUT

44876783482

RTP0–RTP3

PD70433

Page 7

PD70433

CONTENTS

1. PIN FUNCTIONS ....................................................................................................................................... 1 0

1.1 LIST OF PIN FUNCTION .................................................................................................................................... 10

1.1.1 Port Pins ................................................................................................................................................ 10

1.1.2 Non-Port Pins........................................................................................................................................11

2. BLOCK CONFIGURATION....................................................................................................................... 14

2.1 BUS CONTROL UNIT (BCU) ............................................................................................................................. 14

2.2 EXECUTION UNIT (EXU)...................................................................................................................................14

2.3 INTERRUPT CONTROLLER (INTC) .................................................................................................................1 4

2.4 DMA CONTROLLER (DMAC) ........................................................................................................................... 14

2.5 UART/CLOCKED SERIAL INTERFACE (UART/CSI)......................................................................................1 4

2.6 PARALLEL INTERFACE UNIT (PIU)................................................................................................................14

2.7 A/D CONVERTER UNIT (8-BIT A/D) ................................................................................................................ 14

2.8 TIMER/COUNTER UNIT (TCU) .........................................................................................................................14

2.9 PWM (PULSE WIDTH MODULATION) UNIT (PWM).......................................................................................14

2.10 WATCHDOG TIMER (WDT) ..............................................................................................................................14

2.11 PORTS (PORT)................................................................................................................................................... 14

2.12 REAL-TIME OUTPUT PORT (RTOP)................................................................................................................ 14

2.13 CLOCK GENERATOR (CG) .............................................................................................................................. 15

2.14 SOFTWARE INTERVAL TIMER (SIT) ..............................................................................................................15

3. CPU FUNCTIONS....................................................................................................................................... 16

3.1 FEATURES .......................................................................................................................................................... 16

3.2 REGISTERS .........................................................................................................................................................17

3.2.1 Register Banks ...................................................................................................................................... 17

3.2.2 General Registers (AW, BW, CW, DW) .............................................................................................. 19

3.2.3 Pointers (SP, BP) and Index Registers (IX, IY) ................................................................................. 20

3.2.4 Segment Registers (PS, SS, DS0, DS1) ............................................................................................. 20

3.2.5 Extended Segment Registers (DS2, DS3) .........................................................................................21

3.2.6 Special Function Registers (SFR)......................................................................................................22

3.3 PROGRAM COUNTER (PC) ..............................................................................................................................23

3.4 PROGRAM STATUS WORDS (PSW) ...............................................................................................................23

3.5 MEMORY SPACE ...............................................................................................................................................2 4

3.5.1 Basic Memory Space ...........................................................................................................................24

3.5.2 Extended Memory Space..................................................................................................................... 25

3.5.3 Special Function Register Area .......................................................................................................... 26

3.5.4 Vector Table Area.................................................................................................................................34

3.6 REGISTER FILE SPACE ..................................................................................................................................... 36

3.7 I/O SPACE .......................................................................................................................................................... 38

4. BUS CONTROL FUNCTIONS ....................................................................................................................39

4.1 WAIT FUNCTION ............................................................................................................................................... 39

4.2 REFRESH FUNCTION ........................................................................................................................................ 41

4.2.1 Refresh Mode Register (RFM) ............................................................................................................. 41

4.2.2 Wait Control in Refresh Cycle ............................................................................................................41

4.2.3 Refresh Address ...................................................................................................................................4 1

Page 8

PD70433

5. INTERRUPT FUNCTIONS ......................................................................................................................... 42

5.1 FEATURES .........................................................................................................................................................42

5.2 INTERRUPT RESPONSE METHODS ...............................................................................................................45

5.2.1 Vectored Interrupts ..............................................................................................................................4 5

5.2.2 Register Bank Switching Function ....................................................................................................4 6

5.2.3 Macro Service Function....................................................................................................................... 47

6. DMA FUNCTION (DMA CONTROLLER) .................................................................................................. 48

6.1 FEATURES .......................................................................................................................................................... 48

7. SERIAL INTERFACE FUNCTIONS ...........................................................................................................50

7.1 FEATURES .......................................................................................................................................................... 50

7.2 PROTOCOLS .......................................................................................................................................................50

7.3 UART ...................................................................................................................................................................51

7.3.1 Features ................................................................................................................................................. 51

7.4 CLOCKED SERIAL INTERFACE (CSI) ............................................................................................................... 52

7.4.1 Features ................................................................................................................................................. 52

8. PARALLEL INTERFACE FUNCTIONS..................................................................................................... 5 3

8.1 FEATURES .......................................................................................................................................................... 53

9. TIMER FUNCTION ..................................................................................................................................... 55

9.1 FEATURES ..........................................................................................................................................................55

9.2 TIMER UNIT CONFIGURATION ....................................................................................................................... 55

9.3 REAL-TIME OUTPUT PORT FUNCTION .......................................................................................................... 57

9.3.1 Real-Time Output Port Configuration................................................................................................ 57

9.3.2 Real-Time Output Port Operation ...................................................................................................... 59

10. PWM UNIT .................................................................................................................................................. 61

10.1 FEATURES ..........................................................................................................................................................61

10.2 PWM UNIT CONFIGURATION ......................................................................................................................... 61

11. WATCHDOG TIMER FUNCTION ..............................................................................................................6 3

11.1 FEATURES ..........................................................................................................................................................63

11.2 WATCHDOG TIMER CONFIGURATION AND OPERATION .......................................................................... 63

12. A/D CONVERTER FUNCTION ..................................................................................................................64

12.1 FEATURES ..........................................................................................................................................................64

13. STANDBY FUNCTION ...............................................................................................................................66

13.1 HALT MODE ....................................................................................................................................................... 66

13.2 STOP MODE .......................................................................................................................................................67

14. CLOCK GENERATOR ...............................................................................................................................68

14.1 CLOCK GENERATOR CONFIGURATION AND OPERATION......................................................................... 68

Page 9

PD70433

15. SOFTWARE INTERVAL TIMER FUNCTION........................................................................................... 7 0

15.1 SOFTWARE INTERVAL TIMER CONFIGURATION ........................................................................................ 70

16. CODEC INSTRUCTION..............................................................................................................................71

16.1 FEATURES ..........................................................................................................................................................71

16.2 MEMORY MAP................................................................................................................................................... 74

16.3 PROCESSING FLOW ......................................................................................................................................... 76

17. INSTRUCTION SET.................................................................................................................................... 78

17.1 INSTRUCTIONS NEWLY ADDED TO V20/V30 AND V25/V35..................................................................... 78

17.2 INSTRUCTION SET OPERATIONS................................................................................................................... 80

17.3 INSTRUCTION SET TABLE ............................................................................................................................. 105

18. ELECTRICAL SPECIFICATIONS ............................................................................................................1 28

19. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ................................................................... 158

20. PACKAGE DRAWINGS ...........................................................................................................................159

21. RECOMMENDED SOLDERING CONDITIONS ...................................................................................... 162

Page 10

PD70433

1. PIN FUNCTIONS

1.1 LIST OF PIN FUNCTIONS

1.1.1 Port Pins

Pin Name Input/Output Function Alternate Function

Port 0

P00 to P07 Input/output

P10* NMI P11 INTP0 P12 INTP1 P13 INTP2 P14 INTP3/TI P15 INTP4 P16 INTP5 P20 PWM P21 TO00 P22 TO01 P23 TO20 P24 TO21 P25 TO30 P30 TxD0/SB0/SO0 P31 RxD0/SB1/SI0 P32 TxC/SCK0 P33 CTS0 P34 TxD1/SO1 P35 RxD1/SI1 P36 CTS1/SCK1

P40 to P47 PD0 to PD7

Input

Input/output

Input/output specifiable bit-wise 8-bit input/output port

Port 1 7-bit input port

Port 2 Input/output specifiable bit-wise 6-bit input/output port

Port 3 Input/output specifiable bit-wise 7-bit input/output port

Port 4 Input/output specifiable bit-wise 8-bit input/output port

P50 DATASTB P51 ACK P52 BUSY

P60 to P63 ANI0 to ANI3

P70 to P77 RTP0 to RTP7

P80 DMARQ0 P81 DMARQ1

Input

Input/output

Port 5 Input/output specifiable bit-wise 3-bit input/output port

Port 6 Input/output specifiable bit-wise 4-bit input/output port

Port 7 Input/output specifiable bit-wise 8-bit input/output port

Port 8 Input/output specifiable bit-wise 2-bit input/output port

* Unusable as general-purpose port (non-maskable interrupt)

Page 11

1.1.2 Non-Port Pins

(1) Bus control pins

PD70433

Pin Name Function

ASTB External bus cycle address strobe signal output in external bus

WRL

WRH

READY Input External bus cycle ready signal input in external bus

DEX External bus cycle upper byte data enable signal output

RAS DRAM low address latch timing signal output

D8/D16 Input External bus data bus width selection signal input

BUSLOCK Output External bus bus lock signal output

POLL Input of POLL signal (sampled in POLL instruction execution)

HLDRQ External bus hold request signal input

HLDAK External bus hold acknowledge signal output

REFRQ Refresh pulse signal output

Input/ Alternate

Output Function

External memory cycle data read strobe signal output in external bus

Output

Input

Output

External memory cycle lower byte data write strobe signal output in external bus

External memory cycle upper byte data write strobe signal output in external bus

–––

AD0 to AD15

A16 to A23 External bus cycle address signal output in external bus

IORD External I/O cycle data read strobe signal output

IOWR External I/O cycle data write strobe signal output

DMARQ0 DMA request signal input (channel 0) P80

DMARQ1 DMA request signal input (channel 1) P81

DMAAK0 DMA acknowledge signal output (channel 0)

DMAAK1 DMA acknowledge signal output (channel 1)

TCE0 DMA termination signal output (channel 0)

TCE1 DMA termination signal output (channel 1)

3–state External bus cycle address/data multiplex signal input/output

input/output in external bus

3–state

output

Output

Input

Output –––

Page 12

(2) Other pins

PD70433

Pin Name Function

GND GND potential

VDD Positive power supply

AVSS A/D converter GND potential

AVDD A/D converter analog power supply

AVREF A/D converter reference voltage input

RESET Input System reset signal input

X1 Connection pins of crystal resonator/ceramic resonator for

X2 ––– to X1 and leave X2 open.

CLKOUT Internal system clock ø output

WDTOUT Watchdog timer overflow signal output

NMI Non-maskable interrupt request input *1 P10

INTP0 P11

INTP1 P12

Input/ Alternate

Output Function

–––

system clock generation. In case of external clock supply, input

Output

–––

INTP2 P13

INTP3 P14/TI

INTP4 P15

INTP5 P16

TI External event clock input P14/INTP3

PWM PWM output P20

TO00, TO01, TO20, TO21, TO30

TXD0 UART transmission data output P30/SB0/SO0

RXD0 Input UART reception data input P31/SB1/SI0

TXC Output UART transmission clock output P32/SCK0

CTS0 P33

CTS1 P36/SCK1

SB0 P30/TXD0/SO0

SB1 P31/RXD0/SI0

Input External interrupt request input *2

Output Timer unit output P21 to P25

Input UART transmission enable signal input

Input/output SBI transmission/reception data input/output

*1.Because NMI interrupt is unmaskable, NMI interrupt is always initiated by detecting a valid edge (when reading from

port 1, the pin level is read).

2. By masking or disabling (IE = 0) these interrupts, these pins can be used as general–purpose input/output ports, respectively.

Page 13

PD70433

Pin Name Function

SO0 P30/TXD0/SB0

SO1 P34/TXD1

SI0 P31/RXD0/SB1

SI1 P35/RXD1

SCK0 P32/TXC

SCK1 P36/CTS1

PD0 to PD7 Parallel interface — Data input/output P40 to P47

DATASTB Parallel interface — Data strobe signal P50

ACK Parallel interface — Acknowledge signal P51

BUSY Parallel interface — Busy signal P52

ANI0 to ANI3 Input Analog input signal to A/D converter P60 to P63

RTP0 to RTP7 Output Real-time output port P70 to P77

Input/ Alternate

Output Function

Output CSI transmission data output

Input CSI reception data input

CSI serial clock input/output

Input/output

Page 14

PD70433

2. BLOCK CONFIGURATION

2.1 BUS CONTROL UNIT (BCU)

The BCU performs control of the main bus. The BCU starts the necessary internal/external bus cycle on the basis of

the physical address obtained from the execution unit (EXU).

2.2 EXECUTION UNIT (EXU)

The EXU controls address calculation, arithmetic and logical operations, data transfer, etc., by means of a microprogram (firmware for controlling the microsequencer on the basis of decoded op code). The EXU contains 512 bytes of RAM (corresponding to the register file space).

2.3 INTERRUPT CONTROLLER (INTC)

The INTC services hardware interrupt requests generated by on-chip peripheral hardware and interrupt requests generated externally with vectored interrupts, bank switching, or macro service. It can also control the programmable 4level interrupt priority order, and can also perform multiprocessing control for interrupt.

2.4 DMA CONTROLLER (DMAC)

The DMAC is a general-purpose DMA controller, capable of handling the 16M-byte memory space in a linear fashion. Operating modes comprise memory-to-memory transfer mode, intelligent DMA (ring buffer method and counter control method) mode, next address specification mode, and 2-channel operation.

2.5 UART/CLOCKED SERIAL INTERFACE (UART/CSI)

This block supports the asynchronous interface (UART) in which data synchronization is achieved by means of start/ stop bits, and the clocked serial interface (CSI), allowing either to be used.

For the clocked serial interface there is a further choice of serial bus interface mode (SBI) or 3-wire serial I/O mode.

2.6 PARALLEL INTERFACE UNIT (PIU)

This performs input/output using strobe signal synchronization in 8-bit units, and supports the Centronics interface and general-purpose parallel data communication functions.

2.7 A/D CONVERTER UNIT (8-BIT A/D)

This is an A/D converter with 4 analog inputs, and provided with 4 A/D conversion result registers.

2.8 TIMER/COUNTER UNIT (TCU)

The timer/counter unit incorporates a 16-bit timer/counter, and can be used as an interval timer, free-running counter, or event counter.

2.9 PWM (PULSE WIDTH MODULATION) UNIT (PWM)

An 8-bit precision PWM (pulse width modulation) signal output function.

2.10 WATCHDOG TIMER (WDT)

The WDT incorporates an 8-bit watchdog timer for detection of inadvertent program looping, system errors, etc. The WDTOUT pin is provided to give external notification of the generation of watchdog timer interrupts.

2.11 PORTS (PORT)

53 port pins are provided, allowing port pin and control pin functions to be selected.

2.12 REAL-TIME OUTPUT PORT (RTOP)

This is a real-time output port which uses an interrupt from timer 0 as a trigger. It can output the contents of the 8-bit buffer register at programmable intervals in 4-bit or 8-bit units.

Page 15

PD70433

2.13 CLOCK GENERATOR (CG)

The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1 and X2 pins and supplies it as the CPU operating clock.

2.14 SOFTWARE INTERVAL TIMER (SIT)

The SIT incorporates a 16-bit software interval timer as a software timer function and watch function timer. Interval interrupts can be set by input clock (count clock) selection and software timer/counter compare register setting.

Page 16

PD70433

3. CPU FUNCTIONS

The CPU of the V55PI is software upword compatible with the V20 and V30 (native mode), and the V25 and V35.

3.1 FEATURES

• Software upward compatible with V20 & V30 (native mode) and V25 & V35 (includes additional instructions)

• Minimum instruction cycle: 160 ns/12.5 MHz (external 25 MHz clock)

125 ns/16 MHz (external 32 MHz clock)

• Address space: 16M bytes 1M-byte basic memory (program) space 16M-byte extended memory (data) space

• Register file space (in on-chip RAM): 512 bytes/16 register banks

• I/O space: 64K bytes

• Register configuration (compared with V20/V30 and V25/V35)

Item V20, V30 V25, V35 V55PI

Extended segment register None None DS2, DS3

Mode flag MD None None

PSW

Special function register area None (memory mapping onto (memory mapping onto

Input/output instruction trap flag

User flag None F0, F1 None

None IBRK IBRK

240 bytes 496 bytes

FFF00H to FFFEFH) FFE00H to FFFEFH)

• Internal 16-bit architecture, switchable external data bus width (16/8 bits)

• Automatic wait control with memory divided in variable sizes (max. 6 blocks)

• Programmable wait function

• Wait function using READY pin

• Refresh function

• Automatic generation of refresh cycle (RAS only)

• RAS pin functions

RAS pin → DRAM RAS timing RD, WRH, WRL pins → DRAM CAS timing ASTB pin → DRAM row/column address switching timing

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3.2 REGISTERS

The V55PI CPU has general register sets compatible with the V20 and V30 (native mode), and the V25 and V35. The general register sets are mapped onto the register file space. These general register sets are also used as on-chip RAM, and there can be a maximum of 16 register sets in bank form.

In addition, the V55PI has various special function registers for controlling on-chip peripheral hardware. These special function registers are mapped onto memory space addresses 0FFE00H to 0FFFEFH.

3.2.1 Register Banks

The general register sets are mapped onto the register file space (in on-chip RAM). The general register sets are used in a bank arrangement; each bank consists of 32 bytes and up to 16 banks can be set.

The CPU normally uses register bank 15 for program execution, and it is possible to switch to another bank automatically by means of maskable hardware interrupt or software interrupt (BRKCS instruction). It is possible to return from the switchedto register bank to the original register bank by means of the instruction for returning from an interrupt (RETRBI).

The register bank configuration is shown in Figure 3-1. The general register sets are mapped onto the area with an offset of (+08H) to (+1FH) from the start address of each register bank. The word address from the start in a register bank is the extended segment register (DS2) area. The vector PC/DS3 area is used to set the value to be loaded into the PC when the register bank is switched, that is, the offset value of the start address of the interrupt service routine. This area is also used as the extended segment register (DS3) area. The PSW save area is used to save the PSW when the register bank is switched, and the PC save area is used to save the PC when the register bank is switched.

After a reset, register bank 15 is selected automatically. Also, segment register initialization after a reset is performed for register bank 15 only.

The register file space onto which these general register sets are mapped can also be accessed as data memory by addition of a special prefix instruction (IRAM:) to a memory manipulation instruction.

Of the 16 set register banks, banks 0 and 1 have macro service channels (parameter and work area for macro service) allocated in duplicate.

Page 18

000H

020H

040H

060H

080H

0A0H

0C0H

0E0H

100H

120H

140H

160H

180H

1A0H

1C0H

1E0H

1FFH

Figure 3-1. Register Bank Configuration

+00H 15 87 0

+02H

+04H

+06H

+08H

+0AH

+0CH

+0EH

+10H

+12H

+14H

+16H

+18H

+1AH

+1CH

+1EH

DS2

Vector PC/DS3

PSW Save

PC Save

DS0

DS1

PD70433

(Offset from the starting address of each register bank)

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PD70433

3.2.2 General Registers (AW, BW, CW, DW)

There are four 16-bit general registers. In addition to being accessed as 16-bit registers, these registers can also be accessed as 8-bit registers by dividing each register into upper and lower 8-bit halves (AH, AL, BH, BL, CH, CL, DH, DL).

These registers are used as 8-bit or 16-bit registers with a wide range of instructions including transfer, arithmetic and logical operation instructions.

Each register is also used as the default register for specific instruction processing, as shown below.

AW : Word multiplication/division, word input/output, data conversion AL : Byte multiplication/division, byte input/output, BCD rotation, data conversion AH : Byte multiplication/division BW : Data conversion CW : Loop control branch, repeat prefix CL : Shift instructions, rotate instructions, BCD operations DW : Word multiplication/division, indirect addressing input/output

These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number × 32).

Table 3-1. General Register Offsets

AW 1EH

BW 18H

CW 1CH

DW 1AH

AL 1EH

AH 1FH

BL 18H

BH 19H

CL 1CH

CH 1DH

DL 1AH

DH 1BH

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PD70433

3.2.3 Pointers (SP, BP) and Index Registers (IX, IY)

These are 16-bit registers used as base pointers or index registers in memory accesses using based addressing (BP), indexed addressing (IX, IY), based indexed addressing (BP, IX, IY), etc. The SP is also used as the pointer in stack operations. As with general registers, these are used with transfer instructions, arithmetic operation instructions, etc., but in this case they cannot be used as 8-bit registers. Each register is also used as the fixed address pointer for specific instruction processing, as shown below.

SP : Stack manipulation IX : Block transfers, BCD operation source side address specification IY : Block transfers, BCD operation destination side address specification

These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number × 32).

Table 3-2. Pointer and Index Register Offsets

SP 16H

BP 14H

IX 12H

IY 10H

3.2.4 Segment Registers (PS, SS, DS0, DS1)

The CPU manages the 1M-byte basic memory space by dividing it into 64K-byte units. The CPU specifies the start address of each segment with a segment register, and uses another register or effective address for the specification of phyiscal address, with the relative address from the start address as the offset.

The physical address is created as shown below.

Segment Register 4-Bit Fixed

xxxx0H

0xxxxH

.... Segment Start Address

.... Offset Value

xxxxxH

There are four segment registers: PS (Program Segment), SS (Stack Segment), DS0 (Data Segment 0), and DS1 (Data Segment 1). The respective segments are used in the following cases.

PS : Program fetch SS : Stack manipulation instructions, addressing using BP as base register DS0 : General variable accesses, source block data accesses such as block transfer instructions, etc. DS1 : Destination block data accesses such as block transfer instructions, etc.

..... Physical Address (20 Bits)

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However, using a segment override prefix instruction makes it possible for access of general variables to change from DS0 to another segment register. Also, in addressing which uses BP as the base register, another segment register can be used instead of SS.

Example MOV AW, 1000H

MOV DS1 : AW MOV BL, DS1, BYTE PTR [IX]; DSI : Byte data read from IX

When a reset is performed, PS of register bank 15 is initialized to FFFFH, and SS, DS0 and DS1 are initialized to 0000H.

These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number × 32).

Table 3-3. Segment Register Offsets

DS0 08H

DS1 0EH

SS 0AH

PS 0CH

3.2.5 Extended Segment Registers (DS2, DS3)

In addition to the segment registers for accessing the 1M-byte basic memory space, the V55PI is provided with extended segment registers which specify the start address of each 64K-byte segment of the 16M-byte extended memory space. There are two extended segment registers, DS2 (Data Segment 2) and DS3 (Data Segment 3), which are used as shown below.

DS2: Extended memory space general variable accesses (by segment override prefix instructions), source block

data accesses in extended memory space block transfer instructions, etc.

DS3: Extended memory space general variable accesses (by segment override prefix instructions), destination

block data accesses in extended memory space block transfer instructions, etc.

The data access using an extended semgnet register is performed by using the segment override prefix. Especially, in the block transfer instruction, DS2 and DS3 can be specified simultaneously by segment override prefix. (In this case, the order for DS2 and DS3 is optional.)

Example REP

DS2: DS3: MOVBKW ; Word memory block transfer from DS2 : IX to DS3 : IY.

The CPU specifies the start address of each segment with an extended segment register, and performs an access by using another register or effective address for the specification of physical address, with the relative address from the start address as the offset value.

The physical address is created as shown in the next page.

Page 22

Extended Segment Register 8-Bit Fixed

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xxxx00H

00xxxxH

xxxxxxH

When a reset is performed, DS2 and DS3 of register bank 15 are initialized to 0000H. These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number × 32).

Table 3-4. Extended Segment Register Offsets

... Segment Start Address

... Offset Value

... Physical Address (24 Bits)

DS2 00H DS3 02H (Also used as vectored PC)

3.2.6 Special Function Registers (SFR)

The V55PI has a group of registers with the function of controlling on-chip peripheral hardware.

A number of registers are provided according to the type of cotrol for each peripheral hardware unit, and the actual operation can be set using the individual bits in the registers. These registers are mapped onto the memory space, and are read and written to using the same method as for ordinary memory (see 3.5.3 "Special Function Register Area").

Example MOV AW, 0FFE0H

MOV DS1, AW MOV BL, DS1 : BYTE PTR [1EFH]; 0FFE0H : 1EFH (PRC register) Read

There are also two instructions, BTCLR and BTCLRL, which are only valid for special function registers. Of these, BTCLRL is an instruction newly provided in the V25 or V35.

The BTCLR instruction is valid for registers in the upper 240 bytes (0FFF00H to 0FFFEFH) of the special function register area, and the BTCLRL instruction is valid for registers in the lower 256 bytes (0FFE00H to 0FFEFFH).

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3.3 PROGRAM COUNTER (PC)

This is a 16-bit binary counter which holds the offset value of the program memory address on which the CPU is to perform execution.

The PC is incremented each time an instruction code is fetched from the instruction queue, and is also loaded with the new location address value when a branch, call, return or break instruction is executed.

When a reset is performed, 0000H is loaded into the PC. Because the PS register is initialized to FFFFH in a reset, after a reset the CPU begins execution at physical address 0FFFF0H.

3.4 PROGRAM STATUS WORDS (PSW)

The PSW consists of 6 status flags and 5 control flags.

• Status flags

•V (Overflow) ...Overflow detection flag

•S (Sign) ...Sign bit detection flag

•Z (Zero) ...All zero detection flag

•AC (Auxiliary Carry) ...4-bit carry/borrow detection flag

•P (Parity) ...Parity detection flag

•CY (Carry) ... Carry/borrow detection flag

• Control flags

•RB0 to RB3 (Register Banks 0 to 3) ...Register bankspecification flags

•DIR (Direction) ...Block transfer/input/output instruction direction control flag

•IE (Interrupt Enable) ...Interrupt enabled state control flag

•BRK (Break) ...Single-step interrupt control flag

•IBRK (I/O Break) ...Input/output instruction trap control flag

The status flags are set (1) or reset (0) automatically according to the result (data value) of execution of various kinds of instructions. The CY flag can be directly set, reset or inverted by an instruction.

The control flags are set or reset by instructions, and control the operation of the CPU. The IE and BRK flags are always reset when interrupt servicing is initiated.

The contents of the PSW can be saved to and restored from the stack by the PUSH and POP instructions. However, when the contents are restored by the POP PSW instruction, bits 12 to 15 (RB0 to RB3) are not returned to the PSW.

The low-order 8 bits of the PSW can also be saved to or restored from the AH register by an MOV instruction.

The PSW bit configuration is shown below.

151413121110987654 3210

RB3 RB2 RB1 RB0 Y DIR IE BRK S Z 0 AC 0 P IBRK CY

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3.5 MEMORY SPACE

The V55PI has a 16M-byte memory space. Of this, using lowest 1M bytes (000000H to 0FFFFFH) as the basic memory space, the 16M bytes including the basic memory space (000000H to FFFFFFH) can be accessed as the extended memory space. The basic memory space can be accessed using the segment registers (PS, SS, DS0, DS1) in the same way as in the V25 and V35. The extended memory space can be accessed using the extended segment registers (DS2, DS3), and has the basic memory space mapped onto the lowest 1M bytes. See 3.2.4 "Segment Registers (PS, SS, DS0, DS1)" and

3.2.5 "Extended Segment Registers (DS2, DS3)" for the physical addresses.

The 496-byte space 0FFE00H to 0FFFEFH has mapped onto it a group of registers to which specific functions are allocated such as on-chip peripheral hardware registers, control registers, etc., and these are manipulated by memory accesses.

In addition, independent of these, there is a 512-byte register file space (in on-chip RAM). In addition to being accessed by using register manipulation instructions as in the V25 and V35, the register file space can also be accessed as data memory by adding a special prefix instruction (IRAM:) to a memory manipulation in.

Figure 3-2. Memory Space

000000H

Vector Area

003FFH

Basic Memory

Space

(1M Bytes)

0FFFFFH

100000H

Special Function

(On-Chip Area)

FFFFFFH

FFE00H FFFEFH

Extended Memory Space (16M Bytes)

3.5.1 Basic Memory Space

The memory space comprises a 1M-byte basic memory space and 16M-byte extended memory space. The basic memory space is mapped onto the lowest 1M bytes (000000H to 0FFFFFH) of the extended memory space.

The 1M-byte basic memory space is shown in Figure 3-3.

Conditions for accessing the basic memory space by software are the same as for the V20/V30 and V25/V35.

A basic memory space physical address is specified by the segment start address indicated by the segment register (PS, SS, DS0, DS1) and the offset value from the segment start position indicated by another register or immediate data.

The basic memory space has the vectored interrupt vector area and special function register area mapped onto it. For an area in which special function registers are mapped, data accesses cannot be made to external memory (program fetches are possible.)

Page 25

Figure 3-3. Basic Memory Space

PD70433

000000H

Vector Area

1M Bytes

Spaecial Function Register Area

(Internal Area)

0FFFFFH

0FFF0H to 0FFFFFH is a program area used for the system boot, and PS and PC become 0FFFH and 0H, respectively, therefore the program execution starts from 0FFFF0H.

3.5.2 Extended Memory Space

The 16M-byte extended memory space is shown in Figure 3-4.

The only accesses that can be performed on the extended memory space are data accesses.

The basic memory space is mapped onto the lowest 1M bytes (000000H to 0FFFFFH) of the extended memory space, and can be accessed using the segment registers PS, SS, DS0 and DS1.

Data accesses can be performed in the extended memory space using the extended segment registers DS2 and DS3. With DS2 and DS3 it is possible to use a specification as a segment override prefix instruction added to a memory manipulation instruction.

An extended memory space physical address is specified by the segment start address indicated by the extended segment register and the offset value from the segment start position indicated by another register or immediate data. If the generated address indicates the lowest 1M-byte area (000000H to 0FFFFFH), the basic memory space is accessed.

00000H 003FFH

FFE00H

FFFEFH

Page 26

Figure 3-4. Extended Memory Space

PD70433

000000H

0FFFFFH

100000H

FFFFFFH

16M Bytes

Vector Area

1M Bytes

Spaecial Function

(Internal Area)

00000H 003FFH

FFE00H FFFEFH

3.5.3 Special Function Register Area

The 496-byte space 0FFE00H to 0FFFEFH has mapped onto it a group of registers to which functions such as on-chip peripheral hardware operation specification, status monitoring, etc., are assigned.

Program fetches cannot be performed from these areas.

Special function register manipulation is performed by accesses by means of memory manipulation instructions.

If the special function register area is accessed, RD, WRH, WRL, IORD, IOWR and other control signals do not become active.

A list of special function registers is given in Table 3-5. The meaning of the items in the table is explained below.

• Symbol............................ The symbol used to indicate the special function register name. Corresponds to the

operand description format (symbol name) in a memory manipulation instruction.

• R/ W ................................. Indicates whether this special function register is read/write enabled.

R/W : Read/write enabled R : Read only W : Write only

• Manipulation Method ..... Indicates which of the following can be used on the register: bit manipulation,

8-bit manipulation, 16-bit manipulation, 32-bit manipulation.

• RESET............................ Indicates the status of the register after RESET input.

Note Addresses which are not listed are the reserved area, therefore, they should not be accessed by the user

program.

Page 27

Table 3-5. Special Function Registers (1/7)

Address Special Function Register Name Symbol R/W After Reset

0FFE00H A/D conversion result register 0 ADCR0 R 0FFE02H A/D conversion result register 1 ADCR1 R 0FFE04H A/D conversion result register 2 ADCR2 R 0FFE06H A/D conversion result register 3 ADCR3 R 0FFE10H Parallel interface buffer PAD R/W *1 0FFE18H Parallel interface control register 0 PAC0 R/W

0FFE19H Parallel interface control register 1 PAC1 R/W 0FFE1AH Parallel interface status register PAS R/W *2 0FFE1CH Parallel interface acknowledge interval register 1 PAI1 W 0FFE1DH Parallel interface acknowledge interval register 2 PAI2 W 0FFE20H A/D converter mode register ADM R/W 0FFEC0H Interrupt mask flag register 0 (low) MK0L R/W 0FFEC1H Interrupt mask flag register 0 (high) MK0H R/W 0FFEC2H Interrupt mask flag register 1 (low) MK1L R/W 0FFEC3H Interrupt mask flag register 1 (high) MK1H R/W 0FFEC4H In-service priority register ISPR R 0FFEC5H Interrupt mode control register IMC R/W 0FFEC9H Interrupt request control register 09 IC09 R/W 0FFECAH Interrupt request control register 10 IC10 R/W 0FFECBH Interrupt request control register 11 IC11 R/W

0FFECCH Interrupt request control register 12 IC12 R/W 0FFECDH Interrupt request control register 13 IC13 R/W

*1.Varies according to input/output mode.

2. Some bits R, others R/W (possible).

MK0

MK1

Manipulable Bit Units

1 Bit 8 Bits 16 Bits 32 Bits

•

••

•

••

•

••

•

••

•

••

Undefined Undefined Undefined Undefined Undefined

90H 03H

40H Undefined Undefined

00H

FFH

00H

80H

43H

PD70433

Page 28

Table 3-5. Special Function Registers (2/7)

Address Special Function Register Name Symbol R/W After Reset

0FFECEH Interrupt request control register 14 IC14 R/W

0FFED0H Interrupt request control register 16 IC16 R/W 0FFED1H Interrupt request control register 17 IC17 R/W 0FFED2H Interrupt request control register 18 IC18 R/W 0FFED3H Interrupt request control register 19 IC19 R/W 0FFED4H Interrupt request control register 20 IC20 R/W 0FFED5H Interrupt request control register 21 IC21 R/W 0FFED6H Interrupt request control register 22 IC22 R/W 0FFED7H Interrupt request control register 23 IC23 R/W 0FFED8H Interrupt request control register 24 IC24 R/W

0FFED9H Interrupt request control register 25 IC25 R/W 0FFEDAH Interrupt request control register 26 IC26 R/W 0FFEDBH Interrupt request control register 27 IC27 R/W 0FFEDCH Interrupt request control register 28 IC28 R/W 0FFEDDH Interrupt request control register 29 IC29 R/W 0FFEDEH Interrupt request control register 30 IC30 R/W 0FFEDFH Interrupt request control register 31 IC31 R/W

0FFEE0H Interrupt request control register 32 IC32 R/W

0FFEE4H Interrupt request control register 36 IC36 R/W

0FFEE5H Interrupt request control register 37 IC37 R/W

0FFF00H Port 0 P0 R/W 0FFF01H Port 1 P1 R 0FFF02H Port 2 P2 R/W 0FFF03H Port 3 P3 R/W

Manipulable Bit Units

1 Bit 8 Bits 16 Bits 32 Bits

••

43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H

43H Undefined Undefined Undefined Undefined

PD70433

Page 29

Table 3–5. Special Function Registers (3/7)

Address Special Function Register Name Symbol R/W After Reset

0FFF04H Port 4 P4 R/W 0FFF05H Port 5 P5 R/W 0FFF06H Port 6 P6 R 0FFF07H Port 7 P7 R/W

0FFF08H Port 8 P8 R/W 0FFF0CH Port read control register PRDC R/W 0FFF0EH Real–time output port RTP R/W

0FFF10H Port 0 mode register PM0 R/W

0FFF12H Port 2 mode register PM2 R/W

0FFF13H Port 3 mode register PM3 R/W

0FFF14H Port 4 mode register PM4 R/W

0FFF15H Port 5 mode register PM5 R/W

0FFF17H Port 7 mode register PM7 R/W

0FFF18H Port 8 mode register PM8 R/W

0FFF22H Port 2 mode conrol register PMC2 R/W

0FFF23H Port 3 mode control register PMC3 R/W

0FFF24H Port 4 mode control register PMC4 R/W

0FFF25H Port 5 mode control register PMC5 R/W

0FFF27H Port 7 mode control register PMC7 R/W

0FFF28H Port 8 mode control register PMC8 R/W 0FFF2CH Real–time output port control register RTPC R/W 0FFF2DH Real–time output port delay specification register RTPD R/W 0FFF2EH Port 7 buffer (low) P7L R/W 0FFF2FH Port 7 buffer (high) P7H R/W

Manipulable Bit Units

1 Bit 8 Bits 16 Bits 32 Bits

••

Undefined Undefined Undefined Undefined Undefined

00H

Undefined

FFH FFH FFH FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H

40H Undefined Undefined Undefined

PD70433

Page 30

Table 3-5. Special Function Registers (4/7)

Address Special Function Register Name Symbol R/W After Reset

0FFF30H Timer control register 0 TMC0 R/W 0FFF31H Timer control register 1 TMC1 R/W 0FFF32H Timer output control register 0 TOC0 R/W 0FFF33H Timer output control register 1 TOC1 R/W 0FFF34H External interrupt mode register 0 INTM0 R/W

INTM

0FFF35H External interrupt mode register 1 INTM1 R/W 0FFF40H Timer register 0 TM0 R/W 0FFF42H Timer register 1 TM1 R/W 0FFF44H Timer register 2 TM2 R/W 0FFF46H Timer register 3 TM3 R/W

0FFF48H Timer capture register 00 CT00 R/W 0FFF4AH Timer capture register 01 CT01 R/W 0FFF4CH Timer compare register 00 CM00 R/W 0FFF4EH Timer compare register 01 CM01 R/W

0FFF50H Timer capture register 10 CT10 R/W

0FFF52H Timer compare register 10 CM10 R/W

0FFF54H Timer compare register 11 CM11 R/W

0FFF58H Timer compare register 20 CM20 R/W 0FFF5AH Timer compare register 21 CM21 R/W 0FFF5CH Timer compare register 22 CM22 R/W 0FFF5EH Timer compare register 23 CM23 R/W

0FFF60H Watchdog timer mode register WDM R/W*

0FFF64H Timer compare register 30 CM30 R/W

* WDT can only be written to by the RSTWDT instruction (8-bit unit only).

Manipulable Bit Units

1 Bit 8 Bits 16 Bits 32 Bits

••

•

••

•

••

•

••

•

••

•

Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

Undefined

00H 00H 00H 00H 00H 00H 00H 00H 00H 00H

PD70433

00H

Page 31

Table 3-5. Special Function Registers (5/7)

Address Special Function Register Name Symbol R/W After Reset

0FFF66H Timer compare register 31 CM31 R/W 0FFF6CH PWM register PWM R/W 0FFF6DH PWM control register PWMC R/W

0FFF70H Transmit baud rate generator register 0 T

0FFF71H Receive baud rate generator register 0 R

0FFF72H Prescaler register 0 PRS0 R/W

0FFF73H UART mode register 0 / clocked serial interface mode register 0 UARTM0/CSIM0 R/W

0FFF74H UART status register 0 / SBI control register 0 UARTS0/SBIC0 *1/*2

0FFF75H UART transmit buffer 0 / clocked serial I/O shift register 0 T

0FFF76H Receive buffer 0 R

0FFF78H Transmit baud rate generator register 1 T

0FFF79H Receive baud rate generator register 1 R 0FFF7AH Prescaler register 1 PRS1 R/W 0FFF7BH UART mode register 1 / clocked serial interface mode register 1 UARTM1/CSIM1 R/W 0FFF7CH UART status register 1 UARTS1 *1/*2 0FFF7DH UART transmit buffer 1 / clocked serial I/O shift register 1 T 0FFF7EH Receive buffer 1 R 0FFF7FH Protocol selection register ASP R/W

0FFF80H Terminal counter 0 (low) TC0L R/W

0FFF82H Terminal counter 0 (high) TC0H R/W

*1.Some bits R, others R/W.

2. R or W in bit units.

XBRG0 R/W XBRG0 R/W

XB0/SIO0 W XB0 R XBRG1 R/W XBRG1 R/W

XB1/SIO1 W XB1 R

TC0

Manipulable Bit Units

1 Bits 8 Bits 16 Bits 32 Bits

•

••

)

(

•

(

•

)

•

••

)

(

•

(

•

)

•

••

•

••

Undefined

00H

00H Undefined Undefined

00H

00H Undefined Undefined Undefined Undefined

00H

00H Undefined Undefined

PD70433

Remark ( ): Depends on the mode.

Page 32

Table 3-5. Special Function Registers (6/7)

Address Special Function Register Name Symbol R/W After Reset

0FFF84H Terminal counter modulo register 0 (low) TCM0L R/W

TCM0

0FFF86H Terminal counter modulo register 0 (high) TCM0H R/W 0FFF88H DMA up/down counter 0 (low) UDC0L R/W

UDC0

0FFF8AH DMA up/down counter 0 (high) UDC0H R/W 0FFF8CH DMA compare register 0 (low) DCM0L R/W

DCM0

0FFF8EH DMA compare register 0 (high) DCM0H R/W

0FFF90H DMA memory address register 0 (low) MAR0L R/W

MAR0

0FFF92H DMA memory address register 0 (high) MAR0H R/W 0FFF94H DMA read/write pointer 0 (low) DPTC0L R/W

DPTC0

0FFF96H DMA read/write pointer 0 (high) DPTC0H R/W 0FFF9CH DMA mode register 0 DMAM0 R/W 0FFF9DH DMA control register 0 DMAC0 R/W 0FFF9EH DMA status register DMAS R/W 0FFFA0H Terminal counter 1 (low) TC1L R/W

TC1

0FFFA2H Terminal counter 1 (high) TC1H R/W 0FFFA4H Terminal counter modulo register 1 (low) TCM1L R/W

TCM1

0FFFA6H Terminal counter modulo register 1 (high) TCM1H R/W 0FFFA8H DMA up/down counter 1 (low) UDC1L R/W

UDC1

0FFFAAH DMA up/down counter 1 (high) UDC1H R/W

0FFFACH DMA compare register 1 (low) DCM1L R/W

DCM1

0FFFAEH DMA compare register 1 (high) DCM1H R/W 0FFFB0H DMA memory address register 1 (low) MAR1L R/W

MAR1

0FFFB2H DMA memory address register 1 (high) MAR1H R/W

* Bit clear operation possible.

Manipulable Bit Units

1 Bit 8 Bits 16 Bits 32 Bits

•

••

•

••

•

••

•

••

•

••

•

••

•

••

•

••

•

••

•

••

Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

E0H 00H

00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined

PD70433

Page 33

Table 3-5. Special Function Registers (7/7)

Address Special Function Register Name Symbol R/W After Reset

0FFFB4H DMA read/write pointer 1 (low) DPTC1L R/W

DPTC1

0FFFB6H DMA read/write pointer 1 (high) DPTC1H R/W 0FFFBCH DMA mode register 1 DMAM1 R/W 0FFFBDH DMA control register 1 DMAC1 R/W

0FFFE0H Software timer/counter STC R

0FFFE2H Software timer/counter compare register STMC R/W

0FFFE8H Programmable wait control register 0 PWC0 R/W

0FFFE9H Programmable wait control register 1 PWC1 R/W

0FFFEAH Memory block control register MBC R/W 0FFFECH Refresh mode register RFM R/W

0FFFEEH Standby control register STBC R/W *1

0FFFEFH Processor control register PRC R/W

*1 The SFB bit of the standby control register can be set (1) by instruction, but cannot be cleared (0). (Only '1' can be written.) *2 After power-on reset: 00H, otherwise: no change

Manipulable Bit Units

1 Bit 8 Bits 16 Bits 32 Bits

•

••

•

••

Undefined Undefined

E0H 00H

Undefined

FFFFH

EAH AAH FCH

77H

Undefined *2

EEH

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3.5.4 Vector Table Area

The 1K–byte area 00000H to 003FFH in the memory space holds 256 vectors (4 bytes used per vector) for the start

addresses of interrupt routines initiated by interrupt requests, break instructions, etc.

In the initial state, vectors 0 to 47 are reserved as V55PI family dedicated on-chip peripheral and software interrupt vectors. For vectors 8 to 47, the vector address of hardware interrupts except NMI can be changed by means of bits V0 and V1 of the interrupt mode control register (IMC).

Vector 0 (00000H) : Divide error Vector 1 (00004H) : Single step Vector 2 (00008H) : NMI instruction Vector 3 (0000CH) : BRK 3 instruction Vector 4 (00010H) : BRKV instruction Vector 5 (00014H) : CHKIND instruction Vector 6 (00018H) : Input/output instruction Vector 7 (0001CH) : FPO instruction/exception trap

When V1 = V0 = 0 :

Vector 8 (00020H) : INTWDT Vector 9 (00024H) : INTP0 Vector 10 (00028H) : INTP1 Vector 11 (0002CH) : INTP2 Vector 12 (00030H) : INTP3 Vector 13 (00034H) : INTP4 Vector 14 (00038H) : INTP5 Vector 15 (0003CH) : System reserved Vector 16 (00040H) : INTCM00 Vector 17 (00044H) : INTCM01 Vector 18 (00048H) : INTCM10 Vector 19 (0004CH) : INTCM11 Vector 20 (00050H) : INTCM21 Vector 21 (00054H) : INTCM31 Vector 22 (00058H) : INTD0 DMA#0_MAIN Vector 23 (0005CH) : INTD0S DMA#0_SUB Vector 24 (00060H) : INTD1 DMA#1_MAIN Vector 25 (00064H) : INTD1S DMA#1_SUB Vector 26 (00068H) : INTSER0 Vector 27 (0006CH) : INTSER1 Vector 28 (00070H) : INTSR0/INTCSI0 Vector 29 (00074H) : INTSR1/INTCSI1 Vector 30 (00078H) : INTST0 Vector 31 (0007CH) : INTST1 Vector 32 (00080H) : INTSIT Vector 33 (00084H) : System reserved Vector 34 (00088H) : System reserved Vector 35 (0008CH) : System reserved Vector 36 (00090H) : INTPAI Vector 37 (00094H) : INTAD Vector 38 (00098H) : System reserved Vector 39 (0009CH) : System reserved

Page 35

Vector 40 (000A0H) : System reserved Vector 41 (000A4H) : System reserved Vector 42 (000A8H) : System reserved Vector 43 (000ACH) : System reserved Vector 44 (000B0H) : System reserved Vector 45 (000B4H) : System reserved Vector 46 (000B8H) : System reserved Vector 47 (000BCH) : System reserved

When V1 = 0, V0 = 1 :

Vector 72 (00120H) : INTWDT Vector 73 (00124H) : INTP0

•• •

Vector 110 (001B8H) : System reserved Vector 111 (001BCH) : System reserved

When V1 = 1, V0 = 0 :

Vector 136 (00220H) : INTWDT Vector 137 (00224H) : INTP0

•• •

Vector 174 (002B8H) : System reserved Vector 175 (002BCH) : System reserved

PD70433

When V1 = 1, V0 = 1 :

Vector 200 (00320H) : INTWDT Vector 201 (00324H) : INTP0

•• •

Vector 238 (003B8H) : System reserved Vector 239 (003BCH) : System reserved

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PD70433

3.6 REGISTER FILE SPACE

The register file space is shown in Figure 3-5.

The size of the register file space is 512 bytes, and a maximum 16-bank register set can be set.

The register file space is separate from the memory space, and in addition to accesses using a register manipulation instruction as with the V25 and V35, the register file space can be accessed as data memory by adding a special prefix instruction (IRAM:) to a memory manipulation instruction. (Access is performed asynchronously independently of the external bus cycle.

When the IRAM: prefix instruction is added to a memory manipulation instruction, the CPU performs a data access with the low–order 9 bits of the memory address offset value as the register file address. In this case, segment register and physical address addition is not performed, and an external bus cycle is not initiated.

Example

Label1: MOV IRAM : [0024H], AW

MOV [0056H], BW

<1> This shows the case where data is transferred to the register file space using an "IRAM:" prefix

instruction. The AW register value is stored in address 24H of the register file.

<2> This shows the case where an instruction for data transfer to the memory space is used.

If the IRAM prefix instruction is added to the primitive block transfer instruction and BCD operation instruction, which

specify the source block and destination block, it becomes effective for the destination block.

Also, the macro service conrol word area (008H to 03FH), the macro service work area (000H to 007H), and the area used by the macro service channel (008H to 0FFH) are allocated in overlapping fashion in the file space. If a specific macro service which requires work area (RTOPTRN) is not used, these work areas can be used as data space.

.....

<1> <2>

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(

)

1FFH

Figure 3-5. Register File Space

Macro Service Work Area

Macro Service Control Word Area

Macro Service Channel Area

000H

008H 03FH

0FFH

+00H

+02H

+04H

+06H

+08H

+0AH

+0CH

+0EH

+10H

+12H

+14H

+16H

+18H

+1AH

+1CH

+1EH

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15 87 0

DS2

Vector PC/DS3

PSW Save

PC Save

DS0

DS1

Offset from the starting address of each register bank

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PD70433

3.7 I/O SPACE

The V55PI has a 64K-byte I/O space.

The I/O space map is shown in Figure 3-6.

The I/O space is accessed using address bus/data bus and control signals (IORD, IOWR, etc).

0 is output from the unused high-order 8 bits of the address bus.

Wait cycles can be inserted in an I/O cycle by software and the READY pin.

The area FF80H to FFFFH of the I/O space is a reserved area, in which two V55PI on-chip peripheral DMA input/output read/write pointers (IOP) are allocated. The address of IOP0 is FF94H, and the address of IOP1 is FFB4H.

When the CPU executes an input/output instruction with an IOP address as an operand, the DMA controller performs a read/write of data in the DMA controller transfer buffer, with the IOP contents as the address value, and increments (or decrements) the IOP value automatically in accordance with the contents of the DMA control register. Therefore, data written by the DMA controller can be referenced by an input/output instruction, and conversely, data written by an input/output instruction can be transferred by the DMA controller.

Figure 3-6. I/O Map (64K Bytes)

0000H

FF80H FF94H

FFB4H

FFFFH

Remark IOPn corresponds to the DMA read/write pointer (DPTCn).

IOP 0

IOP 1

Reserved Area

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PD70433

4. BUS CONTROL FUNCTIONS

With the V55PI pin, refer to 1.1.2 (1) "Pin function for bus control".

As regards pins which have an alternate function as port pins, when that function is used, the corresponding function must be selected by means of the port mode control register (PMCn).

4.1 WAIT FUNCTION

The V55PI divides the basic memory space (000000H to 0FFFFFH) into a maximum of 4 blocks with a variable memory size, divides the uppermost extended memory space area (100000H to FFFFFFH) into two areas with a variable memory size, and performs wait control for each block. The memory size of each block in the basic memory space is specified by the memory block control register (MBC).

Figure 4-1 shows the memory block configuration when A9H has been set for the MBC register value.

Figure 4-1. Partitioned Memory Control

MBC

MB300MB211MB200MB111MB101MB010MB00

MB31

01 00 01 10

00 01 10

Main Memory Space

Block 0

Block 1

Block 2 Block 3 Block 4

128K Bytes

256K Bytes

512K Bytes 640K Bytes 768K Bytes 896K Bytes 1M Bytes

2M Bytes 4M Bytes

6M Bytes 8M Bytes

Block 5

16M Bytes

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Figure 4-2. Memory Wait Control

76543210

PD70433

PWC1

PWC0

(BLOCK3) (BLOCK2) (BLOCK1) (BLOCK0)

DW31 DW30 DW21 DW20 DW11 DW10 DW01 DW00

76543210

(BLOCK4) (BLOCK1) (I/O Space) (BLOCK5) (BLOCK4)

AW1 AW0 IOW1 IOW0 DW51 DW50 DW41 DW40

Data Wait (DW, IOW)

DWn1/IOW1 DWn0/IOW0 Wait State

000 *1

011 *2

102 *2

113 *2

*1.READY signal is ignored.

2. Additional control by means of READY signal is also possible.

Address Wait (AW)

AWn Wait State

AW0

AW1

0 Not inserted (block 1)

1 Inserted (block 1)

0 Not inserted (block 4)

1 Inserted (block 4)

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4.2 REFRESH FUNCTION

The following functions are provided to refresh DRAM and pseudo-SRAM.

• Function to insert periodically a refresh cycle in a series of bus cycles

• Refresh address output function to refresh DRAM and pseudo-SRAM

• Function to generate a refresh cycle in hold mode and HALT mode.

• Function to insert a wait state in a refresh cycle

4.2.1 Refresh Mode Register (RFM)

The RFM register is an 8-bit register to control refresh operation. A refresh cycle can be selected from the time base counter output tap. While a refresh request is held by another bus cycle if the next refresh request is generated, only the latter is valid. The RFM register value after a reset is 77H.

4.2.2 Wait Control in Refresh Cycle

A wait state can be inserted in a refresh cycle. The specified number of wait states is inserted for memory block 4 by

the programmable wait control register (PWC0) or READY pin.

4.2.3 Refresh Address

Bus pins AD0 to AD15 and A16 to A19 are activated in a refresh cycle.

For each refresh cycle, the count is performed in one-address increments from x00000 to x1FFFFF in the case of the external 8-bit bus width, and in two-address increments from x00001H to xFFFFF in the case of the external 16-bit bus width (the minimum address is returned to after the maximum address).

After initialization by a reset, count-up is started from x00000H in the case of the external 8-bit bus width and x00001H in the case of the external 16-bit bus width.

In the case of the external 16-bit bus width, the refresh address minimum address bit (A0) is fixed at “1” and the DEX pin output is also fixed at “1”.

A20 to A23 are undefined in a refresh cycle.

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PD70433

5. INTERRUPT FUNCTIONS

The V55PI incorporates a powerful interrupt controller (INTC) which controls multiple-interrupt servicing for a total of 25 maskable hardware interrupt requests: 19 internal and 6 external. The interrupt controller controls multiple-interrupt servicing based on programmable priority.

The following functions are provided as interrupt servicing modes: vectored interrupt function, macro service function, register bank switching function.

5.1 FEATURES

V55PI interrupt functions offer the following features:

• Comprehensive servicing states for interrupt requests

• Vectored interrupt function : Branch to interrupt service routine specified by vector table

• Register bank switching function : High-speed interrupt response by automatic register bank switching

• Macro service function : High-speed interrupt servicing by microprogram (firmware)

• 4-level programmable priority order control

• Interrupt multiprocessing control according to the priority

• Rich variety of macro service functions (following 7 modes) closely tied to V55PI on-chip peripheral hardware

EVTCNT : Event count processing BLKTRS : Data transfer between special function register and external memory buffer BLKTRS-C : Data transfer between special function register and external memory buffer (with transfer data

detection function) DTACMP : Special function register status detection DTADIF : Time measurement by timer capture function RTOPTRN : Automatic control of real-time output port DTACMP-M : Data transfer between external I/O and memory

• 7 external interrupt request inputs (NMI, INTP0 to INTP5)

• Maskable interrupt requests are individually maskable.

A list of interrupt sources is given in Table 5-1.

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Table 5-1. Interrupt Sources (1/2)

Interrupt Default Vector Vectored Macro

Classification Priority Generating Generating Table Address Service

Nonmaskable –– ––

10 INTCM01 IC17 CM01 match detection 17 00×44H Yes Yes 022H

Maskable

11 INTCM10 IC18 CM10 match detection 18 00×48H Yes Yes 024H 12 INTCM11 IC19 CM11 match detection 19 00×4CH Yes Yes 026H 13 INTCM21 IC20 CM21 match detection 20 00×50H Yes Yes 028H 14 INTCM31 IC21 CM31 match detection 21 00×54H Yes Yes 02AH

Interrupt Register Macro Service Request Bank Control Word

Signal Switching Address

1 NMI NMI pin input ––– 2 00008H No No

2 WDT Watchdog timer overflow WDT 8 00×20H No No

3 INTP0 IC9 INTP0 pin input 9 00×24H Yes Yes 012H

4 INTP1 IC10 INTP1 pin input 10 00×28H Yes Yes 014H

5 INTP2 IC11 INTP2 pin input 11 00×2CH Yes Yes 016H

6 INTP3 IC12 INTP3 pin input 12 00×30H Yes Yes 018H

7 INTP4 IC13 INTP4 pininput 13 00×34H Yes Yes 01AH

8 INTP5 IC14 INTP5 pin input 14 00×38H Yes Yes 01CH

9 INTCM00 IC16 CM00 match detection 16 00×40H Yes Yes 020H

Interrupt Request

Control Register

Interrupt Source Default

Source Unit Number

External

Timer

15 INTD0 IC22 DMA channel 0_main 22 00×58H Yes Yes 02CH 16 INTD0S IC23 DMA channel 0_sub 23 00×5CH Yes Yes 02EH

DMA

17 INTD1 IC24 DMA channel 1_main 24 00×60H Yes Yes 030H 18 INTD1S IC25 DMA channel 1_sub 25 00×64H Yes Yes 032H

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Table 5-1. Interrupt Sources (2/2)

Interrupt Default Vector Vectored Macro

Classification Priority Generating Generating Table Address Service

19 INTSER0 IC26 UART reception error (ch0) 26 00×68H No Yes 034H 20 INTSER1 IC27 UART reception error (ch1) 27 00×6CH No Yes 036H

21 IC28 28 00×70H 038H

22 IC29 29 00×74H 03AH

Maskable INTCSI1 LDMA channel 5 Yes Yes

23 INTST0 IC30 UART transmission (ch0) 30 00×78H Yes Yes 03CH 24 INTST1 IC31 UART transmission (ch1) 31 00×7CH Yes Yes 03EH 25 INTSIT IC32 STM match detection SIT 32 00×80H No Yes –– 26 INTPAI IC36 Parallel I/F Parallel I/F 36 00×90H Yes Yes –– 27 INTAD IC37 A/D converter

Interrupt Register Macro Service Request Bank Control Word

Signal Switching Address

INTSR0/ UART reception (ch0)/ INTCSI0 Serial transmission/reception (ch0) Yes Yes

INTSR1/ UART reception (ch1)/ Yes Yes

Interrupt Request

Control Register

Divide error 0 00000H No No BRK flag (single-step) 1 00004H No No

Interrupt Sourse Default

Source Unit Number

Serial I/F

A/D converter

37 00×94H Yes Yes 008H

Yes Yes

BRK3 instruction 3 0000CH No No BRKV instruction 4 00010H No No

Software

CHKIND instruction 5 00014H No No

–– –– –– –– ––

Input/output instruction (IBRK flag) 6 00018H No No BRK imm8 * 00×*HNo No BRKCS instruction –– –– No Yes

FP0 instruction/ Exception 7 0001CH No No trap Exception trap

* Indicates that the value is variable in the range 0 to 255 (0 to FFH). Remarks "×" indicates that the value is determined by the V0 and V1 bits of the IMC register.

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5.2 INTERRUPT RESPONSE METHODS

The V55PI has three interrupt response methods: a vectored interrupt function, register bank switching function, and macro service function. In the case of a maskable interrupt request, one of these functions can be selected by means of the interrupt request control register (IC××) for each interrupt source according to the purpose of the interrupt. The on-chip interrupt controller handles interrupt requests according to the set response method.

5.2.1 Vectored Interrupts

A vectored interrupt can only be acknowledged in the interrupt enabled state (EI state). When a vectored interrupt is acknowledged, the CPU enters the interrupt disabled state (DI state), and the current PSW contents and PC and PS contents are saved to the stack. Then the corresponding vector is selected from the vector table, and the interrupt service routine is started at the address indicated by that vector. Vector numbers are fixed for each interrupt source. In the DI state, interrupts are held pending, and are acknowledged when the EI state is set again.

The return from the interrupt is performed by an RETI instruction. In the case of a hardware interrupt other than a nonmaskable interrupt, an FINT instruction must be executed before the return instruction. When a return is made from an interrupt, the PC, PS and PSW are restored from the stack.

Figure 5-1. Interrupt Acknowledge Operation (Performed in Sequence <1> → <4>)

n × 4

n × 4 + 2

Vector Table Stack

n: Vector Number

<4>

<2>

<1>

PSW

IE = 0

<3>

BRK = 0

SP – 6

SP – 4

SP – 2

SP ← SP – 6

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PD70433

5.2.2 Register Bank Switching Function

In the V55PI, general register sets are mapped onto on-chip RAM, and register sets can be held in up to 16 banks. Interrupt servicing is performed by automatically switching the register bank when a BRKCS or TSKSW instruction is executed or when an interrupt is responded to. Because saving of registers to the stack previously performed by software is not required, high-speed switching of the program execution environment is possible.

The register bank switching sequence is performed as follows (See Figure 5-2).

<1> The contents of PSW is saved to temporary register.

<2> The register bank is switched.

<3> IE and BRK are set to 0.

<4> The contents of PSW which is saved to the PC and the temporary register are saved to the saving area, respectively.

<5> The interrupt service routine start address offset value is loaded from the vector PC area in the register bank to

PC.

Figure 5-2. Register Bank Switching Sequence

(In Case of Register Bank Switching by Interrupt)

New Register Bank

Old Register Bank

for Interrupt Servicing

AW CW DW

SP BP

IX IY

DS1

PS SS

DS0

PC Save

PSW Save

Vector PC/DS3

DS2

PSW

<1>

<5>

Temporary Register

<4> <4>

SP BP

IX IY

DS1

PS SS

DS0

PC Save

PSW Save

Vector PC/DS3

DS2

<2> Register Bank Switching <3> IE = 0, BRK = 0

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PD70433

5.2.3 Macro Service Function

The macro service function performs processing of simple data transfers, etc., by means of a microprogram (CPU internal dedicated firmware) started by generation of an interrupt request. The simple, standardized interrupt servicing which was coded and executed by a user program is performed automatically.

Macro service processing is caused by an interrupt request and is performed. Macro service is designed to minimize as far as possible the frequency of generation of interrupts consisting mainly of software processing, hold down the software overhead due to a series of processes used in an interrupt (register saving, initialization, register restoration, return from the interrupt routine), and improve the CPU efficiency.

Processing performed by the macro service is transparent in terms of software, and it is possible to process as a single mass of data what was previously processed by software byte by byte, allowing more efficient programming.

The V55PI macro service supports not only the simple data transfers used in the V25 and V35, but also various operating modes closely linked to the on-chip V55PI peripheral hardware, as shown below.

(a) EVTCNT (EVENT COUNTER)

The counter is updated each time the macro service are generated, and when the counter reaches 0 the macro service

for the corresponding interrupt source is terminated and a vectored interrupt or a register bank switching is generated.

(b) DTACMP (DATA COMPARE)

The interrupt source specific SFR and preset byte data are compared, and if they match, the macro service for the

corresponding interrupt source is terminated and a vectored interrupt or register bank switching is generated.

The difference in using the timer/counter unit capture register is calculated. This is initiated by a timer interrupt: the value of the capture register latched last time is subtracted from the value of the capture register latched this time, and the result is stored in the previously specified memory buffer.

When processing has been performed the previously set number of times, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated.

(d) BLKTRS (BLOCK TRANSFER)

A data transfer is performed between the previously specified memory buffer and SFR.

When the previously set number of data transfers have been performed, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated.

(e) BLKTRS–C (BLOCK TRANSFER WITH CHARACTER SEARCH)

A data transfer is performed between the previously specified memory buffer and SFR. When the previously set number of data transfers have been completed, or when the transfer data matches the previously set character data, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated.

(f) RTOPRTN (RTOP TRANSFER)

Data to be output to the real-time output port is transferred to the port 7 buffer (P7H, P7L), and data which specifies interval for output to the real-time output port is transferred to the timer compare register (CM00, CM01).

(g) DTACMP-M (DATA COMPARE WITH CHARACTER MASK)

The logical product of the status data read from the external I/O and the previously set mask data is performed. The previously set byte data is compared with the result. If it matches, a data transfer is performed between the external I/ O and memory. If it does not match, or if the previously set number of data transfers have been performed, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated.

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PD70433

6. DMA FUNCTION (DMA CONTROLLER)

The V55PI incorporates a 2-channel DMA controller which controls execution of memory-to-I/O or memory-to-memory

DMA transfers on the basis of DMA requests generated by an on-chip peripheral hardware (serial interface, parallel interface, or timer), the external DMARQ pin or a software trigger.

Each channel of the DMA controller further comprises a main channel and a sub-channel: the operating mode determines

whether the main channel and sub-channel are used as a single channel or as separate channels. When used as separate channels, function for a maximum of 4 channels can be constructed.

6.1 FEATURES

• Two independent DMA channels (max. 4-channel configuration possible)

• Four transfer modes

• Single transfer mode ... One DMA transfer cycle is executed in response to one DMA request.

• Demand release mode ... Consecutive DMA transfer cycles are executed while DMA request is active.

• Single-step mode ... DMA transfer cycles and CPU bus cycles are executed alternately after DMA request generation.

• Burst mode ... For each DMA request, the specified number of DMA transfer cycles are executed consecutively.

• Five operating modes

• Intelligent DMA mode–1 (ring buffer system) ... DMA transfers to ring buffer are controlled.

• Intelligent DMA mode–2 (counter control system) ... Transfer data is transferred consecutively, divided into

an arbitrary number of bytes.

• Next address specification mode ... Consecutive transfers are possible between different

transfer buffers.

• 2-channel operating mode ... Main channel and subchannel are used as independent

channels.

• Memory-to-memory transfer mode ... Two bus cycles are started for one DMA transfer cycle,

and memory-to-memory transfer is executed.

• 3 clocks/1 bus cycle (no wait case)

• Transfer objects

• External I/O ←→ memory ... 1 DMA transfer cycle/1 bus cycle

• SFR (internal I/O) ←→ memory ... 1 DMA transfer cycle/1 bus cycle

• Memory ←→ memory (memory includes SFR) ... 1 DMA transfer cycle/2 bus cycles

• Byte transfer/word transfer selectable

• Transfer address increment/decrement/non-update selectable

• DMA transfer end signal (TCE0, TCE1) output

• 24-bit DMA memory address registers (MAR0, MAR1)

• 21-bit terminal counters (TC0, TC1)

• External DMA request signal input pins (DMARQ0, DMARQ1: alternate function as port P80 and P81 pins)

• External DMA acknowledge signal output pins (DMAAK0, DMAAK1)

Page 49

DMA Start Source

Transfer

Mode On–Chip Software

Peripheral Trigger

Table 6-1. Transfer Modes

DMARQ Pin

PD70433

STOP Method Interrupt

Single transfer Available Available Available mode

Demand release mode

Single step Available* Available Available mode

Burst None (stop disabled during the mode transfer)

Not Available Not Available Available

Available* Available Available

Reset of EDMA bit of DMAMn register

Stops when the DMARQ pin is Not acknowledged driven low during the transfer. during transfer. Reset of EDMA bit of DMAMn Acknowledged at register other times.

Reset of EDMA bit of DMAMn

Acknowledged

Acknowledged register

Not acknowledged

* The DMA start source is an on-chip timer interrupt, and transfer is possible only when the transfer I/O specification is

external.

Table 6-2. Correspondence Between Operating Modes and Transfer Modes

Possible Transfer Modes*

Operating Mode Transfer Type

<1> <2> <3> <4>

Intelligent DMA mode–1 I/O (SFR) → Memory (ring buffer method)

Yes Yes No No

Intelligent DMA mode–2 Memory → I/O (SFR) (counter control method)

Next address specification mode I/O (SFR) ←→ Memory Yes Yes No No

2–channel operating mode

Memory–memory transfer mode

(Stop at end) I/O ←→ Memory Yes Yes Yes Yes

(Repetition) I/O ←→ Memory Yes Yes Yes No

(Stop at end) Memory ←→ Memory Yes No Yes Yes

(Repetition) Memory ←→ Memory Yes No Yes No

No No Yes Yes

* Transfer modes

<1> Single transfer mode <2> Demand release mode <3> Single step mode <4> Burst mode

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PD70433

7. SERIAL INTERFACE FUNCTIONS

The V55PI is equipped with a 2-channel serial interface unit (ch0, ch1). The two communication protocols supported by the V55PI are as follows:

(1) Asynchronous UART (2) Clocked CSI SBI: 2-wire serial bus interface

IOE: I/O expansion 3-wire serial interface

7.1 FEATURES

• Two communication protocols supported

• Two serial channels

• Wake-up function

• On-chip dedicated baud rate generator

• DMA request generated by completion of transmission/reception (transmit/receive data DMA transfer is

capable)

7.2 PROTOCOLS

The UART is an asynchronous serial interface which achieves data synchronization by means of start/stop bits, and is

functionally enhanced UART functions compared with previous single-chip microcontroller.

The CSI (clocked serial interface) is a clocked serial interface which achieves synchronization by transmission/reception of a clock. The CSI is a subset of the standard serial bus interface specification for NEC single-chip microcontrollers, and I2C functions are not supported. The wake-up release function is implemented by using macro service.

Table 7-1. Supported Protocols

Supported Protocols

Serial Interface Unit Clocked (CSI) Asynchronous

SBI IOE (UART)

Channel 0 Yes Yes Yes

Channel 1 No Yes Yes

The UART function or CSI function can be programmably selected for each channel. Protocol selection is performed by means of the protocol selection register (ASP).

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7.3 UART

7.3.1 Features

• Transfer rate: 95 to 390 Kbps (with 12.5 MHz system clock 123 to 500 Kbps (with 16 MHz system clock

)

• Full-duplex operation capability

• On-chip dedicated (transmission and reception) baud rate generators

• Wake-up function

• Zero parity function

• Parity error detection

• Framing error detection

• Overrun error detection

• Three dedicated UART interrupt sources

• UART receive error interrupts (INTSER0, INTSER1)

• UART reception interrupts (INTSR0, INTSR1)

• UART transmisstion interrupts (INTST0, INTST1)

• Macro service function

• UART reception interrupts (INTSR0, INTSR1)

• UART transmission interrupts (INTST0, INTST1)

PD70433

)

R×D

T×C*

INTSR

External Clock Control

Figure 7–1. UART Block Diagram

R×B

Shift Register UARTS Shift Register

Reception Control Parity Check

ERP ERF ERO

INTSER

T×B

Transmission Control Parity Addition

INTST

UARTM

T×D

CTS

Transmit Serial Clock

Receive Serial Clock

* Channel 0 only

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PD70433

7.4 CLOCKED SERIAL INTERFACE (CSI)

7.4.1 Features

• Transfer speed: Max. 3.125 Mbps (with 12.5 MHz system clock

Max. 4.0 Mbps (with 16 MHz system clock

• Half-duplex communication

• Data length: 8-bit unit

• External/internal clock selection function

• Data MSB-first/LSB-first selection function

• SBI mode (2-wire NEC type serial bus) ... ch0 only

• Address/command/data identification function

• Function for chip selection by address

• Wake-up function

• Acknowledge signal (ACK) control function

• Busy signal (BUSY) control function

The V55PI clocked serial interface has the following two operating modes.

(1) 3–wire serial I/O mode (IOE mode)

In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK), and serial data input and output (SI, SO). This mode is useful when connecting an I/O device, display controller, etc., which incorporates a conventional clocked serial interface.

The functions of the V25 and V25+ have been enhanced, and data MSB-first/LSB-first selection is possible.

)

(2) Serial bus interface mode (SBI mode)

In the SBI mode, communication is performed with multiple devices by means of two lines: the serial clock (SCK) and the serial bus interface (SB0 or SB1).

This mode conforms to the NEC serial bus format.

In the SBI mode, the sender can output to the serial data bus an address to select the target device for serial communication, a command which gives a directive to the target device, and actual data. Thus there is no need for the line for handshaking required when multiple devices are connected with a conventional clocked serial interface, allowing input/output ports to be used efficiently.

In addition, wake-up release is performed using macro service.

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8. PARALLEL INTERFACE FUNCTIONS

The V55PI incorporates a parallel interface unit for data input on a Centronics specification interface, and general data

input/output.

8.1 FEATURES

The following features are provided as parallel interface functions:

• Centronics specification interface compatibility

• Input/output mode switchable by software

• BUSY signal manipulable by software

• BUSY signal and ACK signal output timing settable

• Initialization by external interrupt

• Dedicated parallel interface interrupt source

• Parallel interface interrupt (INTPAI)

• DMA request signal generation in parallel transmission/reception

• INTPAI functions as a DMA start trigger.

• Signal pin input/output characteristic is TTL level (Centronics specification interface)

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(a) Input mode

Figure 8-1. Parallel Interface Block Diagram

Input Data Latch

PD0–PD7

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(b) Output mode

Internal BusInternal Bus

DATA RD

RESET

DATA WR

IBF

MB0, 1

DMA Request

PAI Timer

Counter

IBSY

S R

ACK Timing Control

BUSY Control Circuit

ACK Control Circuit

Output Data Latch

DATASTB

BUSY

ACK

INTP5

PD0–PD7

DMA Request

INTPAI Request

INT/ DMA Request Control

PAI Timer

DATASTB

Counter

BUSY

ACK

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9. TIMER FUNCTION

The V55PI timer unit can be used as an interval timer, free-running timer and event counter. It is also possible to manipulate P7 as a real-time output port, synchronized with interrupt requests generated by the timer. The normal timer function and real-time output port function are described here.

9.1 FEATURES

The timer function offers the following features.

• 16-bit timer × 4

• Two count clock sources are selectable

• System clock scaled output selectable (φ/8, φ/32: system clock φ)

• External input pulses from TI pin

• External count output signal (TOn output)

• Three 16-bit capture registers on chip (external interrupt input signals INTP0 to INTP2 as triggers)

• Six dedicated timer unit interrupt source (INTCM00, INTCM01, INTCM10, INTCM11, INTCM21, INTCM31)

• Real-time output port function synchronized with timer interrupts

9.2 TIMER UNIT CONFIGURATION

The timer unit configuration is shown in Figure 9-1, and the function of each timer in Table 9-1.

Count function Available Available Available Available

Capture function Available Available Not Available Not Available

Compare function Available Available Available Available

Function Toggle

Timer output output function Set/reset

output

Cascading Not Available Not Available Available

Table 9-1. Timer Functions

Timer 0 Timer 1 Timer 2 Timer 3

Available Not Available Available Not Available

Not Available Not Available Available Available

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Figure 9-1. Timer Unit Block Diagram

INTP0 INTP1

/32

Timer 0

TO00 TO01

INTP2

/32

TO20

16–Bit Free Running Timer (TM0)

Capture Register (CT00)

Capture Register (CT01) Compare Register (CM00) Compare Register (CM01)

Timer 2

16–Bit Timer Register 2 (TM2)

Compare Register (CM20)

Clear

OVF

INTCM00 INTCM01

T T

To Real–Time Output Port

INTCM21

SRQ

16–Bit Timer Register/Event Counter 1

Capture Register (CT10) Compare Register (CM10) Compare Register (CM11)

Clear, Count Enable

Timer 1

(TM1)

Timer 3

16–Bit Timer Register 3 (TM3)

Compare Register (CM30)

Clear

OVF

INTCM10

INTCM11

INTCM31

SRQ

TO30 Compare Register (CM21) Compare Register (CM22) Compare Register (CM23)

SRQ

To DMA Controller

Compare Register (CM31)

TO21

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9.3 REAL-TIME OUTPUT PORT FUNCTION

Port 7 of the V55PI incorporates a real-time output port function, and can output the contents of the port 7 buffer (P7H,

P7L) at programmable intervals from timer 0 bit-wise.

9.3.1 Real-Time Output Port Configuration

The real-time output port configuration is shown in Figure 9-2. It comprises the following buffer registers, output and

control registers.

(1) Port 7 buffer (P7H, P7L)

The buffer registers hold the data to be output next when port 7 is set to the real-time output port mode. The port 7 buffer contents are not affected by reset input.

(2) Real-time output port (RTP)

Real-time output port output data is held in this port after being taken from the port 7 buffer, and output from the

pins.

RTP can be read or written to by an 8-bit or single-bit manipulation instruction (unlike the port 7 output port).

(3) Real-time output port delay specification regiser (RTPD) and delay counter

This register is set and used when using the mode in which a delay time is inserted in the timing for output from

the real-time output port (RTP) to the output pins.

If the P7L bit is set to "0", "0" is output to the corresponding output pin bit after the elapse of the delay time equivalent to the count clock cycle time set in the real-time output port delay specification register after the time at which the transfer trigger is generated. The delay time in this case is counted by the delay counter.

(4) Real-time output port control register (RTPC)

RTPC specifies the operating mode of the real-time output port. It is possible to specify whether or not a delay is to be inserted when data is output, the timing for transferring data to the port 7 buffer, the transfer timing trigger, and so on.

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Figure 9–2. Real–Time Output Port Operation

RTPC

P7H

Port 7 Buffer

Real–Time Output

Port Control Register

Internal Bus

Output

Latch

RTP Bit 3

TRG, BYTE

DLY

P7L

Port 7 Buffer

Delay

Bor-

row

No Delay

Delay Counter

Preset

Delay Specification

Selector

RTPD

INTCM00

(Timer 0)

INTCM01

(Timer 1)

To Port 7

Output Latches

RTP7 to RTP4

P77 P76 P75 P74 P73 P72 P71 P70

Control Output Signals

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9.3.2 Real-Time Output Port Operation

Real-time output port specification is performed bit-wise by the port 7 mode control register (PCM7). Port 7 (P7), the port 7 buffer (P7H, P7L) and the real-time output port can be accessed as real-time output ports. Data output is performed as described below.

When output data is written in the port 7 buffer (P7H, P7L), the port 7 buffer contents are transferred to the real-time output port (RTP) and output to the pins in synchronization with the timing of an interrupt request from timer 0 (INTCM00, INTCM01), or a write to the TRG bit in the control register (RTPC).

An example of the direct control of the output pattern for a real-time output port and the output interval is shown in Figure 9-3.

Update data is transferred from the two data storage areas set beforehand in the external memory space to the realtime output function buffer registers (P7H, P7L) and compare registers (CM00, CM01).

Figure 9-3. Real-Time Output Port Stepping Motor Control

Output Data Area

Output Timing Data Area

Compare Register

CLK

Free Running Timer

CM00 or CM01

TM0

External Memory Space

D1 D2 D3 D4

T1 T2 T3 T4

Timer 0

Interrupt Request

Match

Macro Service Processing

Real-Time Output Trigger/

Macro Service Activation

TransferTransfer or Addition

INTCM00 or INTCM01

Output Data Pointer

Buffer Register Address

Compare Register Address Output Timing Data Pointer

RC Initial Value

Real–Time Output Counter (RC)

Macro Service Counter

Mode Register

Channel Pointer

Internal Bus

Real-Time Output Port

Buffer Register

P7H, P7L

–1

Macro Service Control Word

RTP

Output Latch

Stepping Motor

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In particular, it is possible to insert a delay time in the timing for output by setting the real-time output port delay specification register (RTPD) pins. If the P7L bit is changed from "1" to "0", it is possible to perform output after inserting a delay time of 2 × the system clock set in the RTPD from the timing at which the transfer trigger is generated. In this case, "0" is output from the corresponding output pin. This delay is counted by the delay counter.

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10. PWM UNIT

The V55PI is provided with an 8-bit precision PWM (pulse width modulation) signal output function.

PWM output can be used as a digital-to-analog conversion output by connecting a low-pass filter, etc., externally. This is ideal for the actuator control signal for motors, etc.

10.1 FEATURES

The PWM unit offers the following features:

• PWM output pulse active level selectable

• Frequency: 25 MHz (with 12.5 MHz system clock → PWM cycle: 40.96

: 32 MHz (with 16 MHz system clock

→ PWM cycle: 32.00

• Output pulse width (duty): 0, 1/256, ....., 255/256

→ Resolution: 160 ns (with 12.5 MHz system clock φ)

10.2 PWM UNIT CONFIGURATION

The configuration of the PWM unit is shown in Figure 10-1. The PWM unit consists of the PWM register (PWM) and PWM control register (PWMC), and an 8-bit counter. The PWM register controls the pulse width (duty) in the PWM output mode. The 8–bit counter is set to 00H by reset input.

The PWM register is not affected by reset input.

125 ns (with 16 MHz system clock

)

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Figure 10-1. PWM Unit Block Diagram

8-Bit Counter

Comparator

PWM Slave Latch

Preset

PWM Register

Overflow

Match Detection Signal

Internal Bus

000000CE ALV

Active

Level

Control

PWM Control Register

PWM Output

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11. WATCHDOG TIMER FUNCTION

The watchdog timer is a function for preventing inadvertent program looping and deadlocks.

11.1 FEATURES

• Three overflow times settable (8.1, 32.7, 131.0 [ms]: system clock

clock

= 12.5 MHz)

• Output pin provided (WDTOUT pin) which can be directly connected to the RESET pin

11.2 WATCHDOG TIMER CONFIGURATION AND OPERATION

Non-generation of a watchdog timer interrupt enables normal operation of the program or system to be confirmed. To use the watchdog function, an instruction (RSTWDT) to clear the watchdog timer (start the count) must be included in at fixed intervals in the program execution time, at the start of a subroutine, etc.

If the instruction which clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (INTWDT) is generated and the low-level signal is output to the WDTOUT pin to report a program error.

The watchdog timer configuration is shown in Figure 11-1.

= 16 MHz) (10.4, 41.9, 167.7 [ms]: system

Figure 11-1. Watchdog Timer Configuration Diagram

Frequency Divider

WDTCLR

RESET

STOP

Watchdog Timer (8 bits)

Clear

Overflow

WDTOUT

Active Timer

(5 bits)

INTWDT

Oscillation Stabilizing Time Control Circuit

OVF

WDTOUT

*1.

: System clock

2. WDTCLR: Watchdog timer clearance by instruction

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12. A/D CONVERTER FUNCTION

The V55PI incorporates a high-speed, high-precision 8-bit analog/digital (A/D) converter with four analog inputs (ANI0 to ANI3). The A/D converter uses the successive approximation method, and is provided with four A/D conversion result registers (ADCR0 to ADCR3) which hold the conversion results.

12.1 FEATURES

The A/D converter offers the following features:

• Incorporates four 8-bit A/D conversion result registers.

• Four analog input pins (ANI0 to ANI3)

• Two A/D converter conversion operating modes

• Scan mode : Performs conversion by selecting multiple analog inputs in sequence.

• Select mode : Performs continuous conversion with only one pin used as the analog input.

• Two conversion start methods

• Hardware start : Started by trigger input (INTP4)

• Software start : Started by A/D converter mode register (ADM) bit setting

• Generation of conversion end interrupt request (INTAD)

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Figure 12-1. A/D Converter Block Diagram

Series Resistance String

ANI0 ANI1 ANI2 ANI3

P15/INTP4

External Trigger

A/D Converter Mode Register (ADM)

Input

Circuit

Internal Bus

Sample & Hold Circuit

Control

Comparator

Successive Approxi-

mation Register (SAR)

A/D Conversion Result Register 0 (ADCR0) A/D Conversion Result Register 1 (ADCR1) A/D Conversion Result Register 2 (ADCR2)

A/D Conversion Result Register 3 (ADCR3)

R/2

Tap Decoder

R/2

REF

INTAD

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Internal Bus

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13. STANDBY FUNCTIONS

The V55PI has two methods for controlling the operating clock as standby functions designed to reduce power dissipation. Transition to either of these standby modes is possible by means of a dedicated instruction.

Table 13-1. HALT/STOP Mode Operating Status

Parameter HALT Mode STOP Mode

Clock generator Operating

Internal system clock Stopped

16–bit timer

Watchdog timer

Hold circuit

Serial interface

Parallel interface

A/D Converter

Interrupt request controller

DMA controller

IORD, IOWR High level High level

AD0 to AD15

Bus lines Retained

A16 to A23

R/W output High level High level

Refresh operation Operating Stopped

Data retention

Release method

Operating

Change accordng to DMAC operating status

All internal data retained (CPU status, All internal data retained (CPU status, RAM contents, etc.) RAM contents, etc.)

• NMI

• INTWDT • NMI

• Maskable interrupt request • RESET input

• RESET input

Stopped

13.1 HALT MODE

In this mode, the CPU operating clock is halted.

Setting the CPU idle time to the HALT mode enables overall system power dissipation to be reduced. The HALT mode is entered by executing the HALT instruction.

In the HALT mode the CPU clock and program execution are stopped, and all register and on-chip RAM contents immediately prior to the stoppage are retained. The status of each hardware unit is shown in Table 13-1.

When the HALT instruction is executed during a DMA transfer, transition to the HALT mode is deferred until the transfer bus cycle for one DMA request is completed.

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13.2 STOP MODE

In this mode, clock oscillation is stopped.

This is effective when the entire application system is stopped, and offers extremely low power dissipation. The STOP mode is entered by executing the STOP instruction. In this mode all clocks are stopped. Program execution is stopped, and all register and on-chip RAM contents immediately prior to the stoppage are retained. The status of each hardware unit is shown in Table 13-1.

When the STOP instruction is executed during a DMA transfer, transition to the STOP mode is deferred until the transfer bus cycle for one DMA request is completed. If there is contention between a refresh cycle and STOP instruction execution, transition to the STOP mode is deferred until the refresh cycle is completed.

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14. CLOCK GENERATOR

The clock generator supplies various clocks to the CPU and peripheral hardware, and controls the CPU operating mode.

14.1 CLOCK GENERATOR CONFIGURATION AND OPERATION

The clock generator is configured as shown in Figure 14-1.

The clock generator clock is generated by a crystal resonator or ceramic resonator connected to the X1 and X2 pins. The clock generator output is subjected to waveform shaping (dividing frequency by 2) and selection of the scaling factor by means of the processor control register (PRC), and is then used as the system clock φ.

The system clock 1/2, 1/4, 1/8 or 1/16 the oscillator frequency (f

Selecting a low-speed system clock of a battery-driven system even when the voltage drops.

An external clock can be input. In this case, the clock signal should be input to the X1 pin, and leave the X2 pin open.

scaling factor is specified by the PCK1 and PCK0 bits of the PRC register, and can be selected as

XX).

reduces the current consumption of internal circuit, allowing extended operation

Figure 14-1. Clock Generator

Waveform Shaping

Frequency

Clock Oscillator

Internal Bus

PRC PCK0 PCK1

TB0 TB1

ENCLK

1 1

Dividers

1/2 1/2

1/2

)

(=f

8 1

4 1

Selector

Time Base Counter

Software Interval Timer Refresh Cycle Generator PWM Baud Rate Generator

Watchdog Timer

System Clock

CLKOUT

fXX : Oscillator frequency

: System clock

PRC: Processor control register

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In the V55PI, the frequency divider (time base counter: TBC) which divides the internal system clock φ is shared by each

timer unit.

The TBC cannot be read or written to by an instruction. The TBC tap output (divide-by-2

clock) is supplied to the units shown below as a count clock.

(1) Refresh cycle generator (2) Software interval timer (3) PWM unit (4) Baud rate generator

The TBC is cleared to 00H only by reset input, after which it is constantly incremented. TBC operation is stopped in the

STOP mode. The configuration of the TBC is shown in Figure 14-2.

Figure 14-2. Frequency Divider (Time Base Counter, TBC) Configuration

PWM

Baud Rate

Generator

TBC

Refresh Cycle

Generator

Software Interval

and

Timer

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15. SOFTWARE INTERVAL TIMER FUNCTION

The V55PI incorporates a 16-bit software interval timer as a timer for software timer functions and watch functions.

15.1 SOFTWARE INTERVAL TIMER CONFIGURATION

The configuration of the software interval timer is shown in Figure 15-1.

Figure 15-1. Software Interval Timer Configuration

Software Timer Counter (STC)

/128

Clear

Software Timer Counter Compare Register (STMC)

INTSIT

Match Detection

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16. CODEC INSTRUCTIONS

The V55PI has 9 codec instructions.

Using these special instructions on the V55PI enables not only image information MH encoding but also MR encoding which previously required the use of a special device such as an ACEE (advanced compression/expansion engine) to be implemented by means of a small-scale, high-speed codec.

16.1 FEATURES

The V55PI has the following 9 codec instructions (4 for compression, 5 for expansion):

• Compression instructions (1) Change point table creation instruction: COLTRP (2) Data transmission instruction (transmission of EOL *1, FILL, RTC *2, etc.): ALBIT (3) MH encoding instruction: MHENC (4) MR encoding instruction: MRENC

• Expansion instructions (5) EOL detection instruction: SCHEOL (6) 1-bit (tag) detection instruction: GETBIT (7) MH decoding change point table creation instruction: MHDEC (8) MR decoding change point table creation instruction: MRDEC (9) Pixel data creation instruction: CNVTRP

MH/MR encoding and MH/MR decoding using these instructions are performed as shown in Figures 16-1 and

16-2.

*1. EOL: End Of Line

2. RTC: Return To Control

Note When compression/expansion processing is performed using the V55PI codec instructions, the following

should be specified as preconditions.

• Compression/expansion is to be performed line by line.

• Consideration must be given to task switching and interrupt generation during compression processing.

• The number of bits processed per line must not be changed during processing of one page.

• The segment value must be changed for data over 64 Kbytes that straddles segments during processing.

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Figure 16-1. MH/MR Encoding Processing Flow

Start

K = 0 L = Number of lines

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K = 0

Yes

Data transmission instruction (EOL + tag bit "1" transmission)

Change point table creation instruction

MH encoding instruction

K = K factor – 1 K = K – 1

Data transmission instruction (FILL transmission)

L = L – 1

Data transmission instruction (EOL + tag bit "0" transmission)

Change point table creation instruction

MR encoding instruction

Data transmission instruction (RTC transmission)

L = 0

Yes

End

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Figure 16-2. MH and MR Decoding Processing Flow

Start

EOL detection instruction

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Error detection To Error Processing

1–bit detection instruction (tag bit detection)

Tag = 1

Yes

MH decoding instruction

Yes

End Error detection End

EOL detection

at start

Error detection

Yes

To Error Processing

Yes

MR decoding instruction

EOL detection

at start

Yes

Pixel data creation instruction

* RTC is detected by two EOLs.

Pixel data creation instruction

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16.2 MEMORY MAP

The data memory areas required by the V55PI's codec instructions are shown below.

(1) Register file space

This is the register bank for parameter setting.

(2) User RAM

Encoding line change point table : Storage area for change point information required for performing encoding

In the case of n bit/lines, a maximum area of 2n + 4 bytes is required. Reference line table : Reference line change point information storage area Image data buffer : Storage area for pixel data read from scanner in encoding, or encoding data

received from modem in decoding Transmit/receive buffer : Buffer for transferring encoded data to modem/scanner Print buffer : Buffer for transferring decoded pixel data to recording system

(3) User ROM

Encoding conversion table : Conversion table for MH/MR encoding Decoding conversion table : Conversion table for MH/MR decoding

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(4) Access to Expanded Memory Space

The 16-Mbyte expanded memory space can be accessed by using the expanded segment override prefix instruction (DS2: or DS3:). However, the segment registers DS2 and DS3 that are used during instruction execution are DS2 and DS3 in the parameter setting register banks of each instruction.

Table 16-1. Instructions to which Expanded Segment Override Prefix Can Be Attached

DS2: DS3: CODEC Instruction

Yes Yes COLTRP Yes No MHENC Yes Yes MHDEC Yes No MRENC Yes Yes MRDEC Yes No SCHEOL Yes No GETBIT Yes Yes CNVTRP

Example

DS2 : DS3 : COLTRP DS2 : SCHEOL

The relationship between encoding instructions and data in memory is shown in Figure 16-3, and the relationship between

decoding instruction and data in memory is shown in Figure 16-4.

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Figure 16-3. Encoding Instructions and Data in Memory

DMA

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Parameter

Frame

User ROM

Encoding Conversion

Table (512 Bytes) *

* In case of MH/MR encoding instructions

Figure 16-4. Decoding Instruction and Data in Memory

Software User RAM

Data Output Instruction

Change Point Table Creation Instruction

MH/MR Encoding

Instruction

Image Data (1 Line)

Work (Change Points)

Coding Data (1 Line)

DMA

Parameter

Frame

User ROM

Decoding Conversion

Table (2304 Bytes)*

* In case of MH/MR decoding instructions

Software User RAM

EOL Detection Instruction

1–Bit Detection Instruction

MH/MR Decoding

Instruction

Image Data Creation

Instruction

Coding Data

Work (Change Points)

Image Data (1 Line)

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16.3 PROCESSING FLOW

The instructions shown in 16.1 "Features" are used in the order shown in Figures 16-5 and 16-6 in encoding/decoding

procesing.

Figure 16-5. Processing Flow for Encoding of One Line

Start

Data transmission instruction

(ALBIT)

Transmission of EOL and tag

Change point table creation instruction

(COLTRP)

Change point information for 1 line created, and stored in prescribed storage area (change point table)

MH/MR encoding instruction

(MHENC/MRENC)

(Pixel Data)

Input

Output

(Change Point Table)

Black

White

02113116

1 Word

Input

White

Black

White

Black

.....

Black

White

.....

MH/MR encoding for 1 line

Encoded Data → Transmision Buffer

Fill transmission

End

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Figure 16-6. Processing Flow for Decoding of One Line

Start

EOL detection instruction

(SCHEOL)

EOL (000000000001) is detected

1 bit detection instruction

(GETBIT)

Tag (1 bit) is detected

Encoded Data ← Printer Buffer

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MH/MR decoding instruction

(MHDEC/MRDEC)

MH/MR decoding change point information for 1 line is generated and stored in specified area (change point table)

Pixel data creation instruction

(CNVTRP)

Pixel data for 1 line is created

End

Input

Output

(Change Point Table)

Black

White

02113116

Input

Output

(Pixel Data)

White

1 Word

Black

White

Black

White

.....

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17. INSTRUCTION SET

The V55PI instruction set is upward compatible with the V20/V30 (native mode) and V25/V35 instruction sets.

17.1 INSTRUCTIONS NEWLY ADDED TO V20/V30 AND V25/V35

Instructions which have been added to the V20/V30 and V25/V35 instruction sets, and instructions whose application

range has been extended, are shown below.

(1) Instructions added to V20/V30.

Mnemonic Operand Instruction Group BRKCS reg 16 TSKSW reg 16 MOVSPA None MOVSPB reg 16 BTCLR sfr, imm3, short-label Conditional branch instruction RETRBI None FINT None STOP None CPU control instruction

Data transfer instruction

Interrupt instruction

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(2) Instructions added to V25/V35.

Mnemonic Operand Instruction Group IRAM None Register file space access override prefix instrution

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DS2 None DS3 None

DS2, reg16, mem32 DS3, reg16, mem32

MOV

PUSH

POP

RSTWDT imm8, imm8’ Watchdog timer manipulation instruction BTCLRL sfrl, imm3, short-label Conditional branch instruction

BSCH

xsreg, reg16 xsreg, mem16 reg16, xsreg mem16, xsreg DS2 DS3/VPC DS2 DS3/VPC

reg8 mem8 reg16

Extended segment override prefix instruction

Data transfer instruction

Stack manipulation instruction

Bit manipulation instruction

mem16 QHOUT imm16 QOUT imm16 Queue manipulation instruction QTIN imm16 ALBIT None COLTRP None MHENC None MRENC None SCHEOL None Dedicated FAX instruction GETBIT None MHDEC None MRDEC None CNVTRP None

Remark VPC: Vector PC

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17.2 INSTRUCTION SET OPERATIONS

Table 17-1. Operand Type Legend

Identifier Description

reg, 8/16-bit general register

(Destination register in an instruction using two 8/16-bit general registers) reg’ Source register in an instruction using two 8/16-bit general registers reg8, 8-bit general register

(Destination register in an instruction using two 8-bit general registers) reg8' Source register in an instruction using two 8-bit general registers reg16, 16-bit general register

(Destination register in an instruction using two 16-bit general registers) reg16' Source register in an instruction using two 16-bit general registers mem 8/16-bit memory address mem8 8-bit memory address mem16 16-bit memory address mem32 32-bit memory address sfr Special function register location: FFF00H to FFFEFH sfrl Special function register location: FFE00H to FFEFFH dmem 16-bit direct memory address imm 8/16-bit immediate data imm3 3-bit immediate data imm4 4-bit immediate data imm8 8-bit immediate data imm8' 8-bit immediate date (1’s compliment of imm8) imm16 16-bit immediate data acc Accumulator AW or AL sreg Segment register xsreg Extended segment register src-table Name of 256-byte conversion table src-block Name of source block addressed by register IX dst-block Name of destination block addressed by register IY src-string Name of source string addressed by register IX dst-string Name of destination string addressed by register IY near-proc Procedure start address in current program segment far-proc Procedure start address in a different program segment near-label Absolute address in current program segment short-label Relative address of memory in range –128 to +127 bytes from end of instruction far-label Absolute address in a different program segment regptr16 16-bit general register holding call address offset in current program segment memptr16 16-bit memory address holding call address offset in current program segment memptr32 32-bit memory address holding call address offset and segment data in a different program segment pop-value Number of bytes removed from stack (0 to 64K, normally an even number) fp-op Immediate value which identifies external floating point operation coprocessor operation code repeat Repeat prefix instruction IRAM : Register file space access override prefix instruction R Register set (AW, BW, CW, DW, SP, BP, IX, IY) ( ) Omissible or, / Or

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Table 17-2. Operation Code Legend

Identifier Description

W Word/byte specification bit (1: word, 0: byte). However, when s = 1, sign extension byte data is

specified as 16-bit operand even if W = 1. reg, reg’ 8/16-bit general register specification bits (000 to 111) mod, mem Memory addressing specification bits (mod: 00 to 10, mem: 000 to 111) (disp-low) Optional 16-bit displacement low byte (disp-high) Optional 16-bit displacement high byte disp-low 16-bit displacement low byte for PC relative addition disp-high 16-bit displacement high byte for PC relative addition imm3 3-bit immediate data imm4 4-bit immediate data imm8 8-bit immediate data imm8' 8-bit immediate data (1's complement of imm8) imm16-low 16-bit immediate data low byte imm16-high 16-bit immediate data high byte addr-low 16-bit direct address low byte addr-high 16-bit direct address high byte sreg Segment register specification bits (00 to 11) xsreg Extended segment register specification bits (10 to 11) s Sign extension specification bit (1: sign extension, 0: no sign extension) offset-low Low byte of 16-bit offset data to be loaded in PC offset-high High byte of 16-bit offset data to be loaded in PC seg-low Low byte of 16-bit segment data to be loaded in PS seg-high High byte of 16-bit segment data to be loaded in PS pop-value-low Low byte of 16-bit data which specifies number of bytes to be removed from stack pop-value-high High byte of 16-bit data which specifies number of bytes to be removed from stack disp8 8-bit displacement for relative addition to PC X XXX YYY ZZZ





Operation code of an external floating point operation coprocessor







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Table 17-3. Operation Description Legend

Identifier Description

AW Accumulator (16 bits) AH Accumulator (high byte) AL Accumulator (low byte) BW Register BW (16 bits) CW Register CW (16 bits) CL Register CL (low byte) DW Register DW SP Stack pointer (16 bits) BP Base Pointer (16 bits) PC Program counter (16 bits) PSW Program status word (16 bits) IX Index register (source) (16 bits) IY Index register (destination) (16 bits) PS Program segment register (16 bits) DS3 Extended data segment 3 register (16 bits) DS2 Extended data segment 2 register (16 bits) DS1 Data segment 1 register (16 bits) DS0 Data segment 0 register (16 bits) SS Stack segment register (16 bits) AC Auxiliary carry flag CY Carry flag P Parity flag S Sign flag Z Direction flag IE Interrupt enable flag V Overflow flag IBRK I/O break flag BRK Break flag RB0 Register bank 0 flag RB1 Register bank 1 flag RB2 Register bank 2 flag RB3 Register bank 3 flag VPC Vector PC (...) Contents of memory indicated by contents of in parenthesis disp Displacement (8/16-bit) temp Temporary register (8/16/32 bits) ext–disp8 16 bits with 8-bit displacement sign-extended seg Immediate segment data (16 bits) offset Immediate offset data (16 bits) ← Transfer direction + Addition

− Subtraction × Multiplication ÷ Division

% Modulo

∧ Logical product (AND) ∨ Logical sum (OR)

V Exclusive logical sum (exclusive OR)

××H 2-digit hexadecimal number ××××H 4-digit hexadecimal number

/ Alternate function, or

PD70433

Page 83

Table 17-4. Flag Operation Legend

Identifier Description

(Blank) No change

0 Cleared to 0 1 Set to 1

× Set or cleared depending on result U Undefined R Previously saved value is restored

Table 17-5. Memory Addressing

PD70433

mem

mod

000 BW + IX BW + IX + disp8 BW + IX + disp16

001 BW + IY BW + IY + disp8 BW + IY + disp16

010 BP + IX BP + IX + disp8 BP + IX + disp16

011 BP + IY BP + IY + disp8 BP + IY + disp16

100 IX IX + disp8 IX + disp16

101 IY IY + disp8 IY + disp16

110 Direct address BP + disp8 BP + disp16 111 BW BW + disp8 BW + disp16

00 01 10

Note When BP is used in memory addressing other than in a primitive instruction, the default segment register

is SS. When BP is not used, the default segment register is DS0. In primitive instruction memory addressing, the destination block default segment register is DS1. In memory addressing, the source block default segment register is DS0.

Table 17-6. 8/16-Bit General Register Selection Table 17-7. Segment Register Selection

reg W = 0 W = 1 sreg

000 AL AW 00 DS1

001 CL CW 01 PS

010 DL DW 10 SS

011 BL BW 11 DS0

100 AH SP

101 CH BP

110 DH IX

111 BH IY xsreg

Table 17-8. Extended Segment Register Selection

10 DS3/VPC

11 DS2

Page 84

PD70433

Number of Clock Cycles

In the case of a memory operand the number of clock cycles depends on the addressing mode. The following numbers

should be used for “EA” in Table 17-9 “Number of Clock Cycles”.

mod

mem Cycles Cycles Cycles

000 BW + IX 3 BW + IX + disp8 3 BW + IX + disp16 3 001 BW + IY 3 BW + IY + disp8 3 BW + IY + disp16 3 010 BP + IX 3 BP + IX + disp8 3 BP + IX + disp16 3 011 BP + IY 3 BP + IY + disp8 3 BP + IY + disp16 3 100 IX 2 IX + disp8 2 IX + disp16 2 101 IY 2 IY + disp8 2 IY + disp16 2 110 Direct address 2 BP + disp8 2 BP + disp16 2 111 BW 2 BW + disp8 2 BW + disp16 2

“T” indicates the number of wait states. Any number of wait states from "0" (no wait) up can be used.

00 Clock 01 Clock 10 Clock

Page 85

Mnemonic Operands

Group

Instruction

reg, reg' –– 2 2 2 2

mem, reg –– EA + 2 EA + 3 EA + 2 EA + 3

Table 17-9. Number of Clock Cycles (1/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

reg, mem EA + 2 EA + 5 + T EA + 2

mem, imm –– EA + 2 EA + 3 EA + 2 EA + 3

reg, imm –– 2 2 2 2

acc, dmem 4 7 + T 4

dmem, acc –– 4 5 4 5

sreg, reg16 –– –– –– 2 2

xsreg, reg16 VPC, reg16

MOV sreg, mem16 –– –– EA + 2

xsreg,mem16/

Data transfer instructions

VPC, mem16

reg16, sreg –– –– –– 2 2

8 EA + 8 + 2T

16 EA + 5 + T

8 10 + 2T

16 7 + T

–– –– 2 2

8 EA + 8 + 2T

16 EA + 5 + T

8 EA + 8 + 2T

–– –– EA + 2

16 EA + 5 + T

reg16, xsreg/ reg16, VPC

mem16, sreg –– –– –– EA + 2 EA + 3

mem16, xsreg/ mem16, VPC

DS0, reg16, mem32

DS2, reg16, mem32

DS1, reg16, mem32

DS3, reg16, mem32

–– –– 2 2

–– –– EA + 2 EA + 3

8 EA + 17 + 4T

–– –– EA + 5

16 EA + 11 + 2T

8 EA + 17 + 4T

–– –– EA + 5

16 EA + 11 + 2T

8 EA + 17 + 4T

–– –– EA + 5

16 EA + 11 + 2T

8 EA + 17 + 4T

–– –– EA + 5

16 EA + 11 + 2T

* 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Page 86

Mnemonic Operands

Group

Instruction

AH, PSW –– 2 2 –– ––

Table 17-9. Number of Clock Cycles (2/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

MOV 8 3 3

LDEA reg16, mem16 –– –– –– EA + 2 EA + 2 TRANS/

TRANSB

XCH

Data transfer instructions

MOVSPA –– –– –– 8 8

MOVSPB reg16 –– –– –– 9 9

REPC –– 0 to 1 0 to 1 0 to 1 0 to 1

REPNC –– 0 to 1 0 to 1 0 to 1 0 to 1

REP/ REPE/ –– 0 to 1 0 to 1 0 to 1 0 to 1 REPZ

Repeat prefixes

REPNE/ REPNZ

MOVBK

PSW, AH –– ––

src-table –– 6 9 + T –– ––

reg, reg' –– 4 4 4 4

mem, reg/ reg, mem

AW, reg16/ reg16, AW

dst-block, src-block

16 2 2

EA + 10 + 2T

EA + 4 EA + 7 + T EA + 4

EA + 7 + T

–– –– –– 4 4

–– 0 to 1 0 to 1 0 to 1 0 to 1

21 + 2T 22 + 2T

18 + T 19 + T

8 9 + (14 + 2T)n 9 + (18 + 4T)n

MOVBKB/ MOVBKW

CMPBK

Primitive block transfer instructions

CMPBKB/ CMPBKW

src-block, dst-block

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Remark n: Number of repetitions

(rep)

9 + (11 + T)n 9 + (12 + 2T)n

16 9 + (11 + T)n 9 + (12 + 2T)n

16 9 + (13 + T)n 9 + (15 + 2T)n

(rep CW = 0)

20 + T 22 + 2T

8 9 + (16 + 2T)n 9 + (21 + 4T)n

(rep)

9 + (13 + T)n 9 + (15 + 2T)n

(rep CW = 0)

18 + T 19 + T

23 + 2T 28 + 4T

20 + T 22 + 2T

Page 87

Mnemonic Operands

Group

Instruction

Table 17-9. Number of Clock Cycles (3/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

CMPM dst-block 20 + T

8 10 + (12 + 2T)n

CMPMB/ CMPMW

16 10 + (9 + T)n

LDM src-block 16 + T

8 9 + (9 + 2T)n

LDMB/ LDMW

16 9 + (6 + T)n

Primitive block transfer instructions

STM dst-block 13

8 9 + (9 + 2T)n

STMB/ STMW

16 9 + (6 + T)n

15 17 + T 15

(rep)

10 + 7n 10 + (9 + T)n 10 + 7n

(rep CW = 0)

555

10 13 + T 10

(rep)

9 + 3n 9 + (6 + T)n 9 + 3n

(rep CW = 0)

555

12 13 12

(rep)

9 + 5n 9 + (6 + T)n 9 + 5n

(rep CW = 0)

555

17 + T

13 + T

reg8, reg8' –– –– 22 to 63

INS

reg8, imm4 –– –– 22 to 63

reg8, reg8' –– –– 19 to 41

EXT

Bit field manipulation instructions

reg8, imm4 –– –– 19 to 41

8 31 to 72

16 23 to 64

8 31 to 72

16 23 to 64

8 19 + 2T to 48 + 4T

16 19 to 42 + 2T

8 19 + 2T to 48 + 4T

16 19 to 42 + 2T

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Remark n: Number of repetitions

Page 88

Table 17-9. Number of Clock Cycles (4/20)

PD70433

Mnemonic Operands

Group

Instruction

acc8, imm8

IN*2

acc, DW

imm8, acc

OUT*2

Input/output instructions

DW, acc

INM*2

dst-block, DW

RAM Access Access RAM Access Access

Bus Width

8 10 + 2T

16 7 + T

8 10 + 2T

16 7 + T

8 9 + (13 + 2T)n 9 + (17 + 4T)n

(rep)

9 + (10 + T)n 9 + (11 + 2T)n

16 9 + (10 + T)n 9 + (11 + 2T)n

(rep CW = 0)

Byte Processing Word Processing

On-Chip Other On-Chip Other

–– 7 + T ––

–– 5 –– 5

17 + T 18 + T

20 + 2T 21 + 2T

17 + T 18 + T

14 + T 17 + 2T

(rep)

9 + (7 + T)n 9 + (10 + 2T)n

(rep CW = 0)

Primitive input/output instructions

OUTM*2

DW, src-block

8 9 + (10 + 2T)n 9 + (16 + 4T)n

16 9 + (7 + T)n 9 + (10 + 2T)n

*1. 8 : 8-bit width

16 : 16-bit width

2. When IBRK = 1. As shown in the next page when IBRK = 0.

Remark n: Number of repetitions

17 + 2T 23 + 4T

14 + T 17 + 2T

Page 89

Mnemonic Operands

Group

Instruction

Table 17-9. Number of Clock Cycles (5/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

OUT

Input/output instructions

Primitive input/

output instructions

* 8 : 8-bit width

16 : 16-bit width

acc8, imm8

acc, DW

imm8, acc

DW, acc

dst-block, DWINM

DW, src-blockOUTM

8 60 + 10T 60 + 10T

–– ––

16 40 + 5T 40 + 5T

8 60 + 10T 60 + 10T

–– ––

16 40 + 5T 40 + 5T

8 60 + 10T 60 + 10T

–– ––

16 40 + 5T 40 + 5T

8 60 + 10T 60 + 10T

–– ––

16 40 + 5T 40 + 5T

8 60 + 10T 60 + 10T

–– ––

16 40 + 5T 40 + 5T

8 60 + 10T 60 + 10T

–– ––

16 40 + 5T 40 + 5T

Page 90

Mnemonic Operands

Group

Instruction

reg, reg' –– 3 3 3 3

Table 17-9. Number of Clock Cycles (6/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem, reg EA + 4 EA + 7 + T EA + 4

ADD

ADDC

Addition/subtraction instructions

reg, mem EA + 2 EA + 6 + T EA + 2

reg, imm –– 2 2 2 2

mem, imm EA + 4 EA + 7 + T EA + 4

acc, imm –– 2 2 2 2

reg, reg' –– 3 3 3 3

mem, reg EA + 4 EA + 7 + T EA + 4

reg, mem EA + 2 EA + 6 + T EA + 2

reg, imm –– 2 2 2 2

mem, imm EA + 4 EA + 7 + T EA + 4

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 10 + 2T

16 EA + 7 + T

acc, imm –– 2 2 2 2

reg, reg' –– 3 3 3 3

mem, reg EA + 4 EA + 7 + T EA + 4

SUB

reg, mem EA + 2 EA + 6 + T EA + 2

reg, imm –– 2 2 2 2

mem, imm EA + 4 EA + 7 + T EA + 4

acc, imm –– 2 2 2 2

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 10 + 2T

16 EA + 7 + T

Page 91

Mnemonic Operands

Group

Instruction

reg, reg' –– 3 3 3 3

Table 17-9. Number of Clock Cycles (7/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem, reg EA + 4 EA + 7 + T EA + 4

reg, mem EA + 2 EA + 6 + T EA + 2

SUBC

reg, imm –– 2 2 2 2

Addition/subtraction instructions

ADD4S

SUB4S

CMP4S

ROL4

BCD operation instructions

mem, imm EA + 4 EA + 7 + T EA + 4

acc, imm –– 2 2 2 2

dst-string, src-string

reg8 8 5 5 –– ––

mem8 16 EA + 5 EA + 8 + T –– ––

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 10 + 2T

16 EA + 7 + T

6 + (15 + T)n 6 + (19 + 3T)n –– ––

6 + (16 + T)n 6 + (20 + 3T)n –– ––

6 + (15 + T)n 6 + (18 + 2T)n –– ––

ROR4

INC

DEC

Increment/decrement instructions

reg8 8 5 5 –– ––

mem8 16 EA + 5 EA + 8 + T –– ––

reg8 –– 2 2 –– ––

8 EA + 10 + 2T

mem EA + 3 EA + 7 + T EA + 3

16 EA + 7 + T

reg16 –– –– –– 2 2

reg8 –– 2 2 –– ––

8 EA + 10 + 2T

mem EA + 3 EA + 7 + T EA + 3

16 EA + 7 + T

reg16 –– –– –– 2 2

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Remark n: Half of number of BCD digits

Page 92

Mnemonic Operands

Group

Instruction

reg8 –– 11 11 15 15

Table 17-9. Number of Clock Cycles (8/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem8 EA + 12 EA + 14 + T EA + 16

MULU

reg16 –– 11 11 15 15

mem16 EA + 12 EA + 14 + T EA + 16

reg8 –– 10 10 14 14

mem8 EA + 11 EA + 13 + T EA + 15

reg16 –– 10 10 14 14

Multiplication instructions

MUL

mem16 EA + 11 EA + 13 + T EA + 15

reg16, reg16', imm8/reg16, –– –– –– 14 14 imm8

reg16, 8 EA + 20 + 2T mem16, –– –– EA + 15 imm8 16 EA + 17 + T

8 EA + 21 + 2T

16 EA + 18 + T

8 EA + 21 + 2T

16 EA + 18 + T

8 EA + 20 + 2T

16 EA + 17 + T

8 EA + 20 + 2T

16 EA + 17 + T

reg16, reg16', imm16/reg16, –– –– –– 14 14 imm16

reg16, 8 EA + 20 + 2T mem16, –– –– EA + 15 imm1616 EA + 17 + T

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Page 93

Mnemonic Operands

Group

Instruction

Table 17-9. Number of Clock Cycles (9/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

reg8

mem8

DIVU

reg16

mem16

reg8

Division instructions

mem8

DIV

reg16

mem16

8 15/62 + 10T 15/62 + 10T 23/57 + 10T 23/57 + 10T

16 15/42 + 5T 15/42 + 5T 23/42 + 5T 23/42 + 5T

8 EA + 16/63 + 10T

16 EA + 16/43 + 5T

8 15/62 + 10T 15/62 + 10T 23/57 + 10T 23/57 + 10T

16 15/42 + 5T 15/42 + 5T 23/42 + 5T 23/42 + 5T

8 EA + 16/63 + 10T

16 EA + 16/43 + 5T EA + 18 + T/43 + 5T EA + 24/43 + 5T EA + 26 + T/43 + 5T

8 17/64 + 10T 17/64 + 10T 25/59 + 10T 25/59 + 10T

16 17/44 + 5T 17/44 + 5T 25/44 + 5T 25/44 + 5T

8 EA + 18/65 + 10T

16 EA + 18/45 + 5T EA + 20 + T/45 + 5T EA + 26/45 + 5T EA + 28 + T/45 + 5T

8 17/64 + 10T 17/64 + 10T 25/59 + 10T 25/59 + 10T

16 17/44 + 5T 17/44 + 5T 25/44 + 5T 25/44 + 5T

8 EA + 18/65 + 10T

16 EA + 18/45 + 5T EA + 20 + T/45 + 5T EA + 26/45 + 5T EA + 28 + T/45 + 5T

EA + 18 + T/63 + 10T

EA + 18 + T/63 + 5T

EA + 18 + T/63 + 10T

EA + 20 + T/65 + 10T

EA + 24/58 + 10T

EA + 24/43 + 5T EA + 26 + T/43 + 5T

EA + 24/58 + 10T

EA + 26/60 + 10T

EA + 30 + 2T/58 + 10T

EA + 31 + 2T/60 + 10T

ADJBA

ADJ4A –– 3 3 –– ––

ADJBS

BCD adjustment instructions

ADJ4S –– 3 3 –– ––

CVTBD –– 18 18 –– ––

CVTDB –– 8 8 –– ––

CVTBW –– 3 3 –– ––

instructions

Data conversion

CVTWL –– –– –– 3 3

16 9

86 6

16 9 9

9––––

–– ––

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Remark Figures on right of / (slash) apply in case of a divide error.

Page 94

Mnemonic Operands

Group

Instruction

reg, reg' –– 3 3 3 3

Table 17-9. Number of Clock Cycles (10/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem, reg EA + 4 EA + 6 + T EA + 4

CMP

Comparison instructions

NOT

instructions

NEG

Complement operation

reg, mem EA + 2 EA + 6 + T EA + 2

reg, imm –– 2 2 2 2

mem, imm EA + 4 EA + 6 + T EA + 4

acc, imm –– 2 2 2 2

reg –– 2 2 2 2

mem EA + 3 EA + 7 + T EA + 3

reg –– 2 2 2 2

mem EA + 3 EA + 7 + T EA + 3

reg, reg' –– 3 3 3 3

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

mem, reg/ reg, mem

TEST

Logical operation instructions

AND

reg, imm –– 2 2 2 2

mem, imm EA + 4 EA + 6 + T EA + 4

acc, imm –– 2 2 2 2

reg, reg' –– 3 3 3 3

mem, reg EA + 4 EA + 7 + T EA + 4

reg, mem EA + 2 EA + 6 + T EA + 2

reg, imm –– 2 2 2 2

mem, imm EA + 4 EA + 7 + T EA + 4

acc, imm –– 2 2 2 2

8 EA + 9 + 2T

EA + 4 EA + 6 + T EA + 4

16 EA + 6 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 10 + 2T

16 EA + 7 + T

* 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Page 95

Mnemonic Operands

Group

Instruction

reg, reg' –– 3 3 3 3

Table 17-9. Number of Clock Cycles (11/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem, reg EA + 4 EA + 7 + T EA + 4

reg, mem EA + 2 EA + 6 + T EA + 2

OR 16 EA + 6 + T

reg, imm –– 2 2 2 2

mem, imm EA + 4 EA + 7 + T EA + 4

acc, imm –– 2 2 2 2

reg, reg' –– 3 3 3 3

mem, reg EA + 4 EA + 7 + T EA + 4

Logical operation instructions

reg, mem EA + 2 EA + 6 + T EA + 2

XOR 16 EA + 6 + T

reg, imm –– 2 2 2 2

mem, imm EA + 4 EA + 7 + T EA + 4

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 9 + 2T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 9 + 2T

8 EA + 10 + 2T

16 EA + 7 + T

acc, imm –– 2 2 2 2

reg8, CL –– 3 3 3 3

mem8, CL EA + 4 EA + 6 + T EA + 4

reg16, CL –– 3 3 3 3

mem16, CL EA + 4 EA + 6 + T EA + 4

TEST1

reg8, imm3 –– 2 2 2 2

mem8, imm3 EA + 4 EA + 6 + T EA + 4

Bit manipulation instructions

reg16, imm4 –– 2 2 2 2

mem16, imm4 EA + 4 EA + 6 + T EA + 4

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 9 + 2T

16 EA + 6 + T

8 EA + 9 + 2T

16 EA + 6 + T

* 8 : 8-bit width 16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Page 96

Mnemonic Operands

Group

Instruction

reg8, CL –– 3 3 3 3

Table 17-9. Number of Clock Cycles (12/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem8, CL EA + 4 EA + 7 + T EA + 4

reg16, CL –– 3 3 3 3

mem16, CL EA + 4 EA + 7 + T EA + 4

NOT1 reg8, imm3 –– 2 2 2 2

mem8, imm3 EA + 4 EA + 7 + T EA + 4

reg16, imm4 –– 2 2 2 2

mem16, imm4

CY––2222

reg8, CL –– 3 3 3 3

Bit manipulation instructions

mem8, CL EA + 4 EA + 7 + T EA + 4

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

EA + 4 EA + 7 + T EA + 4

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

reg16, CL –– 3 3 3 3

mem16, CL EA + 4 EA + 7 + T EA + 4

CLR1 reg8, imm3 –– 2 2 2 2

mem8, imm3 EA + 4 EA + 7 + T EA + 4

reg16, imm4 –– 2 2 2 2

mem16, imm4

CY––2222

DIR –– 2 2 2 2

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

EA + 4 EA + 7 + T EA + 4

16 EA + 7 + T

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Page 97

Mnemonic Operands

Group

Instruction

reg8, CL –– 3 3 3 3

Table 17-9. Number of Clock Cycles (13/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem8, CL EA + 4 EA + 7 + T EA + 4

reg16, CL –– 3 3 3 3

mem16, CL EA + 4 EA + 7 + T EA + 4

reg8, imm3 –– 2 2 2 2

SET1

mem8, imm3 EA + 4 EA + 7 + T EA + 4

reg16, imm4 –– 2 2 2 2

Bit manipulation instructions

mem16, imm4

CY––2222

DIR –– 2 2 2 2

mem

BSCH 16 EA + 8 + 3n + T EA + 8 + 3n + T EA + 8 + 3n + T EA + 8 + 3n + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

16 EA + 7 + T

8 EA + 10 + 2T

EA + 4 EA + 7 + T EA + 4

16 EA + 7 + T

8 EA + 8 + 3n + T EA + 8 + 3n + T EA + 11 + 3n + 2T EA + 11 + 3n + 2T

reg –– 4 + 3n 4 + 3n 4 + 3n 4 + 3n

reg, 1 –– 3 3 3 3

mem, 1 EA + 3 EA + 7 + T EA + 3

reg, CL –– 5 + n 5 + n 5 + n 5 + n

SHL 8 EA + 11 + 2T + n

mem, CL EA + 5 + n EA + 8 + T + n EA + 6 + n

Shift instructions

reg, imm8 –– 5 + n 5 + n 5 + n 5 + n

mem, imm8 EA + 6 + n EA + 8 + T + n EA + 6 + n

8 EA + 10 + 2T

16 EA + 7 + T

16 EA + 8 + T + n

8 EA + 11 + 2T + n

16 EA + 8 + T + n

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Remark Number of shifts (n in a bit manipulation instruction indicates the bit number searched for)

Page 98

Mnemonic Operands

Group

Instruction

reg, 1 –– 3 3 3 3

Table 17-9. Number of Clock Cycles (14/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem, 1 EA + 3 EA + 7 + T EA + 3

reg, CL –– 5 + n 5 + n 5 + n 5 + n

SHR 8 EA + 11 + 2T + n

mem, CL EA + 5 + n EA + 8 + T + n EA + 6 + n

reg, imm8 –– 5 + n 5 + n 5 + n 5 + n

mem, imm8 EA + 6 + n EA + 8 + T + n EA + 6 + n

reg, 1 –– 3 3 3 3

Shift instructions

mem, 1 EA + 3 EA + 7 + T EA + 3

reg, CL –– 5 + n 5 + n 5 + n 5 + n

SHRA 8 EA + 11 + 2T + n

mem, CL EA + 5 + n EA + 8 + T + n EA + 6 + n

reg, imm8 –– 5 + n 5 + n 5 + n 5 + n

8 EA + 10 + 2T

16 EA + 7 + T

16 EA + 8 + T + n

8 EA + 11 + 2T + n

16 EA + 8 + T + n

8 EA + 10 + 2T

16 EA + 7 + T

16 EA + 8 + T + n

mem, imm8 EA + 6 + n EA + 8 + T + n EA + 6 + n

reg, 1 –– 3 3 3 3

mem, 1 EA + 3 EA + 7 + T EA + 3

reg, CL –– 5 + n 5 + n 5 + n 5 + n

ROL 8 EA + 11 + 2T + n

mem, CL EA + 5 + n EA + 8 + T + n EA + 6 + n

Rotate instructions

reg, imm8 –– 5 + n 5 + n 5 + n 5 + n

mem, imm8 EA + 6 + n EA + 8 + T + n EA + 6 + n

8 EA + 11 + 2T + n

16 EA + 8 + T + n

8 EA + 10 + 2T

16 EA + 7 + T

16 EA + 8 + T + n

8 EA + 11 + 2T + n

16 EA + 8 + T + n

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Remark Number of shifts (n in a bit manipulation instruction indicates the bit number searched for)

Page 99

Mnemonic Operands

Group

Instruction

reg, 1 –– 3 3 3 3

Table 17-9. Number of Clock Cycles (15/20)

Byte Processing Word Processing

On-Chip Other On-Chip Other

RAM Access Access RAM Access Access

Bus Width*

PD70433

mem, 1 EA + 3 EA + 7 + T EA + 3

reg, CL –– 5 + n 5 + n 5 + n 5 + n

ROR 8 EA + 11 + 2T + n

mem, CL EA + 5 + n EA + 8 + T + n EA + 6 + n

reg, imm8 –– 5 + n 5 + n 5 + n 5 + n

mem, imm8 EA + 6 + n EA + 8 + T + n EA + 6 + n

reg, 1 –– 3 3 3 3

mem, 1 EA + 3 EA + 7 + T EA + 3

reg, CL –– 5 + n 5 + n 5 + n 5 + n

ROLC 8 EA + 11 + 2T + n

mem, CL EA + 5 + n EA + 8 + T + n EA + 6 + n

Rotate instructions

reg, imm8 –– 5 + n 5 + n 5 + n 5 + n

8 EA + 10 + 2T

16 EA + 7 + T

16 EA + 8 + T + n

8 EA + 11 + 2T + n

16 EA + 8 + T + n

8 EA + 10 + 2T

16 EA + 7 + T

16 EA + 8 + T + n

mem, imm8 EA + 6 + n EA + 8 + T + n EA + 6 + n

reg, 1 –– 3 3 3 3

mem, 1 EA + 3 EA + 7 + T EA + 3

reg, CL –– 5 + n 5 + n 5 + n 5 + n

RORC 8 EA + 11 + 2T + n

mem, CL EA + 5 + n EA + 8 + T + n EA + 6 + n

reg, imm8 –– 5 + n 5 + n 5 + n 5 + n

mem, imm8 EA + 6 + n EA + 8 + T + n EA + 6 + n

8 EA + 11 + 2T + n

16 EA + 8 + T + n

8 EA + 10 + 2T

16 EA + 7 + T

16 EA + 8 + T + n

8 EA + 11 + 2T + n

16 EA + 8 + T + n

* 8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

Remark Number of shifts

Page 100

Mnemonic Operands

Group

Instruction

near-proc –– –– ––

PD70433

Table 17-9. Number of Clock Cycles (16/20)

RAM Access Access RAM Access Access

Bus Width

8 19 + 2T

16 16 + T

Byte Processing Word Processing

On-Chip Other On-Chip Other

regptr16 –– –– ––

CALL memptr16 –– ––

far-proc –– –– ––

memptr32 –– ––

Subroutine control instructions

pop-value –– –– ––

RET

*2 –– –– ––

pop-value*2 –– –– ––

8 18 + 2T

16 15 + T

8 EA + 19 + 2T EA + 24 + 4T

16 EA + 16 + T EA + 18 + 2T

8 29 + 4T

16 23 + 2T

8 EA + 32 + 4T EA + 44 + 8T

16 EA + 26 + 2T EA + 32 + 4T

8 18 + 2T

–– –– ––

16 15 + T

8 19 + 2T

16 16 + T

8 26 + 4T

16 20 + 2T

8 27 + 4T

16 21 + 2T

mem16 –– –– EA + 7

reg16 –– –– –– –– 7

sreg –– –– –– –– 7

xsreg/VPC –– –– –– –– 7

PUSH

PSW –– –– –– –– 6

R––––––

Stack manipulation instructions

imm8 –– –– –– –– 6

imm16 –– –– –– –– 6

*1.8 : 8-bit width

16 : 16-bit width –– : Both 8-bit and 16-bit bus width

2. Segment-external

Remark n: Number of shifts

100

8 EA + 13 + 2T

16 EA + 10 + T

8 57 + 14T

16 36 + 7T

Datasheet UPD70433R-12, UPD70433R-16, UPD70433GJ-16-3EB, UPD70433GJ-12-3EB, UPD70433GD-16-5BB Datasheet (NEC)

Specifications and Main Features

Frequently Asked Questions

User Manual

DESCRIPTION

FEATURES

APPLICATIONS

ORDERING INFORMATION

PIN CONFIGURATION (TOP VIEW)

INTERNAL BLOCK DIAGRAM

1. PIN FUNCTIONS

1.1 LIST OF PIN FUNCTIONS

1.1.1 Port Pins

1.1.2 Non-Port Pins

2. BLOCK CONFIGURATION

2.1 BUS CONTROL UNIT (BCU)

2.2 EXECUTION UNIT (EXU)

2.3 INTERRUPT CONTROLLER (INTC)

2.4 DMA CONTROLLER (DMAC)

2.5 UART/CLOCKED SERIAL INTERFACE (UART/CSI)

2.6 PARALLEL INTERFACE UNIT (PIU)

2.7 A/D CONVERTER UNIT (8-BIT A/D)

2.8 TIMER/COUNTER UNIT (TCU)

2.9 PWM (PULSE WIDTH MODULATION) UNIT (PWM)

2.10 WATCHDOG TIMER (WDT)

2.11 PORTS (PORT)

2.12 REAL-TIME OUTPUT PORT (RTOP)

2.13 CLOCK GENERATOR (CG)

2.14 SOFTWARE INTERVAL TIMER (SIT)

3. CPU FUNCTIONS

3.1 FEATURES

3.2 REGISTERS

3.2.1 Register Banks

3.2.2 General Registers (AW, BW, CW, DW)

3.2.3 Pointers (SP, BP) and Index Registers (IX, IY)

3.2.4 Segment Registers (PS, SS, DS0, DS1)

3.2.5 Extended Segment Registers (DS2, DS3)

3.2.6 Special Function Registers (SFR)

3.3 PROGRAM COUNTER (PC)

3.4 PROGRAM STATUS WORDS (PSW)

3.5 MEMORY SPACE

3.5.1 Basic Memory Space

3.5.2 Extended Memory Space

3.5.3 Special Function Register Area

3.5.4 Vector Table Area

3.6 REGISTER FILE SPACE

3.7 I/O SPACE

4. BUS CONTROL FUNCTIONS

4.1 WAIT FUNCTION

4.2 REFRESH FUNCTION

4.2.1 Refresh Mode Register (RFM)

4.2.2 Wait Control in Refresh Cycle

4.2.3 Refresh Address

5. INTERRUPT FUNCTIONS

5.1 FEATURES

5.2 INTERRUPT RESPONSE METHODS

5.2.1 Vectored Interrupts

5.2.2 Register Bank Switching Function

5.2.3 Macro Service Function

6. DMA FUNCTION (DMA CONTROLLER)

6.1 FEATURES

7. SERIAL INTERFACE FUNCTIONS

7.1 FEATURES

7.2 PROTOCOLS

7.3 UART

7.3.1 Features

7.4 CLOCKED SERIAL INTERFACE (CSI)

7.4.1 Features

8. PARALLEL INTERFACE FUNCTIONS

8.1 FEATURES

9. TIMER FUNCTION

9.1 FEATURES

9.2 TIMER UNIT CONFIGURATION

9.3 REAL-TIME OUTPUT PORT FUNCTION

9.3.1 Real-Time Output Port Configuration

9.3.2 Real-Time Output Port Operation

10. PWM UNIT

10.1 FEATURES

10.2 PWM UNIT CONFIGURATION

11. WATCHDOG TIMER FUNCTION