Datasheet UPD6P4BMC-5A4, UPD6P4BGS Datasheet (NEC)

Download

Page 1

DATA SHEET

MOS INTEGRATED CIRCUIT

PD6P4B

4-BIT SINGLE-CHIP MICROCONTROLLER

FOR INFRARED REMOTE CONTROL TRANSMISSION

DESCRIPTION

The µPD6P4B is a microcontroller for infrared remote control transmitters which is provided with a one-time

PROM as the program memory.

Because users can write programs for the µPD6P4B, it is ideal for program evaluation and small-scale production

of the application systems using the

When reading this document, also refer to the µPD62 Data Sheet (U14208E) and the µPD63, 63A, 64 Data

Sheet (U11371E).

PD62, 63, 63A, or 64.

FEATURES

• Program memory (one-time PROM): 1002 × 10 bits

• Data memory (RAM) : 32 × 4 bits

• Built-in carrier generation circuit for infrared remote control

• 9-bit programmable timer : 1 channel

• Command execution time : 16

• Stack level : 1 level (Stack RAM is for data memory RF as well.)

• I/O pins (KI/O) : 8 units

• Input pins (K

• Sense input pin (S0) : 1 unit

•S1/LED pin (I/O) : 1 unit (In output mode, this is the remote control transmission display

• Power supply voltage : V

• Operating ambient temperature : T

• Oscillator frequency : fX = 2.4 to 8 MHz

• POC circuit

APPLICATION

Infrared remote control transmitter (for AV and household electric appliances)

I) : 4 units

s (when operating at fX = 4 MHz: ceramic oscillation)

pin.)

DD = 2.2 to 3.6 V (at fX = 4 MHz)

VDD = 2.7 to 3.6 V (at fX = 8 MHz)

A = –40 to +85 °C

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. U13594EJ2V0DS00 (2nd edition) Date Published May 1999 N CP(K) Printed in Japan

The mark shows major revised points.

1998,1999

Page 2

ORDERING INFORMATION

Part Number Package

PD6P4BGS 20-pin plastic SOP (300 mil)

PD6P4BMC-5A4 20-pin plastic SSOP (300 mil)

PIN CONFIGURATION (TOP VIEW)

20-pin Plastic SOP (300 mil)

• µPD6P4BGS 20-pin Plastic SSOP (300 mil)

PD6P4BMC-5A4

•

(1) Normal operating mode

PD6P4B

I/O6

KI/O7

S1/LED

REM

XOUT

XIN

GND

RESET

1 2 3 4 5

6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

I/O5

KI/O4 KI/O3 KI/O2 KI/O1 KI/O0 KI3 KI2 KI1 KI0

Data Sheet U13594EJ2V0DS00

Page 3

(2) PROM programming mode

D D

CLK

(L)

OUT

GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

D D D D D D MD MD MD MD

Caution Round brackets ( ) indicate the pins not used in the PROM programming mode.

L : Connect each of these pins to GND via a pull-down resistor.

PD6P4B

BLOCK DIAGRAM

CARRIER GENERATOR

REM

/LED

9-bit TIMER

CPU CORE

RAM

ONETIME PROM

PORT K

I/O

PORT S

SYSTEM CONTROL

KI0-K

I/O0-KI/O7

S0, S1/LED

RESET

X X

OUT

GND

Data Sheet U13594EJ2V0DS00

Page 4

LIST OF FUNCTIONS

PD6P4B

Item

ROM capacity 1002 × 10 bits

One-time PROM RAM capacity 32 × 4 bits Stack 1 level (shared with RF of RAM) I/O pin Key input (KI) : 4 pins

Key I/O (KI/O) : 8 pins

Key expansion input (S0, S1) : 2 pins

Remote control transmitter display output (LED) : 1 pin (shared with S1 pin) Number of keys 32 keys

48 keys (when expanded by key expansion input)

96 keys (when expanded by key expansion input and diode) Clock frequency Ceramic oscillation

fX = 2.4 to 4 MHz

fX = 4 to 8 MHz Instruction execution time 16 µs (at fX = 4 MHz) Carrier frequency fX/8, fX/16, fX/64, fX/96, fX/128, fX/192, no carrier (high level) Timer 9-bit programmable timer : 1 channel POC circuit Provided

Note

PD6P4B

Supply voltage VDD = 2.2 to 3.6 V (fX = 2.4 to 4 MHz), VDD = 2.7 to 3.6 V (fX = 4 to 8 MHz) Operating ambient • TA = –40 to +85 °C

temperature • TA = –20 to +70 °C (when using POC circuit) Package • 20-pin plastic SOP (300 mil)

• 20-pin plastic SSOP (300 mil)

Note It is necessary to design the application circuit so that the RESET pin goes low at a supply voltage of less

than 2.7 V.

Data Sheet U13594EJ2V0DS00

Page 5

PD6P4B

TABLE OF CONTENTS

1. PIN FUNCTIONS......................................................................................................................... 6

1.1 Normal Operating Mode.................................................................................................................... 6

1.2 PROM Programming Mode............................................................................................................... 7

1.3 INPUT/OUTPUT Circuits of Pins ...................................................................................................... 8

1.4 Dealing with Unused Pins ................................................................................................................ 9

1.5 Notes on Using K

I Pin at Reset ........................................................................................................ 9

2. DIFFERENCES AMONG µPD62, 63, 63A, 64, AND µPD6P4B ................................................. 10

2.1 Program Memory (One-time PROM) ................................................................................................ 11

3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................. 12

3.1 Operating Mode When Writing/Verifying Program Memory.......................................................... 12

3.2 Program Memory Writing Procedure .............................................................................................. 13

3.3 Program Memory Reading Procedure.............................................................................................14

4. ELECTRICAL SPECIFICATIONS............................................................................................... 15

5. CHARACTERISTIC CURVE (REFERENCE VALUES) .............................................................. 21

6. APPLIED CIRCUIT EXAMPLE ................................................................................................... 23

7. PACKAGE DRAWINGS..............................................................................................................24

8. RECOMMENDED SOLDERING CONDITIONS.......................................................................... 26

APPENDIX A. DEVELOPMENT TOOLS ........................................................................................ 27

APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT .......................... 28

Data Sheet U13594EJ2V0DS00

Page 6

PD6P4B

1. PIN FUNCTIONS

1.1 Normal Operating Mode

Pin No. Symbol Function Output Format When Reset

1KI/O0-KI/O7 CMOS High-level output 2 push-pull 15-20

3S0 — High-impedance

4S1/LED CMOS push-pull High-level output

5 REM CMOS push-pull Low-level output

6VDD —— 7XOUT — Low level

8XIN (oscillation stopped) 9 GND —— 10 RESET ——

11-14 KI0-KI3

These pins refer to the 8-bit I/O ports. I/O switching can be made in 8-bit units. In INPUT mode, a pull-down resistor is added. In OUTPUT mode, they can be used as the key scan output of the key matrix.

Refers to the input port. Can also be used as the key return input of the key matrix. In INPUT mode, the availability of the pull-down resistor of the S0 and S1 ports can be specified by software in terms in 2-bit units. If INPUT mode is canceled by software, this pin is placed in OFF mode and enters the high-impedance state.

Refers to the I/O port. In INPUT mode (S1), this pin can also be used as the key return input of the key matrix. The availability of the pull-down resistor of the S0 and S1 ports can be specified by software in 2-bit units. In OUTPUT mode (LED), it becomes the remote control transmission display output (active low). When the remote control carrier is output from the REM output, this pin outputs the low level from the LED output synchronously with the REM signal.

Refers to the infrared remote control transmission output. The output is active high. Carrier frequency: fX/8, fX/64, fX/96, high-level,

fX/16, fX/128, fX/192 (usable on software) Refers to the power supply. These pins are connected to system clock ceramic

resonators. Refers to the ground.

Normally, this pin is a system reset input. By inputting a low level, the CPU can be reset. When resetting with the POC circuit a low level is output. A pull-up resistor is incorporated.

Note 2

These pins refer to the 4-bit input ports. They can be used as the key return input of the key matrix. The use of the pull-down resistor can be specified by software in 4-bit units.

Note 1

(OFF mode)

(LED)

— Input (low-level)

Notes 1. Be careful about this because the drive capability of the low-level output side is held low.

2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when

reset is released (when RESET pin changes from low level to high level, or POC is released due to supply voltage startup).

Data Sheet U13594EJ2V0DS00

Page 7

1.2 PROM Programming Mode

Pin No. Symbol Function I/O

1, 2 D0-D7 8-bit data input/output when writing/verifying program memory I/O 15-20

3 CLK Clock input for updating address when writing/verifying program Input

memory

6VDD Power Supply. –

Supply +6 V to this pin when writing/verifying program memory. 7XOUT Clock necessary for writing program memory. Connect 4 MHz ceramic – 8XIN resonator to these pins. Input 9 GND GND – 10 VPP Supplies voltage for writing/verifying program memory. –

Apply +12.5 V to this pin. 11-14 MD0-MD3 Input for selecting operation mode when writing/verifying program memory. Input

PD6P4B

Data Sheet U13594EJ2V0DS00

Page 8

1.3 INPUT/OUTPUT Circuits of Pins

The input/output circuits of the µPD6P4B pins are shown in partially simplified forms below.

I/O0-KI/O7 (4) S0

(1) K

data

Output latch

P-ch

Input buffer

PD6P4B

output

disable

Selector

Input buffer

Note The drive capability is held low.

I0-KI3

(2) K

standby

release

Input buffer

pull-down flag

N-ch

Note

N-ch

standby

release

REM output latch

pull-down flag

(5) S1/LED

output

disable

standby

release

pull-down flag

OFF mode

Input buffer

N-ch

P-ch

N-ch

(3) REM (6) RESET

VDD

P-ch

data

Output latch

N-ch

Carrier generator

Internal reset signal

other than POC

Data Sheet U13594EJ2V0DS00

POC circuit

Input buffer

P-ch

N-ch

Page 9

1.4 Dealing with Unused Pins

The following connections are recommended for unused pins in the normal operation mode.

Table 1-1. Connections for Unused Pins

PD6P4B

KI/O INPUT mode — Open

OUTPUT mode High-level output REM — S1/LED OUTPUT mode (LED) setting S0 OFF mode setting Directly connected to GND KI —

Note

RESET

Inside the microcontroller Outside the microcontroller

Built-in POC circuit Open

Connection

Note If the circuit is an applied one requiring high reliability, be sure to design it in such a manner that the RESET

signal is entered externally.

Caution The I/O mode and the terminal output level are recommended to be fixed by setting them

repeatedly in each loop of the program.

1.5 Notes on Using KI Pin at Reset

In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is

released (when RESET pin changes from low level to high level, or POC is released due to supply voltage startup).

Data Sheet U13594EJ2V0DS00

Page 10

PD6P4B

2. DIFFERENCES AMONG µPD62, 63, 63A, 64, AND µPD6P4B

Table 2-1 shows the differences among the µPD62, 63, 63A, 64, and µPD6P4B.

The only differences among these models are the program memory, supply voltage, system clock frequency, oscillation stabilization wait time, and POC circuit (mask option), and the CPU function and internal peripheral hardware are the same.

The electrical characteristics also differ slightly. For the electrical characteristics, refer to the Data Sheet of each model.

Table 2-1. Differences among

(1) When POC circuit (mask option) is provided to

PD62, 63, 63A, 64, and µPD6P4B

PD62, 63, 63A, and 64

Item

ROM One-time PROM Mask ROM

Oscillation stabilization wait time

• On releasing STOP mode by release 286/fX 52/fX condition

• On releasing STOP or HALT mode by 478/fX to 926/fX 246/fX to 694/fX RESET input and at reset

VPP pin and operating mode select pin Provided Not provided Electrical specifications Some electrical specifications, such as data retention voltage and current

PD6P4B

1002 × 10 bits 512 × 10 bits 768 × 10 bits 1002 × 10 bits (000H to 3E9H) (000H to 1FFH) (000H to 2FFH) (000H to 3E9H)

consumption, differ. For details, refer to Data Sheet of each model.

PD62, 63

PD63A

PD64

(2) When POC circuit (mask option) is not provided to µPD62, 63, 63A, and 64

Item

ROM One-time PROM Mask ROM

Oscillation stabilization wait time

• On releasing STOP mode by release 286/fX 52/fX condition

• On releasing STOP or HALT mode by 478/fX to 926/fX 246/fX to 694/fX RESET input and at reset

VPP pin and operating mode select pin Provided Not provided POC circuit Incorporated Not provided Supply voltage

System clock frequency

Electrical specifications Some electrical specifications, such as data retention voltage and current

PD6P4B

1002 × 10 bits 512 × 10 bits 768 × 10 bits 1002 × 10 bits (000H to 3E9) (000H to 1FFH) (000H to 2FFH) (000H to 3E9H)

VDD = 2.2 to 3.6 V (TA = –40 to +85 °C)

•fX = 2.4 to 4 MHz

•fX = 4 to 8 MHz

consumption, differ. For details, refer to Data Sheet of each model.

PD62, 63

VDD = 1.8 to 3.6 V (TA = –40 to +85 °C)

•fX = 2.4 to 4 MHz

Note

• fX = 2.4 to 8 MHz (VDD = 2.2 to 3.6 V)

PD63A

PD64

Note It is necessary to design the application circuit so that the RESET pin goes low when the supply voltage

is less than 2.7 V.

Data Sheet U13594EJ2V0DS00

Page 11

PD6P4B

2.1 Program Memory (One-time PROM) ... 1002 steps × 10 bits

This one-time PROM is configured with 10 bits per step and is addressed by the program counter. The program memory stores programs and table data. The 22 steps from addresses 3EAH through 3FFH constitute a test program area and must not be used.

Figure 2-1. Program Memory Map

10 bits

000H

3E9H

3EAH

3FFH

Note Even if execution jumps to the test program area by mistake, it returns to address 000H.

Test program area

Note

Data Sheet U13594EJ2V0DS00

Page 12

3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)

The program memory of the µPD6P4B is a one-time PROM of 1002 × 10 bits. To write or verify this program memory, the pins shown in Table 3-1 are used. Note that no address input pin

is used. Instead, the address is updated by using the clock input from the CLK pin.

Table 3-1. Pins Used to Write/Verify Program Memory

Pin Name Function

VPP Supplies voltage when writing/verifying program memory.

Apply +12.5 V to this pin.

VDD Power supply.

Supply +6 V to this pin when writing/verifying program memory.

CLK Inputs clock to update address when writing/verifying program memory.

By inputting pulse four times to CLK pin, address of program memory is updated. MD0-MD3 Input to select operation mode when writing/verifying program memory. D0-D7 Inputs/outputs 8-bit data when writing/verifying program memory. XIN, XOUT Clock necessary for writing program memory. Connect 4 MHz ceramic resonator to this pin.

PD6P4B

3.1 Operating Mode When Writing/Verifying Program Memory

The µPD6P4B is set in the program memory write/verify mode when +6 V is applied to the VDD pin and +12.5 V is applied to the VPP pin after the µPD6P4B has been in the reset status (VDD = 5 V, VPP = 0 V) for a specific time. In this mode, the operating modes shown in Table 3-2 can be set by setting the MD all the pins other than those shown in Table 3-1 to GND via pull-down resistor.

Table 3-2. Setting Operation Mode

Setting of Operating Mode Operation Mode

VPP VDD MD0 MD1 MD2 MD3

+12.5 V +6 V H L H L Clear program address to 0

L H H H Write mode L L H H Verify mode H × H H Program inhibit mode

×: don’t care (L or H)

0 through MD3 pins. Connect

Data Sheet U13594EJ2V0DS00

Page 13

Repeated X time

Reset

Oscillation stabilization

wait time

Write Verify Additional write

Address

increment

Data input

Hi-Z Hi-Z Hi-Z

Data output

Data input

Hi-Z

VPP VDD

GND

DD+1

VDD

GND

CLK

VDD

D0-D7

MD0

MD1

MD2

MD3

PD6P4B

3.2 Program Memory Writing Procedure

The program memory is written at high speed in the following procedure.

(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the V (3) Supply 5 V to the V (4) Wait for 2 ms until oscillation of the ceramic resonator connected across the XIN and XOUT pins stabilizes. (5) Set the program memory address 0 clear mode by using the mode setting pins. (6) Supply 6 V to V (7) Set the program inhibit mode. (8) Write data to the program memory in the 1-ms write mode. (9) Set the program inhibit mode. (10) Set the verify mode. If the data have been written to the program memory, proceed to (11). If not, repeat

steps (8) through (10). (11) Additional writing of (number of times of writing in (8) through (10): X) × 1 ms. (12) Set the program inhibit mode. (13) Input a pulse to the CLK pin four times to update the program memory address (+1). (14) Repeat steps (8) through (13) up to the last address. (15) Set the 0 clear mode of the program memory address. (16) Change the voltages on the V (17) Turn off power.

DD pin. Keep the VPP pin low. PP pin after waiting for 10

DD and 12.5 V to VPP.

DD and VPP pins to 5 V.

The following figure illustrates steps (2) through (13) above.

Data Sheet U13594EJ2V0DS00

Page 14

3.3 Program Memory Reading Procedure

(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the V DD pin. Keep the VPP pin low. (3) Supply 5 V to the VPP pin after waiting for 10 µs. (4) Wait for 2 ms until oscillation of the ceramic resonator connected across the X (5) Set the program memory address 0 clear mode by using the mode setting pins. (6) Supply 6 V to VDD and 12.5 V to V PP. (7) Set the program inhibit mode. (8) Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to

the CLK pin four times. (9) Set the program inhibit mode. (10) Set the program memory address 0 clear mode. (11) Change the voltage on the V

DD and VPP pins to 5 V.

(12) Turn off power.

The following figure illustrates steps (2) through (10) above.

Oscillation stabilization

Reset

GND

wait time

IN and XOUT pins stabilizes.

PD6P4B

GND

CLK

D0-D

Hi-Z Hi-Z

"L"

Data output Data output

Data Sheet U13594EJ2V0DS00

Page 15

PD6P4B

4. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = +25 °C)

Parameter Symbol Test Conditions Rating Unit

Power supply voltage VDD –0.3 to +7.0 V

VPP –0.3 to +13.5 V Input voltage VI KI/O, KI, S0, S1, RESET –0.3 to VDD + 0.3 V Output voltage VO –0.3 to VDD + 0.3 V High-level output current IOH

Low-level output current IOL

Operating ambient TA –40 to +85 °C temperature

Storage temperature Tstg –65 to +150 °C

Note

REM Peak value –30 mA

rms –20 mA

LED Peak value –7.5 mA

rms –5 mA

One KI/O pin Peak value –13.5 mA

rms –9 mA

Total of LED and KI/O pins Peak value –18 mA

rms –12 mA

Note

REM Peak value 7.5 mA

rms 5 mA

LED Peak value 7.5 mA

rms 5 mA

Note Work out the rms with: [rms] = [Peak value] × Duty.

Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even momen-

tarily. In other words, an absolute maxumum rating is a value at which the possibility of psysical damage to the product cannnot be ruled out. Care must therefore be taken to ensure that the these ratings are not exceeded during use of the product.

Recommended Power Supply Voltage Range (T

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Power supply voltage VDD fX = 2.4 to 4 MHz 2.2 3.0 3.6 V

fX = 4 to 8 MHz

A = –40 to +85 °C)

Note

2.7 3.0 3.6 V

Note It is necessary to design the application circuit so that the RESET pin goes low when the supply voltage

is less than 2.7 V.

Data Sheet U13594EJ2V0DS00

Page 16

DC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

High-level input voltage VIH1 RESET 0.8 VDD VDD V

VIH2 KI/O 0.65 VDD VDD V VIH3 KI, S0, S1 0.65 VDD VDD V

Low-level input voltage VIL1 RESET 0 0.2 VDD V

VIL2 KI/O 0 0.3 VDD V VIL3 KI, S0 , S1 0 0.15 VDD V

High-level input ILH1 KI 3 leakage current VI = VDD, pull-down resistor not incorporated

ILH2 S0, S1 3

VI = VDD, pull-down resistor not incorporated Low-level input leakage IUL1 KI VI = 0 V –3 current IUL2 KI/O VI = 0 V –3

IUL3 S0, S1 VI = 0 V –3 High-level output voltage VOH1 REM, LED, KI/O IOH = –0.3 mA 0.8 VDD V Low-level output voltage VOL1 REM, LED IOL = 0.3 mA 0.3 V

VOL2 KI/O IOL = 15 µA 0.4 V High-level output current IOH1 REM VDD = 3.0 V, VOH = 1.0 V –5 –9 mA

IOH2 KI/O VDD = 3.0 V, VOH = 2.2 V –2.5 –5 mA Low-level output current IOL1 KI/O VDD = 3.0 V, VOL = 0.4 V 30 70

VDD = 3.0 V, VOL = 2.2 V 100 220 Built-in pull-up resistor R1 RESET 25 50 100 k Ω Built-in pull-down resistor R 2 RESET 2.5 5 15 kΩ

R3 KI, S0, S1 75 150 300 k Ω R4 KI/O 130 250 500 k Ω

Data hold power supply VDDOR In STOP mode 1.2 3.6 V voltage

Supply current

Note

IDD1 Operating fX = 8 MHz, VDD = 3 V ± 10 % 1.4 2.8 mA

mode fX = 4 MHz, VDD = 3 V ± 10 % 1.1 2.2 mA

IDD2 HALT mode fX = 8 MHz, VDD = 3 V ± 10 % 1.3 2.6 mA

fX = 4 MHz, VDD = 3 V ± 10 % 1.0 2.0 mA

IDD3 STOP mode VDD = 3 V ± 10 % 1.0 8.0

VDD = 3 V ± 10 %, TA = 25 ˚C 1.0 2.0

PD6P4B

Note The POC circuit current and the current flowing in the built-in pull-up resistor are not included.

Data Sheet U13594EJ2V0DS00

Page 17

PD6P4B

AC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Instruction execution time tCY 15.9 27

VDD = 2.7 to 3.6 V

KI, S0, S1 high-level width tH 10

When canceling Standby mode HALT mode 10

RESET low-level width tRSL 10

Note 1

7.9 27

STOP mode Note 2

Notes 1. When using at fX = 4 MHz or higher, it is necessary to design the application circuit so that the RESET

pin goes low when the supply voltage is less than 2.7 V.

2. 10 + 286/f

X + oscillation growth time

Remark t

POC Circuit

POC-detected voltage POC circuit current IPOC 1.2 1.5

CY = 64/fX (fX: System clock oscillator frequency)

Note 1

(TA = –20 to +70 °C)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Note 2

VPOC 1.8 2.0 2.2 V

Notes 1. Operates effectively under the conditions of fX = 2.4 to 4 MHz.

2. Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal

reset is canceled. From the time of V

POC ≥ VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the

period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect.

System Clock Oscillator Characteristics (T

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Oscillator frequency fX 2.4 3.64 4.0 MHz (ceramic resonator) Note 2.4 3.64 8.0 MHz

A = –40 to +85 °C, VDD = 2.2 to 3.6 V)

Note When using at fX = 4 MHz or higher, it is necessary to design the application circuit so that the RESET

pin goes low when the supply voltage is less than 2.7 V.

An external circuit example

C1 C2

Data Sheet U13594EJ2V0DS00

OUT

Page 18

PROM Programming Mode

PD6P4B

DC Programming Characteristics (T

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

High-level input voltage VIH1 Other than CLK 0.7 VDD VDD V

VIH2 CLK VDD–0.5 VDD V

Low-level input voltage VIL1 Other than CLK 0 0.3 VDD V

VIL2 CLK 0 0.4 V Input leakage current ILI VIN = VIL or VIH 10 High-level output voltage VOH IOH = –1 mA VDD–1.0 V Low-level output voltage VOL IOL = 1.6 mA 0.4 V VDD supply current IDD 30 mA VPP supply current IPP MD0 = VIL, MD1 = VIH 30 mA

A = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V)

Cautions 1. Keep VPP to within +13.5 V including overshoot.

2. Apply VDD before VPP and turns it off after VPP.

Data Sheet U13594EJ2V0DS00

Page 19

PD6P4B

AC Programming Characteristics (TA = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V)

Parameter Symbol Note1 Test Conditions MIN. TYP. MAX. Unit Address setup time MD1 setup time (vs. MD0↓)tM1S tOES 2 Data setup time (vs. MD0↓)tDS tDS 2 Address hold time Data hold time (vs. MD0↑)tDH tDH 2 MD0↑→ data output float delay time tDF tDF 0 130 ns VPP setup time (vs. MD3↑)tVPS tVPS 2 VDD setup time (vs. MD3↑)tVDS tVCS 2 Initial program pulse width tPW tPW 0.95 1.0 1.05 ms Additional program pulse width tOPW tOPW 0.95 21.0 ms MD0 setup time (vs. MD1↑)tMOS tCES 2 MD0↓→ data output delay time tDV tDV MD0 = MD1 = VIL 1 MD1 hold time (vs. MD0↑)tM1H tOEH tM1H+tM1R ≥ 50 µs2 MD1 recovery time (vs. MD0↓)tM1R tOR 2 Program counter reset time tPCR –10 CLK input high-, low-level width tXH, tXL – 0.125 CLK input frequency fX – 8 MHz Initial mode set time tI –2 MD3 setup time (vs. MD1↑)tM3S –2 MD3 hold time (vs. MD1↓)tM3H –2 MD3 setup time (vs. MD0↓)tM3SR –

Note 2

Address Address MD3 hold time (vs. MD0↑)tM3HR – MD3↓→ data output float delay time tDFR – Reset setup time tRES –10 Oscillation stabilization wait time

Note 2

(vs. MD0↓)tAS tAS 2

Note 2

(vs. MD0↑)tAH tAH 2

→ data output delay time

→ data output hold time tHAD tOH

Note 3

tOAD tACC

tWAIT –2ms

When program memory is read When program memory is read When program memory is read When program memory is read When program memory is read

µ µ µ µ µ

µ µ

µ µ µ µ µ µ

µ µ µ

2 0 130 ns 2

µ µ

µ µ µ

s s s s s

s s

s s s s s s

s s s s s

s s s

Notes 1. Equivalent symbol of the corresponding µPD27C256A (The µPD27C256A is a maintenance product.)

2. The internal address signal is incremented at the falling edge of the third clock of CLK.

3. Connect a 4 MHz ceramic resonator between the X

Data Sheet U13594EJ2V0DS00

IN and XOUT pins.

Page 20

Program Memory Write Timing

WAIT

PCR

VPS

VDS

M3S

RES

GND

CLK

D0-D

Data input

M1S

PD6P4B

Data output

M1H

M1R

MOS

Data input Data input

OPW

Hi-ZHi-ZHi-ZHi-ZHi-Z

M3H

Program Memory Read Timing

WAIT

RES

GND

CLK

D0-D

PCR

Hi-Z

VPS

VDS

Data output

"L"

DAD

HAD

Data output

M3HR

Hi-Z

DFR

M3SR

Data Sheet U13594EJ2V0DS00

Page 21

5. CHARACTERISTIC CURVE (REFERENCE VALUES)

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2 0

12 343.62.2

IDD vs V

DD (fX

= 4 MHz)

Power supply current IDD [mA]

Power supply voltage VDD [V]

IOL vs V

(REM, LED)

Low-level output current IOL [mA]

Low-level output voltage VOL [V]

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2 0

12 343.62.2

IDD vs V

DD (fX

= 8 MHz)

Power supply current IDD [mA]

Power supply voltage VDD [V]

IOH vs V

(REM)

High-level output current IOH [mA]

High-level output voltage VOH [V]

IOH vs V

(LED)

High-level output current IOH [mA]

High-level output voltage VOH [V]

0.6 1.8 2.4 31.2

9 8 7 6 5 4 3 2 1

–20

VDD – 0.6 VDD – 1.8 VDD – 2.4 VDD – 3VDD – 1.2

–18 –16 –14 –12 –10

–8 –6 –4 –2

–10

VDD – 0.6 VDD – 1.8 VDD – 2.4 VDD – 3VDD – 1.2

–9 –8 –7 –6 –5 –4 –3 –2 –1

OPERATING mode

HALT mode

OPERATING mode

HALT mode

A = 25 °C )

A = 25 °C, VDD = 3.0 V)

A = 25 °C , VDD = 3.0 V)

A = 25 °C)

PD6P4B

Data Sheet U13594EJ2V0DS00

Page 22

PD6P4B

IOL vs VOL (KI/O

320

280

[ A]

240 200 160 120

Low-level output current I

0.6 1.8 2.4 31.2

Low-level output voltage VOL [V]

)

= 25 °C, VDD = 3.0 V) (TA = 25 °C, VDD = 3.0 V)

IOH vs VOH (KI/O

)

–15 –14 –13 –12

[mA]

–11

–10

–9 –8 –7 –6 –5 –4 –3

High-level output current I

–2 –1

0 V

–

0.6 V

–

1.8 V

–

1.2

–

High-level output voltage VOH [V]

2.4 V

–

Data Sheet U13594EJ2V0DS00

Page 23

6. APPLIED CIRCUIT EXAMPLE

Example of Application to System

• Remote-control transmitter (40 keys; mode selection switch accommodated)

I/O6

I/O7

S1/LED REM

I/O5

K K

I/O4

I/O3

I/O2

I/O1

PD6P4B

V X

OUT

GND RESET

I/O0

• Remote-control transmitter (48 keys accommodated)

I/O6

I/O7

S1/LED REM

I/O5

K K

I/O4

I/O3

I/O2

I/O1

Mode selection switch

Key matrix 8 × 5 = 40 keys

V X

OUT

GND RESET

I/O0

Key matrix 8 × 6 = 48 keys

Remark When the POC circuit is used effectively, it is not necessary to connect the capacitor enclosed in the

dotted lines.

Data Sheet U13594EJ2V0DS00

Page 24

7. PACKAGE DRAWINGS

20 PIN PLASTIC SOP (300 mil)

110

PD6P4B

1120

detail of lead end

NOTE

Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS INCHES

12.7±0.3

0.78 MAX.

1.27 (T.P.) D 0.42 0.017 E

F G H

I 5.6±0.2 0.220 J K 0.22

L 0.6±0.2 0.024

N P3° 3°

+0.08 –0.07

0.1±0.1

1.8 MAX.

1.55±0.05

7.7±0.3

1.1 +0.08

–0.07

0.12

0.10

+7° –3°

0.500±0.012

0.031 MAX.

0.050 (T.P.)

0.004±0.004

0.071 MAX.

0.061±0.002

0.303±0.012

0.043

0.009

0.005

0.004 +7°

–3°

P20GM-50-300B, C-5

+0.003 –0.004

+0.009 –0.008

+0.003 –0.004

+0.008 –0.009

Data Sheet U13594EJ2V0DS00

Page 25

20 PIN PLASTIC SSOP (300 mil)

20 11

detail of lead end

PD6P4B

110

NOTE

Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition.

L U

ITEM MILLIMETERS

6.65±0.15

A B

0.475 MAX.

0.65 (T.P.) D E

F G H

L M N

+0.08

0.24

−0.07

0.1±0.05

1.3±0.1

1.2

8.1±0.2

6.1±0.2

1.0±0.2

0.17±0.03

0.5

0.13

0.10 +5°

3°

−3°

0.25T

0.6±0.15U

S20MC-65-5A4-1

Data Sheet U13594EJ2V0DS00

Page 26

8. RECOMMENDED SOLDERING CONDITIONS

Carry out the soldered packaging of this product under the following recommended conditions. For details of the soldering conditions, refer to information material Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than the recommended conditions, please consult one of our NEC

sales representatives.

Table 8-1. Soldering Conditions for Surface-Mount Type

PD6P4BGS-×××: 20-pin plastic SOP (300 mil)

(1)

PD6P4B

Soldering Method Soldering Condition

Infrared reflow Package peak temperature: 235 °C, Time: 30 secs. max. (210 °C min.), IR35-00-2

Number of times: Twice max.

VPS Package peak temperature: 215 °C, Time: 40 secs. max. (200 °C min.), VP15-00-2

Number of times: Twice max.

Wave soldering Solder bath temperature: 260 °C max., Time: 10 secs. max., Number of times: once, WS60-00-1

Preheating temperature: 120 °C max. (package surface temperature.)

Partial heating Pin temperature: 300 °C or less ; time: 3 secs or less (for each side of the device) —

Recommended

Condition Symbol

Caution Do not use two or more soldering methods in combination (except partial heating).

PD6P4BMC-5A4: 20-pin plastic SSOP (300 mil)

(2)

Soldering Method Soldering Condition

Infrared reflow Package peak temperature: 235 °C, Time: 30 secs. max. (210 °C min.), IR35-00-3

Number of times: Three times max.

VPS Package peak temperature: 215 °C, Time: 40 secs. max. (200 °C min.), VP15-00-3

Number of times: Three times max.

Wave soldering Solder bath temperature: 260 °C max., Time: 10 secs. max., Number of times: once, WS60-00-1

Preheating temperature: 120 °C max. (package surface temperature.)

Partial heating Pin temperature: 300 °C or less ; time: 3 secs or less (for each side of the device) —

Recommended

Condition Symbol

Caution Do not use two or more soldering methods in combination (except partial heating).

Data Sheet U13594EJ2V0DS00

Page 27

APPENDIX A. DEVELOPMENT TOOLS

A PROM programmer, program adapter, and emulator are provided for the µPD6P4B.

Hardware

PD6P4B

• PROM programmer (AF-9704

Note

, AF-9705

Note

, AF-9706

Note

)

This PROM programmer supports the µPD6P4B.

By connecting a program adapter to this PROM programmer, the

PD6P4B can be programmed.

Note These are products of Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd (03-3733-1163).

• Program adapter (PA-61P34, PA-61P34BMC)

It is used to program the

PD6P4B in combination with AF-9704, AF-9705, or AF-9706.

The usable package differs depending on the program adapter.

• PA-61P34 :

PD6P4BGS

• PA-61P34BMC :µPD6P4BGS, µPD6P4BMC-5A4

Note

• Emulator (EB-6133

)

It is used to emulate the µPD6P4B.

Note This is a product of Naito Densei Machida Mfg. Co., Ltd. For details, consult Naito Densei Machida

Mfg. Co., Ltd. (044-822-3813).

Software

• Assembler (AS6133)

• This is a development tool for remote control transmitter software.

Part Number List of AS6133

Host Machine OS Supply Medium Part Number

PC-9800 series MS-DOSTM (Ver. 5.0 to Ver. 6.2) 3.5-inch 2HD (CPU: 80386 or more)

IBM PC/ATTM compatible MS-DOS (Ver. 6.0 to Ver. 6.22) 3.5-inch 2HC

PC DOSTM (Ver. 6.1 to Ver. 6.3)

S5A13AS6133

S7B13AS6133

Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this

software.

Data Sheet U13594EJ2V0DS00

Page 28

APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT

(in the case of NEC transmission format in command one-shot transmission mode)

Caution When using the NEC transmission format, please apply for a custom code at NEC.

(1) REM output waveform (From <2> on, the output is made only when the key is kept pressed.)

REM output

58.5 to 76.5 ms < 1 >

108 ms 108 ms

Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can

be reduced by sending the reader code and the stop bit from the second time.

(2) Enlarged waveform of <1>

< 3 >

< 2 >

PD6P4B

REM output

9 ms

Leader code

4.5 ms

13.5 ms

(3) Enlarged waveform of <3>

REM output

(4) Enlarged waveform of <2>

REM output

Custom code

9 ms

8 bits

13.5 ms

18 to 36 ms

Custom code'

8 bits

58.5 to 76.5 ms

4.5 ms

2.25 ms

Data code

0.56 ms

1.125 ms

8 bits

2.25 ms

1100

Data code

8 bits

27 ms

Stop Bit 1 bit

11.25 ms

Leader code

Data Sheet U13594EJ2V0DS00

0.56 ms Stop Bit

Page 29

(5) Carrier waveform (Enlarged waveform of each code’s high period)

REM output

8.77 s

9 ms or 0.56 ms Carrier frequency : 38 kHz

26.3 s

(6) Bit array of each code

PD6P4B

C0C1C2C3C4C5C6C7C0'

C1'

C2'

C3'

C4'

=======

C5'

C6'

C7'

D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D

Data codeData codeCustom code'Custom codeLeader code

Caution To prevent malfunction with other systems when receiving data in the NEC transmission

format, not only fully decode (make sure to check Data Code as well) the total 32 bits of the 16-bit custom codes (Custom Code, Custom Code’) and the 16-bit data codes (Data Code, Data Code) but also check to make sure that no signals are present.

Data Sheet U13594EJ2V0DS00

Page 30

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

DD or GND with a resistor, if it is considered to have a

PD6P4B

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

Data Sheet U13594EJ2V0DS00

Page 31

PD6P4B

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290

NEC Electronics (Germany) GmbH

Benelux Office Eindhoven, The Netherlands Tel:040-2445845 Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France Tel:01-30-67 58 00 Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860

NEC Electronics Hong Kong Ltd.

Hong Kong Tel:2886-9318 Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130 Tel:65-253-8311 Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

NEC Electronics Italiana s.r.l.

Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388

Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829

J99.1

Data Sheet U13594EJ2V0DS00

Page 32

PD6P4B

MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT and PC DOS are trademarks of IBM Corp.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

M7 98.8