Datasheet UPD66P04BGS, UPD66P04BGS-GJG Datasheet (NEC)

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD66P04B

4-BIT SINGLE-CHIP MICROCONTROLLER

FOR INFRARED REMOTE CONTROL TRANSMISSION

DESCRIPTION

The µPD66P04B is a microcontroller for infrared remote control transmitters which is provided with a one-time

PROM as the program memory.

Because users can write programs for the µPD66P04B, it is ideal for program evaluation and small-scale

µ

production of the application systems using the

When reading this document, also refer to the µPD6604 Data Sheet (U11281E).

FEATURES

• Program memory (one-time PROM): 1002 × 10 bits

• Data memory (RAM) : 32 × 4 bits

• Built-in carrier generation circuit for infrared remote control

• 9-bit programmable timer : 1 channel

• Command execution time : 16

• Stack level : 1 level (Stack RAM is for data memory RF as well.)

• I/O pins (K

• Input pins (KI) : 4 units

• Sense input pin (S

•S1/LED pin (I/O) : 1 unit (When in output mode, this is the remote control transmission

• Power supply voltage : V

• Operating ambient temperature : TA = –40 to +85 °C

• Oscillator frequency : fOSC = 300 kHz to 1 MHz

• POC circuit

I/O) : 8 units

0) : 1 unit

PD6604.

µ

s (when operating at fOSC = 500 kHz: RC oscillation)

display pin.)

DD = 2.2 to 3.6 V

APPLICATION

Infrared remote control transmitter (for AV and household electric appliances)

µ

Because the
the models using ceramic oscillation.
In applications where the clock accuracy and stability pose a problem, use the µPD61P34B (ceramic
oscillation type).

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.

Document No. U13596EJ2V0DS00 (2nd edition)
Date Published June 1999 N CP(K)
Printed in Japan

PD66P04B uses an RC oscillation system clock, its accuracy and stability are lower than

The mark

shows major revised points.

©

1998,1999

ORDERING INFORMATION

Part Number Package

µ

PD66P04BGS 20-pin plastic SOP (300 mil)

µ

PD66P04BGS-GJG 20-pin plastic shrink SOP (300 mil)

PIN CONFIGURATION (TOP VIEW)

20-pin Plastic SOP (300 mil)

•µPD66P04BGS

20-pin Plastic Shrink SOP (300 mil)

µ

PD66P04BGS-GJG

•

(1) Normal operating mode

µ

PD66P04B

K
K

S1/LED

REM

V

OSC

OSC

GND

RESET

(2) PROM programming mode

CLK

(L)

V

OSCOUT

OSCIN

GND

V

I/O6

I/O7

S

OUT

D6
D7

1
2

0

3
4
5

DD

6
7

IN

8
9
10

1
2
3
4
5

DD

6
7
8
9

PP

10

20
19
18
17
16
15
14
13
12
11

20
19
18
17
16
15
14
13
12
11

K
K
K
K
K
K
K
K
K
K

D5
D4
D3
D2
D1
D0
MD3
MD2
MD1
MD0

I/O5

I/O4

I/O3

I/O2

I/O1

I/O0

I3

I2

I1

I0

Caution Round brackets ( ) indicate the pins not used in the PROM programming mode.

L : Connect each of these pins to GND via a pull-down resistor.

2

Data Sheet U13596EJ2V0DS00

BLOCK DIAGRAM

µ

PD66P04B

REM

CARRIER
GENERATOR

CPU
CORE

S

1

/LED

9-bit
TIMER

RAM

LIST OF FUNCTIONS

Item

ROM capacity 1002 × 10 bits

One-time PROM
RAM capacity 32 × 4 bits
Stack 1 level (shared with RF of RAM)

ONE­TIME
PROM

4

8

2

µ

PD66P04B

PORT K

PORT K

I/O

PORT S

SYSTEM
CONTROL

4

KI0-K

I

8

2

I3

K

I/O0-KI/O7

S0, S1/LED

RESET

IN

OSC
OSC

OUT

V

DD

GND

I/O pin Key input (KI) : 4 pins

Key I/O (KI/O) : 8 pins

Key expansion input (S0, S1) : 2 pins

Remote control transmitter display output (LED): 1 pin (shared with S1 pin)
Number of keys 32 keys

48 keys (when expanded by key expansion input)

96 keys (when expanded by key expansion input and diode)
Clock frequency RC oscillation

fOSC = 300 to 500 kHz

fOSC = 500 kHz to 1 MHz

Note

Instruction execution time 16 µs (at fOSC = 500 kHz)
Carrier frequency fOSC, fOSC/2, fOSC/8, fOSC/12, fOSC/16, fOSC/24, no carrier (high level)
Timer 9-bit programmable timer : 1 channel
POC circuit Internal
Supply voltage VDD = 2.2 to 3.6 V
Operating ambient • TA = –40 to +85 °C

temperature • TA = –20 to +70 °C (when POC circuit used)
Package • 20-pin plastic SOP (300 mil)

• 20-pin plastic shrink SOP (300 mil)

Note It is necessary to design the application circuit so that the RESET pin goes low at a supply voltage of less

than 2.2 V.

Data Sheet U13596EJ2V0DS00

3

µ

PD66P04B

TABLE OF CONTENTS

1. PIN FUNCTIONS......................................................................................................................... 5

1.1 Normal Operating Mode.................................................................................................................... 5

1.2 PROM Programming Mode............................................................................................................... 6

1.3 INPUT/OUTPUT Circuits of Pins ...................................................................................................... 7

1.4 Dealing with Unused Pins ................................................................................................................ 8

1.5 Notes on Using K

I Pin at Reset ........................................................................................................ 8

2. DIFFERENCES BETWEEN µPD6604 AND µPD66P04B .......................................................... 9

3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY) .................................. 10

3.1 Operating Mode When Writing/Verifying Program Memory.......................................................... 10

3.2 Program Memory Writing Procedure .............................................................................................. 11

3.3 Program Memory Reading Procedure.............................................................................................12

4. ELECTRICAL SPECIFICATIONS............................................................................................... 13

5. CHARACTERISTIC CURVE (REFERENCE VALUES) .............................................................. 19

6. APPLIED CIRCUIT EXAMPLE ................................................................................................... 21

7. PACKAGE DRAWINGS..............................................................................................................22

8. RECOMMENDED SOLDERING CONDITIONS.......................................................................... 24

APPENDIX A. DEVELOPMENT TOOLS ........................................................................................ 25

APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT .......................... 26

4

Data Sheet U13596EJ2V0DS00

µ

PD66P04B

1. PIN FUNCTIONS

1.1 Normal Operating Mode

Pin No. Symbol Function Output Format When Reset

1KI/O0-KI/O7 CMOS High-level output
2 push-pull
15-20

3S0 — High-impedance

4S1/LED CMOS push-pull High-level output

5 REM CMOS push-pull Low-level output

6VDD ——
7 OSCOUT — High-impedance

8 OSCIN

9 GND ——
10 RESET ——

11-14 KI0-KI3

These pins refer to the 8-bit I/O ports. I/O switching can
be made in 8-bit units.
In INPUT mode, a pull-down resistor is added.
In OUTPUT mode, they can be used as the key scan
output of the key matrix.

Refers to the input port.
Can also be used as the key return input of the key
matrix.
In INPUT mode, the availability of the pull-down resistor
of the S0 and S1 ports can be specified by software in
terms in 2-bit units.
If INPUT mode is canceled by software, this pin is placed
in OFF mode and enters the high-impedance state.

Refers to the I/O port.
In INPUT mode (S1), this pin can also be used as the key
return input of the key matrix.
The availability of the pull-down resistor of the S0 and S1
ports can be specified by software in 2-bit units.
In OUTPUT mode (LED), it becomes the remote control
transmission display output (active low). When the
remote control carrier is output from the REM output, this
pin outputs the low level from the LED output synchronously
with the REM signal.

Refers to the infrared remote control transmission output.
The output is active high.
Carrier frequency: fOSC, fOSC/8, fOSC/12, high-level,

fOSC/2, fOSC/16, fOSC/24

(usable on software)
Refers to the power supply.
These pins are used for RC oscillation.

Refers to the ground.
Normally, this pin is a system reset input. By inputting

a low level, the CPU can be reset. When resetting with
the POC circuit a low level is output. A pull-up resistor
is incorporated.

Note 2

These pins refer to the 4-bit input ports.
They can be used as the key return input of the key
matrix.
The use of the pull-down resistor can be specified by
software in 4-bit units.

Note 1

(OFF mode)

(LED)

(oscillation stopped)
Low level

(oscillation stopped)

— Input (low-level)

Notes 1. Be careful about this because the drive capability of the low-level output side is held low.

2. In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when

reset is released (when RESET pin changes from low level to high level, or POC is released due to
supply voltage startup).

Data Sheet U13596EJ2V0DS00

5

1.2 PROM Programming Mode

Pin No. Symbol Function I/O

1, 2 D0-D7 8-bit data input/output when writing/verifying program memory I/O
15-20

3 CLK Clock input for updating address when writing/verifying program Input

memory

6VDD Power Supply. –

Supply +6 V to this pin when writing/verifying program memory.
7 OSCOUT Clock necessary for writing program memory. Connect a resistor –
8 OSCIN (R = 47 kΩ) and a capacitor (C = 27 pF) to these pins. Input
9 GND GND –
10 VPP Supplies voltage for writing/verifying program memory. –

Apply +12.5 V to this pin.
11-14 MD0-MD3

Input for selecting operation mode when writing/verifying program memory.

Input

µ

PD66P04B

6

Data Sheet U13596EJ2V0DS00

1.3 INPUT/OUTPUT Circuits of Pins

The input/output circuits of the µPD66P04B pins are shown in partially simplified forms below.

I/O0-KI/O7 (4) S0

(1) K

V

DD

data

Output
latch

P-ch

Input buffer

µ

PD66P04B

output

disable

Selector

Input buffer

Note The drive capability is held low.

I0-KI3

(2) K

standby

release

Input buffer

pull-down flag

N-ch

N-ch

Note

N-ch

standby

release

REM
output latch

pull-down flag

(5) S1/LED

output

disable

standby

release

pull-down flag

OFF mode

Input buffer

V

N-ch

DD

P-ch

N-ch

N-ch

(3) REM (6) RESET

V

DD

P-ch

data

Output
latch

N-ch

Carrier
generator

Internal reset signal

other than POC

Data Sheet U13596EJ2V0DS00

Input buffer

POC circuit

V

DD

P-ch

N-ch

7

1.4 Dealing with Unused Pins

The following connections are recommended for unused pins in the normal operation mode.

Table 1-1. Connections for Unused Pins

µ

PD66P04B

Pin

KI/O INPUT mode — Open

OUTPUT mode High-level output
REM —
S1/LED OUTPUT mode (LED) setting
S0 OFF mode setting Directly connected to GND
KI —

Note

RESET

Inside the microcontroller Outside the microcontroller

Built-in POC circuit Open

Connection

Note If the circuit is an applied one requiring high reliability, be sure to design it in such a manner that the RESET

signal is entered externally.

Caution The I/O mode and the terminal output level are recommended to be fixed by setting them

repeatedly in each loop of the program.

1.5 Notes on Using KI Pin at Reset

In order to prevent malfunction, be sure to input a low level to more than one of pins KI0 to KI3 when reset is

released (when RESET pin changes from low level to high level, or POC is released due to supply voltage startup).

8

Data Sheet U13596EJ2V0DS00

µ

PD66P04B

2. DIFFERENCES BETWEEN µPD6604 AND µPD66P04B

Table 2-1 shows the differences between the µPD6604 and µPD66P04B.

The only differences among these models are the program memory, supply voltage, system clock frequency,
oscillation stabilization wait time, and POC circuit (mask option), and the CPU function and internal peripheral
hardware are the same.

The electrical characteristics also differ slightly. For the electrical characteristics, refer to the Data Sheet of each
model.

µ

Table 2-1. Differences between

(1) When POC circuit (mask option) is provided to

PD6604 and µPD66P04B

µ

PD6604

Item
ROM One-time PROM Mask ROM
Oscillation stabilization wait time

• On releasing STOP mode by release 260/fOSC 36/fOSC

condition

• On releasing STOP or HALT mode by 284/fOSC to 340/fOSC 60/fOSC to 116/fOSC

RESET input and at reset
VPP pin and operating mode select pin Provided Not provided
Electrical specifications Some electrical specifications, such as data retention voltage and current

consumption, differ. For details, refer to Data Sheet of each model.

µ

PD66P04B

µ

PD6604

(2) When POC circuit (mask option) is not provided to µPD6604

Item
ROM One-time PROM Mask ROM
Oscillation stabilization wait time

• On releasing STOP mode by release 260/fOSC 36/fOSC

condition

• On releasing STOP or HALT mode by 284/fOSC to 340/fOSC 60/fOSC to 116/fOSC

RESET input and at reset
VPP pin and operating mode select pin Provided Not provided
POC circuit Incorporated Not provided
Supply voltage VDD = 2.2 to 3.6 V VDD = 1.8 to 3.6 V

(TA = –40 to +85 °C) (TA = –40 to +85 °C)

System clock frequency

Electrical specifications Some electrical specifications, such as data retention voltage and current

•fOSC = 300 to 500 kHz

•fOSC = 500 kHz to 1MHz

consumption, differ. For details, refer to Data Sheet of each model.

µ

PD66P04B

Note

µ

PD6604

•fOSC = 300 to 500 kHz

•

fOSC = 300 kHz to 1 MHz (VDD = 2.2 to 3.6 V)

Note It is necessary to design the application circuit so that the RESET pin goes low when the supply voltage

is less than 2.2 V.

Data Sheet U13596EJ2V0DS00

9

µ

PD66P04B

3. WRITING AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)

The program memory of the µPD66P04B is a one-time PROM of 1002 × 10 bits.
To write or verify this one-time PROM, the pins shown in Table 3-1 are used. Note that no address input pin

is used. Instead, the address is updated by using the clock input from the CLK pin.

Table 3-1. Pins Used to Write/Verify Program Memory

Pin Name Function

VPP Supplies voltage when writing/verifying program memory.

Apply +12.5 V to this pin.

VDD Power supply.

Supply +6 V to this pin when writing/verifying program memory.

CLK Inputs clock to update address when writing/verifying program memory.

By inputting pulse four times to CLK pin, address of program memory is updated.
MD0-MD3 Input to select operation mode when writing/verifying program memory.
D0-D7 Inputs/outputs 8-bit data when writing/verifying program memory.
OSCIN, OSCOUT Clock necessary for writing program memory. Connect a resistor (R = 47 kΩ) and a capacitor

(C = 27 pF) to these pins.

3.1 Operating Mode When Writing/Verifying Program Memory

The µPD66P04B is set in the program memory write/verify mode when +6 V is applied to the VDD pin and +12.5
V is applied to the VPP pin after the µPD66P04B has been in the reset status (VDD = 5 V, VPP = 0 V) for a specific
time. In this mode, the operating modes shown in Table 3-2 can be set by setting the MD
all the pins other than those shown in Table 3-1 to GND via pull-down resistor.

Table 3-2. Setting Operation Mode

Setting of Operating Mode Operation Mode

VPP VDD MD0 MD1 MD2 MD3

+12.5 V +6 V H L H L Clear program address to 0

L H H H Write mode
L L H H Verify mode

H × H H Program inhibit mode

×: don’t care (L or H)

0 through MD3 pins. Connect

10

Data Sheet U13596EJ2V0DS00

µ

Repeated X time

Reset

Oscillation stabilization

wait time

Write Verify Additional write

Address

increment

Data input

Hi-Z Hi-Z Hi-Z

Data output

Data input

Hi-Z

VPP
VDD

GND

V

DD+1

VDD

GND

CLK

V

PP

D0-D7

MD0

MD1

MD2

MD3

VDD

PD66P04B

3.2 Program Memory Writing Procedure

The program memory is written at high speed in the following procedure.

(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low.
(2) Supply 5 V to the V
(3) Supply 5 V to the V
(4) Wait for 2 ms until oscillation of the clock connected across the OSCIN and OSC OUT pins stabilizes.
(5) Set the program memory address 0 clear mode by using the mode setting pins.
(6) Supply 6 V to V
(7) Set the program inhibit mode.
(8) Write data to the program memory in the 1-ms write mode.
(9) Set the program inhibit mode.
(10) Set the verify mode. If the data have been written to the program memory, proceed to (11). If not, repeat

steps (8) through (10).
(11) Additional writing of (number of times of writing in (8) through (10): X) × 1 ms.
(12) Set the program inhibit mode.
(13) Input a pulse to the CLK pin four times to update the program memory address (+1).
(14) Repeat steps (8) through (13) up to the last address.
(15) Set the 0 clear mode of the program memory address.
(16) Change the voltages on the V
(17) Turn off power.

DD pin. Keep the VPP pin low.
PP pin after waiting for 10

DD and 12.5 V to VPP.

DD and VPP pins to 5 V.

µ

s.

The following figure illustrates steps (2) through (13) above.

Data Sheet U13596EJ2V0DS00

11

µ

PD66P04B

3.3 Program Memory Reading Procedure

(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low.
(2) Supply 5 V to the V DD pin. Keep the VPP pin low.
(3) Supply 5 V to the VPP pin after waiting for 10 µs.
(4) Wait for 2 ms until oscillation of the clock connected across the OSC
(5) Set the program memory address 0 clear mode by using the mode setting pins.
(6) Supply 6 V to VDD and 12.5 V to VPP.
(7) Set the program inhibit mode.
(8) Set the verify mode. Data of each address is output sequentially each time the clock pulse is input to

the CLK pin four times.
(9) Set the program inhibit mode.
(10) Set the program memory address 0 clear mode.
(11) Change the voltage on the V

DD and VPP pins to 5 V.

(12) Turn off power.

The following figure illustrates steps (2) through (10) above.

Oscillation stabilization

Reset

V

PP

V

DD

PP

V

GND

wait time

IN and OSCOUT pins stabilizes.

V

DD

+1

V

DD

DD

V

GND

CLK

D0-D

MD

MD

MD

MD

7

0

1

2

3

Hi-Z Hi-Z

"L"

Data output Data output

12

Data Sheet U13596EJ2V0DS00

µ

PD66P04B

4. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = +25 °C)

Parameter Symbol Test Conditions Rating Unit

Power supply voltage VDD –0.3 to +7.0 V

VPP –0.3 to +13.5 V
Input voltage VI KI/O, KI, S0, S1 , RESET –0.3 to VDD + 0.3 V
Output voltage VO –0.3 to VDD + 0.3 V
High-level output current IOH

Low-level output current IOL

Operating ambient TA –40 to +85 °C
temperature

Storage temperature Tstg –65 to +150 °C

Note

REM Peak value –30 mA

rms –20 mA

LED Peak value –7.5 mA

rms –5 mA

One KI/O pin Peak value –13.5 mA

rms –9 mA

Total of LED and KI/O pins Peak value –18 mA

rms –12 mA

Note

REM Peak value 7.5 mA

rms 5 mA

LED Peak value 7.5 mA

rms 5 mA

Note Work out the rms with: [rms] = [Peak value] × Duty.

Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even momen-

tarily. In other words, an absolute maxumum rating is a value at which the possibility of psysical
damage to the product cannnot be ruled out. Care must therefore be taken to ensure that the
these ratings are not exceeded during use of the product.

Recommended Power Supply Voltage Range (T

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Power supply voltage VDD fOSC = 300 to 500 kHz 2.2 3.0 3.6 V

fOSC = 500 kHz to 1 MHz

A = –40 to +85 °C)

Note

2.2 3.0 3.6 V

Note It is necessary to design the application circuit so that the RESET pin goes low when the supply voltage

is less than 2.2 V.

Data Sheet U13596EJ2V0DS00

13

µ

PD66P04B

DC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

High-level input voltage VIH1 RESET 0.8 VDD VDD V

VIH2 KI/O 0.65 VDD VDD V
VIH3 KI, S0, S1 0.65 VDD VDD V

Low-level input voltage VIL1 RESET 0 0.2 VDD V

VIL2 KI/O 0 0.3 VDD V
VIL3 KI, S0 , S1 0 0.15 VDD V

High-level input ILH1 KI 3
leakage current VI = VDD, pull-down resistor not incorporated

ILH2 S0, S1 3

VI = VDD, pull-down resistor not incorporated
Low-level input leakage IUL1 KI VI = 0 V –3
current IUL2 KI/O VI = 0 V –3

IUL3 S0, S1 VI = 0 V –3
High-level output voltage VOH1 REM, LED, KI/O IOH = –0.3 mA 0.8 VDD V
Low-level output voltage VOL1 REM, LED IOL = 0.3 mA 0.3 V

VOL2 KI/O IOL = 15 µA 0.4 V
High-level output current IOH1 REM VDD = 3.0 V, VOH = 1.0 V –5 –9 mA

IOH2 KI/O VDD = 3.0 V, VOH = 2.2 V –2.5 –5 mA
Low-level output current IOL1 KI/O VDD = 3.0 V, VOL = 0.4 V 30 70

VDD = 3.0 V, VOL = 2.2 V 100 220
Built-in pull-up resistor R1 RESET 25 50 100 k Ω
Built-in pull-down resistor R 2 RESET 2.5 5 15 kΩ

R3 KI, S0, S1 75 150 300 k Ω
R4 KI/O 130 250 500 k Ω

Data hold power supply VDDDR In STOP mode 1.2 3.6 V
voltage

Supply current

Note

IDD1 Operating fOSC = 1.0 MHz, VDD = 3 V ± 10 % 0.6 1.2 mA

mode fOSC = 455 kHz, VDD = 3 V ± 10 % 0.5 1.0 mA

IDD2 HALT mode fOSC = 1.0 MHz, VDD = 3 V ± 10 % 0.5 1.0 mA

fOSC = 455 kHz, VDD = 3 V ± 10 % 0.4 0.8 mA

IDD3

STOP mode

VDD = 3 V ± 10 % 1.0 8.0
VDD = 3 V ± 10 %, TA = 25 °C 1.0 2.0

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

µ

A

Note The POC circuit current and the current flowing in the built-in pull-up resistor are not included.

14

Data Sheet U13596EJ2V0DS00

µ

PD66P04B

AC Characteristics (TA = –40 to +85 °C, VDD = 2.2 to 3.6 V)

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

Instruction execution time tCY 15.9 27

Note 1 7.9 27

KI, S0, S1 high-level width tH 10

When canceling standby mode HALT mode 10

STOP mode Note 2

RESET low-level width tRSL 10

Notes 1. When using at fOSC = 500 kHz or higher, it is necessary to design the application circuit so that the

RESET pin goes low when the supply voltage is less than 2.2 V.

2. 10 + 260/fOSC

Remark tCY = 8/fOSC (fOSC: System clock oscillator frequency)

Note 1

POC Circuit

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
POC-detected voltage
POC circuit current IPOC 1.2 1.5

(TA = –20 to +70 °C)

Note 2

VPOC 1.8 2.0 2.2 V

µ

s

µ

s

µ

s

µ

s

µ

s

µ

s

µ

A

Notes 1. Operates effectively under the conditions of fOSC = 300 to 500 kHz.

2. Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal

reset is canceled.
From the time of V

POC ≥ VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the

period of VPOC ≥ VDD lasts less than 1 ms, the internal reset may not take effect.

System Clock Oscillator Characteristics (T

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Oscillator frequency fOSC 300 455 500 kHz

Note 300 455 1000 kHz

A = –40 to +85 °C, VDD = 2.2 to 3.6 V)

Note When using at fOSC = 500 kHz or higher, it is necessary to design the application circuit so that the RESET

pin goes low when the supply voltage is less than 2.2 V.

Recommended Oscillator Constant (T

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit
Capacity of oscillation C 22 27 33 pF

capacitor
Oscillation resistance R 47 kΩ

A = –40 to +85 °C, VDD = 2.2 to 3.6 V)

An external circuit example

OSC

IN

OSC

OUT

R

C

Data Sheet U13596EJ2V0DS00

15

PROM Programming Mode

µ

PD66P04B

DC Programming Characteristics (T

Parameter Symbol Test Conditions MIN. TYP. MAX. Unit

High-level input voltage VIH1 Other than CLK 0.7 VDD VDD V

VIH2 CLK VDD–0.5 VDD V

Low-level input voltage VIL1 Other than CLK 0 0.3 VDD V

VIL2 CLK 0 0.4 V
Input leakage current ILI VIN = VIL or VIH 10
High-level output voltage VOH IOH = –1 mA VDD–1.0 V
Low-level output voltage VOL IOL = 1.6 mA 0.4 V
VDD supply current IDD 30 mA
VPP supply current IPP MD0 = VIL, MD1 = VIH 30 mA

A = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V)

Cautions 1. Keep VPP to within +13.5 V including overshoot.

2. Apply V

DD before VPP and turns it off after VPP.

µ

A

16

Data Sheet U13596EJ2V0DS00

µ

PD66P04B

AC Programming Characteristics (TA = 25 °C, VDD = 6.0 ±0.25 V, VPP = 12.5 ±0.3 V)

Parameter Symbol Note1 Test Conditions MIN. TYP. MAX. Unit
Address setup time
MD1 setup time (vs. MD0↓)tM1S tOES 2
Data setup time (vs. MD0↓)tDS tDS 2
Address hold time
Data hold time (vs. MD0↑)tDH tDH 2
MD0↑→ data output float delay time tDF tDF 0 130 ns
VPP setup time (vs. MD3↑)tVPS tVPS 2
VDD setup time (vs. MD3↑)tVDS tVCS 2
Initial program pulse width tPW tPW 0.95 1.0 1.05 ms
Additional program pulse width tOPW tOPW 0.95 21.0 ms
MD0 setup time (vs. MD1↑)tMOS tCES 2
MD0↓→ data output delay time tDV tDV MD0 = MD1 = VIL 1
MD1 hold time (vs. MD0↑)tM1H tOEH tM1H+tM1R ≥ 50 µs2
MD1 recovery time (vs. MD0↓)tM1R tOR 2
Program counter reset time tPCR –10
CLK input high-, low-level width tXH, tXL – 0.125
CLK input frequency fX – 8 MHz
Initial mode set time tI –2
MD3 setup time (vs. MD1↑)tM3S –2
MD3 hold time (vs. MD1↓)tM3H –2
MD3 setup time (vs. MD0↓)tM3SR –

Note 2

Address
Address
MD3 hold time (vs. MD0↑)tM3HR –
MD3↓→ data output float delay time tDFR –
Reset setup time tRES –10
Oscillation stabilization wait time

Note 2

Note 2

(vs. MD0↓)tAS tAS 2

Note 2

(vs. MD0↑)tAH tAH 2

→ data output delay time

→ data output hold time tHAD tOH

Note 3

tOAD tACC

tWAIT –2ms

When program memory is read
When program memory is read
When program memory is read
When program memory is read
When program memory is read

µ
µ
µ
µ
µ

µ
µ

µ
µ
µ
µ
µ
µ

µ
µ
µ

2

2
0 130 ns
2

2

µ
µ

µ
µ
µ

s
s
s
s
s

s
s

s
s
s
s
s
s

s
s
s
s
s

s
s
s

Notes 1. Equivalent symbol of the corresponding µPD27C256A (The µPD27C256A is a maintenance product.)

2. The internal address signal is incremented at the falling edge of the third clock of CLK.

3. Connect a resistor (R = 47 kΩ) and a capacitor (C = 27 pF) between the OSCIN and OSCOUT pins.

Data Sheet U13596EJ2V0DS00

17

Program Memory Write Timing

t

WAIT

t

RES

V

PP

V

V

DD

PP

GND

DD

+1

V

V

V

DD

DD

GND

CLK

D0-D

7

t

t

MD

0

MD

1

MD

2

MD

3

t

t

t

PCR

t

M3S

VPS

VDS

Data input

t

DS

t

M1S

µ

PD66P04B

t

XH

t

Data output

t

DH

t

PW

t

M1H

t

DV

t

DF

t

M1R

t

MOS

Data input Data input

t

DS

t

OPW

XL

t

DH

t

AH

t

AS

Hi-ZHi-ZHi-ZHi-ZHi-Z

t

M3H

Program Memory Read Timing

t

WAIT

t

RES

V

PP

V

V

DD

PP

GND

VDD+1

V

V

DD

DD

GND

CLK

D0-D

7

t

I

MD

0

MD

1

t

PCR

Hi-Z

t

t

VPS

VDS

t

XL

t

DV

t

XH

Data output

"L"

t

DAD

t

MAD

Data output

t

M3HR

Hi-Z

t

DFR

18

MD

MD

2

t

M3SR

3

Data Sheet U13596EJ2V0DS00

5. CHARACTERISTIC CURVE (REFERENCE VALUES)

IOL vs V

OL

(REM, LED)

Low-level output current IOL [mA]

Low-level output voltage VOL [V]

IOH vs V

OH

(REM)

High-level output current IOH [mA]

High-level output voltage VOH [V]

IOH vs V

OH

(LED)

High-level output current IOH [mA]

High-level output voltage VOH [V]

10

0.6 1.8 2.4 31.2

9
8
7
6
5
4
3
2
1

0

–20

VDD – 0.6 VDD – 1.8 VDD – 2.4 VDD – 3VDD – 1.2

–18
–16
–14
–12
–10

–8
–6
–4
–2

0

V

DD

–10

VDD – 0.6 VDD – 1.8 VDD – 2.4 VDD – 3VDD – 1.2

–9
–8
–7
–6
–5
–4
–3
–2
–1

0

V

DD

(TA = 25 °C, VDD = 3.0 V)

(T

A = 25 °C , VDD = 3.0 V)

(T

A = 25 °C , VDD = 3.0 V)

IDD vs V

DD

Power supply current IDD [mA]

Power supply voltage VDD [V]

(T

A = 25 °C)

1100

1000

900

800

700

600

500

400

1.2 2.4 3.0 4.23.61.8

f

OSC

vs V

DD

Oscillator frequency fosc [kHz]

Power supply voltage VDD [V]

(C = 27 pF, T

A = 25 °C)

R = 47 kΩ

R = 22 kΩ

1.2

1.0

0.8

0.6

0.4

0.2

0

1.8 2.4 3.0

1 MHz operating mode
1 MHz HALT mode

455 kHz operating mode
455 kHz HALT mode

3.6 4.2

2.2

µ

PD66P04B

Data Sheet U13596EJ2V0DS00

19

µ

PD66P04B

IOL vs VOL (KI/O

320

µ

280

[ A]

OL

240
200
160
120

80

Low-level output current I

40

0

0.6 1.8 2.4 31.2

Low-level output voltage VOL [V]

)

(T

A

= 25 °C, VDD = 3.0 V) (TA = 25 °C, VDD = 3.0 V)

IOH vs VOH (KI/O

)

–15
–14
–13
–12

[mA]

–11

OH

–10

–9
–8
–7
–6
–5
–4
–3

High-level output current I

–2
–1

0

V

V

DD

–

0.6 V

DD

DD

DD

–

1.8 V

DD

–

1.2

–

High-level output voltage VOH [V]

2.4 V

DD

–

3V

20

Data Sheet U13596EJ2V0DS00

6. APPLIED CIRCUIT EXAMPLE

Example of Application to System

• Remote-control transmitter (40 keys; mode selection switch accommodated)

K

I/O6

K

I/O7

S

0

+

S1/LED
REM

I/O5

K
K

I/O4

K

I/O3

K

I/O2

K

I/O1

µ

PD66P04B

DD

V
OSC
OSC
GND

OUT

IN

+

R

C

RESET

K

I/O0

K

I3

K

I2

K

I1

K

I0

• Remote-control transmitter (48 keys accommodated)

KI/O6
KI/O7
S0

+

S1/LED
REM

Mode selection switch

Key matrix
8 × 5 = 40 keys

KI/O5
KI/O4
KI/O3
KI/O2
KI/O1

DD

V

+

OSCOUT

R

OSCIN

C

GND
RESET

KI/O0

KI3
KI2
KI1
KI0

Key matrix
8 × 6 = 48 keys

Remark When the POC circuit is used effectively, it is not necessary to connect the capacitor enclosed in the

dotted lines.

Data Sheet U13596EJ2V0DS00

21

7. PACKAGE DRAWINGS

(1)µPD66P04BGS

20 PIN PLASTIC SOP (300 mil)

110

µ

PD66P04B

1120

detail of lead end

P

A

G

C

D

M

M

N

E

F

NOTE

Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

H

I

J

L

B

K

ITEM MILLIMETERS INCHES

A

12.7±0.3

B

0.78 MAX.

C

1.27 (T.P.)
D 0.42 0.017
E

F
G
H

I 5.6±0.2 0.220

J
K 0.22

L 0.6±0.2 0.024

M

N
P3° 3°

+0.08
–0.07

0.1±0.1

1.8 MAX.

1.55±0.05

7.7±0.3

1.1
+0.08

–0.07

0.12

0.10

+7°
–3°

0.500±0.012

0.031 MAX.

0.050 (T.P.)

0.004±0.004

0.071 MAX.

0.061±0.002

0.303±0.012

0.043

0.009

0.005

0.004
+7°

–3°

P20GM-50-300B, C-5

+0.003
–0.004

+0.009
–0.008

+0.003
–0.004

+0.008
–0.009

22

Data Sheet U13596EJ2V0DS00

(2)µPD66P04BGS-GJG

20 PIN PLASTIC SHRINK SOP (300 mil)

20 11

110

A

F

G

detail of lead end

P

H

I

µ

PD66P04B

J

S

E

NS

C

M

D

NOTE

1. Controlling dimension millimeter.

2. Each lead centerline is located within 0.12 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

M

B

K

L

ITEM MILLIMETERS INCHES

A

6.7±0.3 0.264

B

0.575 MAX.

C

0.65 (T.P.)

D

0.32

E

0.125±0.075

F

2.0 MAX.

G

1.7±0.1

H

8.1±0.3

I

6.1±0.2

J

1.0±0.2

K

0.15

L

0.5±0.2

0.12

M

0.10

N

+7°

3° 3°

P

–3°

+0.08

–0.07

+0.10

–0.05

+0.012
–0.013

0.023 MAX.

0.026 (T.P.)
+0.003

0.013

–0.004

0.005±0.003

0.079 MAX.
+0.004

0.067

–0.005

0.319±0.012

0.240±0.008
+0.009

0.039

–0.008
+0.004

0.006

–0.002
+0.008

0.020

–0.009

0.005

0.004

+7°
–3°

P20GM-65-300B-3

Data Sheet U13596EJ2V0DS00

23

µ

PD66P04B

8. RECOMMENDED SOLDERING CONDITIONS

Carry out the soldered packaging of this product under the following recommended conditions.
For details of the soldering conditions, refer to information material Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than the recommended conditions, please consult one of our NEC

sales representatives.

Table 8-1. Soldering Conditions for Surface-Mount Type

µ

PD66P04BGS : 20-pin plastic SOP (300 mil)

µ

PD66P04BGS-GJG : 20-pin plastic SSOP (300 mil)

Soldering Method Soldering Condition

Infrared reflow Package peak temperature: 235 °C, Time: 30 secs. max. (210 °C min.), IR35-00-2

Number of times: Twice max.

VPS Package peak temperature: 215 °C, Time: 40 secs. max. (200 °C min.), VP15-00-2

Number of times: Twice max.

Wave soldering Solder bath temperature: 260 ° C max., Time: 10 secs. max., WS60-00-1

Number of times: once, Preheating temperature: 120 °C max. (package
surface temperature.)

Partial heating Pin temperature: 300 °C or less ; time: 3 secs or less (for each side of the device) —

Recommended

Condition Symbol

Caution Do not use two or more soldering methods in combination (except partial heating).

24

Data Sheet U13596EJ2V0DS00

APPENDIX A. DEVELOPMENT TOOLS

A PROM programmer, program adapter, and emulator are provided for the µPD66P04B.

Hardware

µ

PD66P04B

• PROM programmer (AF-9704

Note

, AF-9705

Note

, AF-9706

Note

)

This PROM programmer supports the µPD66P04B.

µ

By connecting a program adapter to this PROM programmer, the

PD66P04B can be programmed.

Note These are products of Ando Electric. For details, consult Ando Electric (03-3733-1163).

• Program adapter (PA-61P34, PA-61P34BMC)

It is used to program the µPD66P04B in combination with AF-9704, AF-9705, or AF-9706.

• Emulator (EB-6133

Note

)

It is used to emulate the µPD66P04B.

Note This is a product of Naito Densei Machida Mfg. Co., Ltd. For details, consult Naito Densei Machida

Mfg. Co., Ltd. (044-822-3813).

Software

• Assembler (AS6133)

• This is a development tool for remote control transmitter software.

Part Number List of AS6133

Host Machine OS Supply Medium Part Number

PC-9800 series MS-DOSTM (Ver. 5.0 to Ver. 6.2) 3.5-inch 2HD
(CPU: 80386 or more)

IBM PC/ATTM compatible MS-DOS (Ver. 6.0 to Ver. 6.22) 3.5-inch 2HC

PC DOSTM (Ver. 6.1 to Ver. 6.3)

µ

S5A13AS6133

µ

S7B13AS6133

Caution Although Ver.5.0 or later has a task swap function, this function cannot be used with this

software.

Data Sheet U13596EJ2V0DS00

25

µ

PD66P04B

APPENDIX B. EXAMPLE OF REMOTE-CONTROL TRANSMISSION FORMAT

(in the case of NEC transmission format in command one-shot transmission mode)

Caution When using the NEC transmission format, please apply for a custom code at NEC.

(1) REM output waveform (From <2> on, the output is made only when the key is kept pressed.)

REM output

58.5 to 76.5 ms
< 1 >

108 ms 108 ms

Remark If the key is repeatedly pressed, the power consumption of the infrared light-emitting diode (LED) can

be reduced by sending the reader code and the stop bit from the second time.

(2) Enlarged waveform of <1>

< 2 >

< 3 >

REM output

9 ms

Leader code

4.5 ms

13.5 ms

(3) Enlarged waveform of <3>

REM output

(4) Enlarged waveform of <2>

Custom code

9 ms

8 bits

13.5 ms

18 to 36 ms

Custom code'

8 bits

58.5 to 76.5 ms

4.5 ms

Data code

0.56 ms

1.125 ms
0

8 bits

2.25 ms
1100

Data code

8 bits

27 ms

Stop Bit
1 bit

REM output

26

9 ms

11.25 ms

Leader code

2.25 ms

0.56 ms
Stop Bit

Data Sheet U13596EJ2V0DS00

(5) Carrier waveform (Enlarged waveform of each code’s high period)

REM output

8.77 s

9 ms or 0.56 ms
Carrier frequency : 38 kHz

26.3 s

µ

µ

(6) Bit array of each code

µ

PD66P04B

C0C1C2C3C4C5C6C7C0'

C1'

C2'

C3'

C4'

=======

C

C

C

0

1

or

or

or

C

o

C

1

C

C5'

C

C

C

2

3

4

or

or

or

2

C

3

C

4

C

C6'

C7'

D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D

=

C

C

5

6

7

or

or

5

C

6

C

7

Data codeData codeCustom code'Custom codeLeader code

Caution To prevent malfunction with other systems when receiving data in the NEC transmission

format, not only fully decode (make sure to check Data Code as well) the total 32 bits of the
16-bit custom codes (Custom Code, Custom Code’) and the 16-bit data codes (Data Code,
Data Code) but also check to make sure that no signals are present.

7

Data Sheet U13596EJ2V0DS00

27

[MEMO]

µ

PD66P04B

28

Data Sheet U13596EJ2V0DS00

[MEMO]

µ

PD66P04B

Data Sheet U13596EJ2V0DS00

29

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.

DD or GND with a resistor, if it is considered to have a

µ

PD66P04B

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.

30

Data Sheet U13596EJ2V0DS00

µ

PD66P04B

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: [phone]

800-366-9782

Fax: [phone]

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: [phone]
Fax: [phone]

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel:[phone]
Fax: [phone]

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel:[phone]
Fax: [phone]

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel:[phone]
Fax: [phone]

NEC Electronics Taiwan Ltd.

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: [phone]
Fax: [phone]

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]

Taipei, Taiwan
Tel: [phone]
Fax: [phone]

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: [phone]
Fax: [phone]

J99.1

Data Sheet U13596EJ2V0DS00

31

µ

PD66P04B

MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT and PC DOS are trademarks of IBM Corp.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7 98.8