Datasheet UPD61P24CS, UPD61P24GS Datasheet (NEC)

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Page 1

DATA SHEET

MOS INTEGRATED CIRCUIT

PD61P24

4-BIT SINGLE-CHIP MICROCONTROLLER

FOR REMOTE CONTROL TRANSMISSION

DESCRIPTION

The µPD61P24 is a 4-bit single-chip microcontroller for infrared remote controllers for TVs, VCRs, stereos, cassette

decks, air conditioners, etc.

As the

and for small-scale production of such systems.

The functions of the

manual before designing your system.

PD61P24 is user-programmable, it is ideal for evaluation of programs running in a µPD6124A or 6600A,

PD61P24 are described in detail in the following User’s Manual. Be sure to read this

PD612X Series User’s Manual: IEP-1083

FEATURES

•Transmitter for programmable infrared remote controller

•19 types of instructions

•Instruction execution time: 17.6 ramic resonator)

•On-chip one-time PROM: 1002 × 10 bits

•Data memory (RAM) capacity : 32 × 5 bits

•9-bit programmable timer: 1 channel

•I/O pins (K

•Input pins (K

CautionTo use the NEC transmission format, ask NEC to supply the custom code.

I/O): 8 pins

I): 4 pins

Do no use R0 when using a register as an operand of the branch instruction.

s (with 455-kHz ce-

•Serial input pins (S-IN): 1 pin

•Transmission-in-progress indication pin (S-OUT): 1 pin

•Transmit carrier frequency (REM)

OSC/12, fOSC/8

•Standby operation (HALT/STOP mode)

•Low power consumption

•Current consumption in STOP mode (T 1 µA MAX.

•Low-voltage operation: VDD = 2.2 to 5.5 V

A = 25°C)

DocumentNo. U12629EJ4V0DS00 (4th edition) Previous No. IC-2876 Date Published July 1997 N Printed in Japan

The information in this document is subject to change without notice.

The mark shows major revised points.

1997

Page 2

ORDERING INFORMATION

Part Number Package

PD61P24CS 20-pin plastic shrink DIP (300 mil)

PD61P24GS 20-pin plastic SOP (300 mil)

PIN CONFIGURATION (Top View)

(1) Normal operating mode (2) PROM programming mode

PD61P24

I/O1

I/O0

S-IN

S-OUT

REM

OSC-OUT

OSC-IN

1 2 3 4 5 6 7 8 9

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

(Open) (Open)

(Open)

4 5 6

7 8

CLK

10(L) 11 MD3

20 19 18 17 16 15 14 13 12 MD2

Caution Round brackets ( ) indicate the pins not used in the PROM programming mode.

L : Connect each of these pins to GND via a resistor (470 Ω). Open: Leave these pins open.

D2 D3 D4 D5 D6 D7 MD0 MD1

Page 3

BLOCK DIAGRAM

PD61P24

OSC

OSC-OUT

TIMER

(L)

MOD

TIMER

(H)

10 bits

ROM D.P.

PC(L)

PC(H)

CNTL

L H

1002 × 10 bits

M P X

ALU

One-Time

PROM

(L)

One-Time

PROM

(H)

ACC

S-INREMS-OUTOSC-IN

KEY

OUT(L)

ADD DEC

KEY

OUT(H)

I/O0-KI/O7

32 × 5 bits

RAM

M P X

RAM

KEY

K -K

I0 I3

CNTL

(L)

Watchdog

timer

function

ACK

(H)

Page 4

1. PROGRAM COUNTER (PC) ……… 10 BITS

The program counter (PC) is a binary counter, which holds the address information for the program memory.

Figure 1-1. Program Counter Organization

PD61P24

PC7PC6PC5PC4PC3PC2PC1PC

Normally, the program counter contents are automatically incremented each time an instruction is executed,

according to the number of instruction bytes.

When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination. Immediate data or the data memory contents are loaded to all or some bits of the PC. When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack

memory. Then, a value needed for each jump instruction will be loaded.

When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded

into the PC.

When “all clear” is input or on reset, the PC contents are cleared to “000H”.

2. STACK POINTER (SP) ……… 2 BITS

This 2-bit register holds the start address information for the stack area. The stack area is shared with the data

memory.

The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when

the return instruction (RET) is executed.

The stack pointer is cleared to “00B” after reset or “all clear” is input, and indicates the highest address FH for

the data memory as the stack area.

The figure below shows the relationship for the stack pointer and the data memory area.

Data memory

RC R RE RF

(SP)

11B 10B

01B 00B

If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset

signal will be generated.

Page 5

3. PROGRAM MEMORY (ROM) ……… 1002 STEPS × 10 BITS

The program memory (ROM) is configured in 10 bits steps. It is addressed by the program counter. Program and table data are stored in the program memory.

Figure 3-1. Program Memory Map

000H

0FFH

100H

1FFH

200H

2FFH

300H

3E9H

3EAH

3FFH

Test program area

PD61P24

4. DATA MEMORY (RAM) ……… 32 WORDS × 5 BITS

The data memory is a RAM of 32 words × 5 bits. The data memory stores processing data. In some cases, the

data memory is processed in 8-bit units. R0 may be used as the data pointer for the ROM.

After power application, the RAM will be undefined. The RAM retains the previous data on reset.

Figure 4-1. Data Memory Organization

SP–3 SP–2 SP–1 SP–0

Caution Avoid using the RAM areas RD, RE, and RF in a CALL routine as much as possible because these

areas are also used as stack memory areas (to prevent program hang-up in case the value of the SP is destroyed due to some reason such as noise). When using these RAM areas as general-purpose RAM areas, be sure to include stack pointer checking in the main routine.

Page 6

5. DATA POINTER (R0)

R0 (R10, R00) for the data memory can serve as the data pointer for the ROM. R0 specifies the low-order 8 bits in the ROM address. The high-order 2 bits in the ROM address are specified

by the control register.

Table referencing for ROM data can be easily executed by calling the ROM contents by setting the ROM address

to the data pointer.

On reset or “all clear” is input, it becomes undefined.

Figure 5-1. Data Pointer Organization

PD61P24

Control registers (P )

6. ACCUMULATOR (A) ……… 4 BITS

The accumulator (A) is a 4-bit register. The accumulator plays a major role in each operation. On reset or “all clear” is input, it becomes undefined.

Figure 6-1. Accumulator Organization

7. ARITHMETIC LOGIC UNIT (ALU) ……… 4 BITS

The arithmetic logic unit (ALU) is a 4-bit operation circuit, and executes simple operations, such as arithmetic

operations.

8. FLAGS

(1) Status flag

When the status for each pin is checked by the STTS instruction, if the condition coincides with the condition specified by the STTS instruction, the status flag (F) is set (to 1). On reset or “all clear” is input, it becomes undefined.

(2) Carry flag

When the INC (increment) instruction or the RL (rotate left) instruction is executed, if a carry is generated from the MSB for the accumulator, the carry flag (C) is set (to 1). The carry flag (C) is also set (to 1), if the contents for the accumulator are “FH”, when the SCAF instruction is executed. On reset or “all clear” is input, it becomes undefined.

Page 7

PD61P24

9. SYSTEM CLOCK GENERATOR

The system clock generator consists of a resonator, which uses a ceramic resonator (400kHz to 500kHz).

Figure 9-1. System Clock Generator

OSC-IN

OSC-OUT

In the STOP mode (oscillation stop HALT instruction), the oscillator in the system clock generator stops its

operation, and the system clock ø is stopped.

STOP mode

System clock

Page 8

PD61P24

10. TIMER

The timer block determines the transmission output pattern. The timer consists of 10 bits, of which 9 bits serve as the 9-bit down counter and the remaining 1 bit serves as the 1-bit latch, which determines the carrier output validity.

The 9-bit down counter is decremented (–1) every 8/f starting down count operation. Down counting stops after all of the 9 bits become 0. When down counting is stopped, the signal indicating that the timer operation has stopped, is output. If the CPU is at standby (HALT TIMER) for the timer operation completion, the standby (HALT) condition is released and the next instruction will be executed. If the next instruction again sets the value of the down counter, down counting continues without any error (the carrier output of the REM pin is not affected).

Set the down count time according to the following calculation; (set value (HEX) + 1) × 8/f to the timer is done by the timer manipulation instruction.

When the down counter is operating, the remote control transmission carrier can be output to the REM pin. Whether or not to output the carrier can be selected by the MSB for the timer register block. Set “1”, when outputting the carrier, or “0”, when not outputting the carrier.

If all the down counter bits become “0”, when outputting the carrier, the carrier output will be stopped. When not outputting the carrier, the REM pin output will become low level.

A signal in synchronization with the REM output is output to the S-OUT pin. However, the waveform for the SOUT pin is low, when the carrier is being output to the REM pin, or it is high, when the carrier is not being output to the REM pin.

If the HALT instruction, which initiates the oscillation stop mode, is executed when the down counter is operating, the oscillation stop mode is initiated after down counting is stopped (after 0).

Timer operation STOP/RUN is controlled by the control register (P

At reset (all clear) time, the REM pin goes low and S-OUT pin goes high. All 10 bits of the timer are cleared to 000H.

OSC(s) in synchronization with the machine cycle, after

OSC. Setting the value

1). (Refer to 13. CONTROL REGISTER (P1).)

Caution Because the timer clock is not synchronized with the carrier output, the pulse width may be

shortened at the beginning and end of the carrier output.

Figure 10-1. Timer Block Organization

Set by timer mainpulation instruction

MSB

fosc/8

S-OUT

REM

1/0

Clear

Carrier (fosc/12, fosc/8) Selected by control register

9-bit down counter

Zero detection circuit

D of control register P

(Timer RUN/STOP)

Page 9

PD61P24

11. PIN FUNCTIONS

11.1 KI/O Pin (P0)

This is the 8-bit I/O pin for key-scan output. When the control register (P1) is set for the input port, the port can be used as an 8-bit input pin. When the port is set for the input mode, all of these pins are pulled down to the VSS level inside the LSI.

At reset (all cleared), the value of I/O mode and output latch becomes undefined.

Figure 11-1. K

I/O7

I/O6

I/O5

11.2 KI/O Pull-Down Resistor Configuration

Input/output selection

I/O Pin Organization

I/O4

I/O3

(P )

I/O1

Control register

I/O0

I/O2

P-ch

Output signal

Input signal

CMOS

Pull-down resistor

N-ch

When KI/O is set to the input mode, pull-down resistor R is turned on.

N-ch

Page 10

11.3 KI Pin (P12)

This is the 4-bit pin for key input. All of these pins are pulled down to the VSS level by PLA data.

PD61P24

Figure 11-2. K

11.4 KI Pull-Down Resistor Configuration

I Pin Organization

P-ch

Pin Input signal

PLA KI pull-down

resistor switch

N-ch

Pull-down resistor

When the pull-down resistor switch is turned on (set 1) by PLA data, pull-down resistor R is turned on.

Page 11

PD61P24

11.5 S-OUT Pin

By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that communication is in progress.

The S-OUT pin is CMOS output.

The S-OUT pin goes high on reset.

11.6 S-IN Pin (D

0 bit of P1)

To input serial data, use the S-IN pin. When control register (P1) is set to serial input mode, the S-IN pin is connected as an input to the LSB of the accumulator; the S-IN pin is pulled down to the V

SS level within the LSI.

In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is copied to the LSB of the accumulator.

If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no through current flows internally. When the RL A instruction is executed, the MSB is copied to the LSB.

At reset (all cleared), the S-IN pin goes into a high-impedance state.

Figure 11-3. Configuration of the S-IN Pin

Control register

S-IN

Page 12

12. PORT REGISTER (P×)

KI/O, KI, and the control register are handled as port registers. The table below shows the relations between the port registers and pins.

Table 12-1. Relations between Port Registers and Pins

PD61P24

Name Read Write Read Write

KI/O Pin status Output latch Pin status Output latch Undefined [input mode, output latch]

KI Pin status – – – Input mode

S-IN Pin status is read by RL A instruction when D0 of P1 register = 1. High impedance (D0 of P1 register = 0)

Input Mode Output Mode

P1× (H)

P 10

P11

P12

KI/O7-4 KI/O3-0

Control register (H) Control register (L)

I3-0

P00

P01

P02

On Reset

0× (L)

Page 13

13. CONTROL REGISTER (P1)

The control register contains of 10 bits. The controllable items are shown in Table 13-1.

Table 13-1. Control Register (P1)

PD61P24

Bit D

Name Test mode –

Set

Value

Be sure to set 0.

HALT

OSC

STOP

D.P. AD

AD =0

8 OSC

AD =1

8 OSC

MOD K

Timer

STOPNOP f /8AD =0

f /12AD =1

RUN

OUT

I/O

D0 .......................... Specifies data to be input to A0 when the accumulator is shifted to the left.

0: A3, 1:S-IN

1 .......................... Specifies the status of KI/O, as follows:

0: input mode, 1: output mode

D2 .......................... Specifies the status of the timer, as follows:

0: Count stop, 1: Count execution

3 .......................... Specifies the carrier frequency output from the REM pin.

0: fOSC/8, 1: fOSC/12

4, D5 ................. Specify the high-order 2 bits of the ROM data pointer.

D6 .......................... Determines what happen to the oscillation circuit when the HALT instruction is executed.

0: Oscillation does not stop 1: Oscillation stops (STOP mode)

7 .......................... Be sure to set this bit to 0.

D8, D9 ................. These bits specify test modes. Be sure to set them to 0.

RL A

S-IN

←

Remark D

0 = D8 = D9 = 0 on reset, and the other bits are undefined.

Page 14

14. STANDBY FUNCTION (HALT INSTRUCTION)

The µPD6600A is provided with the standby mode (HALT instruction), in order to reduce the power consumption,

when not executing the program. Clock oscillation can be stopped in the standby mode (STOP mode).

In the standby mode, the program execution stops. However, the contents of the internal registers and the data

memory are all retained.

14.1 STOP Mode (Oscillation stop HALT instruction)

In the STOP mode, the operation of the system clock generator (ceramic resonator oscillation circuit) stops.

Therefore, operations requiring the system clock will stop.

If the HALT instruction is executed during timer operation, the program counter stops. The oscillation stop mode

will be initiated, after the timer count down operation is completed.

14.2 HALT Mode (Oscillation continue HALT instruction)

The CPU stops its operation, until the HALT release condition is satisfied. The system clock operation continues in this mode.

14.3 Standby Release Conditions

(1) S-IN input

I/O input

(2) K

I input

(3) K (4) Timer count down operation completion

PD61P24

Remark Either high level or low level can be specified for setting a release condition by input.

Table 14-1. Standby Mode Releasing Condition

D1D

0 0 S-IN

00 K

0/1

0 1 Timer

Releasing condition:

Releasing Condition

I/O

“0”···Low level detection “1”···High level detection

Remarks

When RL A is selected, the standby mode is always released.

Valid only in the IN mode.

Released when 0.

←

Page 15

0.1 F

thL

Charge mode

Charge start instruction

Execute HALT instruction immediately before NOP. (Charge for 0.4 ms or more)

Discharge mode

Charge-discharge pattern

Discharge start instruction

Discharge starts after the NOP instruction execution. (Discharge time is about 5 ms from V

to V

thL

)

The pattern must be controlled by the program, in such a manner that the C charge level will not go below V

thL

PD61P24

15. AC PIN (ALL CLEAR PIN)

Internal part of the CPU including the program counter can be reset by setting the AC pin to the low level.

Watchdog Timer Function

A power-on reset function and a CR watchdog timer function, that can be controlled by program, can be realized

by connecting a 0.1

F capacitor across the AC pin and the VSS.

Caution When the watchdog timer function is not used, switch to charging mode by executing a NOP

instruction immediately before a HALT instruction at the beginning of the program. (Be sure to connect the capacitor.)

Page 16

16. MASK OPTIONS (PLA DATA)

The following items are fixed by mask option:

I, S-IN pin pull-down resistor provided

•K

• Carrier duty selection (1/3) at fOSC/12

• Hang-up detection provided

I/O ALL

<1> K

The system is reset when the hang-up detection KI/O ALL switch is set to ON (“1”) by PLA data and if the

I/O pins are in the input mode in the oscillation stop HALT mode or if even one of the KI/O pins is low.

K To use a pin as a key source of the switch, turn ON the switch with PLA data.

PD61P24

Figure 16-1. Hang-up Detection K

I/O0

K output signal K output signal

I/O1

K output signal

I/O2

K output signal

I/O3

K output signal

I/O4

K output signal

I/O5

K output signal

I/O6

K output signal

I/O7

K input/output selection

I/O

I/O ALL Configuration Diagram

PLA hang-up detection K

I/O

ALL switch

To RESET circuit

<2> HALT release condition specification (S-IN, KI/O, KI)

The system is reset if S-IN and KI/O are used in the HALT mode when S-IN and KI/O are specified by PLA data not to be used (“1”). K

I is used (“0”).

Page 17

BIT Assignment by Switch Selection

PD61P24

Address

pull-down resistor

Duty

S-IN

Hang-up detection

Corresponding Portion

Note

MSB

7654

(Provided)1(Provided)1(Provided)

(Provided)

Duty

(1/3 duty)

I/O

ALL

(Detection

provided)

HALT

S-IN

(Unused)

HALT

I/O

(Unused)

HALT

(Used)

321

S-IN

pull-down

resistor

(Provided)

LSB

Page 18

17. WRITING, READING, AND VERIFYING ONE-TIME PROM (PROGRAM MEMORY)

To write, read, or verify the PROM, set the PROM mode and use the pins shown in Table 17-1. No address input

pin is used. To update the address, the clock signal input from the CLK pin is used.

Table 17-1. Pins Used to Write, Read, and Verify Program Memory

Symbol Function

VPP Applies program voltage (12.5 V)

CLK Inputs clock to update address

MD0-MD3 Selects operation mode

D0-D7 Inputs/outputs 8-bit data

VDD Applies supply voltage (6 V)

17.1 Operation Mode When Writing, Reading, and Verifying Program Memory

PD61P24 enters the program memory write, read, or verify mode if +6 V is applied to the VDD pin and +12.5

The

V is applied to the VPP pin after the reset status has been held a certain time (VDD = 5 V, AC = low level).

In this mode, the operation modes listed in Table 17-2 can be selected by using the MD0 through MD3 pins. Any input pins not used for writing, reading, or verifying the program memory must be open or connected to GND

via a pull-down resistor (470 Ω).

PD61P24

Table 17-2. Operating Mode When Writing, Reading, and Verifying Program Memory

Specifies Operation Mode Operation Mode

VPP VDD MD0 MD1 MD2 MD3

+12.5 V +6 V H L H L Clears program memory address to 0

L H H H Write mode L L H H Read and verify modes

H × H H Program inhibit mode

×: don’t care (L or H)

Page 19

PD61P24

17.2 Program Memory Writing Procedure

The program memory is written at high speed in the following procedure.

(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the V (3) Wait for 10

DD pin. Keep the VPP pin low.

s, and supply 5 V to the VPP pin. (4) Set the mode in which the program memory address is cleared to 0, by using the mode setting pins. (5) Supply 6 V to VDD and 12.5 V to VPP. (6) Set the program inhibit mode. (7) Write data in the 1-ms write mode. (8) Set the program inhibit mode. (9) Set the verify mode. If the data has been correctly written, proceed to (10). If not, repeat (7) through (9).

(10) Additional writing of (Number of times data has been written in (7) through (9): X) × 1 ms (11) Set the program inhibit mode. (12) Input a pulse four times to the CLK pin to update the program memory address (+1). (13) Repeat (7) through (12) until the data is written to the last address. (14) Set the mode in which the program memory address is cleared to 0. (15) Change the voltage on the V

DD and VPP pins to 5 V.

(16) Turn off power supply.

Program memory writing steps (2) through (12) are illustrated below.

Repeat X times







Reset

Write

GND

VDD+1

GND

CLK

D0-D7

MD0

MD1

Hi-Z Hi-Z Hi-Z Hi-Z

Data input





Verify

Data output





Additional write

Data input

Address increment

MD2

MD3

Page 20

17.3 Program Memory Reading Procedure

(1) Pull down the pins not used to GND via resistor. Keep the CLK pin low. (2) Supply 5 V to the V (3) Wait for 10 µs, and supply 5 V to the VPP pin. (4) Set the mode in which the program memory address is cleared to 0, by using the mode setting pins. (5) Supply 6 V to V (6) Set the program inhibit mode. (7) Set the verify mode. If a clock pulse is input to the CLK pin, the data of one address is output each time the

pulse has been input to the CLK pin four times. (8) Set the program inhibit mode. (9) Set the mode in which the program memory address is cleared to 0.

(10) Change the voltage on the V (11) Turn off power supply.

Program memory reading steps (2) through (9) are illustrated below.

Reset

DD pin. Keep the VPP pin low.

DD and 12.5 V to VPP.

DD and VPP pins to 5 V.

PD61P24

GND

CLK

D0-D7

MD0

MD1

MD2

Hi-Z Hi-Z

“ L ”

Data output Data output

MD3

Page 21

18. INSTRUCTION SET

Accumulator Manipulation Instructions

D00

E00

A00

ANL ANL ANL ANL ORL ORL ORL ORL XRL XRL XRL XRL INC RL

A, R

A, @R0H A, @R0L A, #data A, R

A, @R0H A, @R0L A, #data A A

–

D10 D30 D31

E10 E30 E31

A10 A30 A31 A13

F13

D01

E01

A01

PD61P24

D02

E02

A02

D0F

E0F

A0F

D20

E20

A20

D21

E21

A21

D2F

E2F

A2F

Input/Output Instructions

IN OUT ANL ORL XRL

OUT

P , A, A, A,

A P

#data

F18

218 D18 E18 A18

318

P1P and P0P operate in pair format

Data Transfer Instructions

MOV MOV MOV F30A, @R H0 MOV F31A, #data

MOV R , A

A, @R H

r 200 201 202 20F 220 221 22F

F10

F19 219

D19

E19 A19

319

R10 R11 R12 R1F R00 R01 R0FRr

F00

F1A 21A D1A E1A A1Z

F38 238 D38 E38 A38

F39

239 D39 E39 A39

F3A

23A D3A E3A A3A

31A

F01 F02 F0F F20 F21 F2FA, R

R0 R1 R2 RFRr

MOV MOV

R , @R

300 301 302 30FR , #data 320 321 322 32F

R1r and R0r operate in pair format

Page 22

Branch Instructions

PD61P24

JMP0 JMP0 Rr

JC JC

JNC JNC JF

JF JNF JNF

addr

Note

addr

Note

Rr addr

Note

Rr addr

Note

Rr addr

Note

Note r = 1 through F

r = 0 canot be used.

Subroutine Instructions

CALL0 RET

addr

–

411

– – 401 402 40F

611

–

601

602

631

–

621

–

622

711

–

701

702

731

312

–

411

–

721

722

412

60F

62F

70F

72F

←

Pair register

Timer/Counter Manipulation Instructions

0-1

F1F 21F

F3F

23F

MOV MOV MOV MOV

A, T , T, T,

A #data @R

–

31F 33F

Other Instructions

R HALT #data STTS R

STTS #data SCAF

NOP

111

120 121 122 12F

131

D13

000

Page 23

19. APPLICATION CIRCUIT EXAMPLE

Key matrix

Mode select switch

Infrared LED

SE303 series SE313 SE307-C SE1003-C

Transmission indication

2SC3616, 3618 2SD1615, 1616 2SC2001

3.0 V

47 F

100 pF

0.1 F

I/O1

I/O0

S-IN

1 2 3

5 6

7 8

I/O2

I/O3

S-OUT

REM V

OSC-OUT OSC-IN

I/O4

I/O5

I/O6

I/O7

PD61P24

20 19 18 17 16 15

14 13

12 11

PD61P24

Caution The ceramic resonator start up capacitor value must be determined, by taking the voltage level and

the oscillation start up characteristics for the ceramic resonator into consideration.

Page 24

PD61P24

20. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA =25°C)

Parameter Symbol Ratings Unit Supply Voltage VDD 7.0 V Input Voltage VIN –0.3 to VDD + 0.3 V Operating Ambient Temperature TA –20 to +75 °C Storage Temperature Tstg –40 to +125 °C

Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality

of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure to use the product(s) within the ratings.

Recommended Operating Range (T

Parameter Symbol MIN. TYP. MAX. Unit Supply Voltage VDD 2.2 5.5 V Oscillation Frequency fOSC 400 500 kHz

A =25°C)

Page 25

PD61P24

DC Characteristics (VDD = 3.0 V, fOSC = 455 kHz, TA =25°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply Voltage VDD 2.2 5.5 V Current Consumption 1 IDD1 fOSC = 455 kHz 0.3 1.5 mA Current Consumption 2 IDD2 fOSC = STOP 1.0 REM High Level Output Current IOH1 VO = 1.0 V –5 –8 –15 mA REM Low Level Output Current IOL1 VO = 0.3 V 0.5 1.5 2.5 mA S-OUT High Level Output Current IOH2 VO = 2.7 V –0.3 –1.0 –2.0 mA S-OUT Low Level Output Current IOL2 VO = 0.3 V 1 1.5 2.5 mA KI High Level Input Current IIH1 VI = 3.0 V 10 30 KI High Level Input Current IIH1' VI = 3.0 V, without pull-down resistor 0.2 KI Low Level Input Current IIL1 VI = 0 V –0.2 KI/O High Level Input Current I IH2 VI = 3.0 V 10 30 KI/O High Level Input Current IIH2' VI = 3.0 V, without pull-down resistor 0.2 KI/O Low Level Input Current IIL2 VI = 0 V –0.2 KI/O High Level Output Current IOH3 V0 = 2.5 V –1.5 –2.0 –4.0 mA KI/O Low Level Output Current IOL3 V0 = 2.1 V 25 50 100 S-IN High Level Input Current I IH3 VI = 3.0 V 6 15 S-IN High Level Input Current IIH3' VI = 3.0 V, without pull-down resistor 0.2 S-IN Low Level Input Current IIL3 VI = 0 V –0.2 KI High Level Input Voltage VIH1 2.1 3.0 V KI Low Level Input Voltage VIL1 VI = 3.0 V 0 0.9 V KI/O High Level Input Voltage VIH2 1.3 3.0 V KI/O Low Level Input Voltage VIL2 0 0.4 V S-IN High Level Input Voltage IIH3 1.1 3.0 V S-IN Low Level Input Voltage IIL3 0 0.4 V AC Pull-Up Resistor R1 VI = 0 V 0.3 3.0 kΩ AC Pull-Down Resistor R2 VI = 2.7 V 150 400 1500 kΩ AC High Level Input Voltage VIH4 1.8 3.0 V AC Low Level Input Voltage VIL4 0 1.2 V

Page 26

PD61P24

DC Programming Characteristics (TA = 25±5

Parameter Symbol Conditions MIN. TYP. MAX. Unit

High-level input voltage VIH1 Other than CLK 0.7 VDD VDD V

VIH2 CLK VDD–0.5 VDD V

Low-level input voltage VIL1 Other than CLK 0 0.3 VDD V

VIL2 CLK 0 0.4 V Input leakage current ILI VIN = VIL or VIH 10 High-level output voltage VOH IOH = –1 mA VDD–1.0 V Low-level output voltage VOL IOL = 1.6 mA 0.4 V VDD supply current IDD 30 mA VPP supply current IPP MD0 = VIL, MD1 = VIH 30 mA

°C, VDD = 6.0±0.25 V, VPP = 12.5±0.5 V)

Cautions 1. Keep V PP to within +13.5 V including the overshoot.

2. Apply V

AC Programming Characteristics (TA = 25±5

Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit Address setup time MD1 setup time (vs. MD0↓)tM1S tOES 2 Data setup time (vs. MD0↓)tDS tDS 2 Address hold time Data hold time (vs. MD0↑)tDH tDH 2 MD0↑→ data output float delay time tDF tDF 0 130 ns VPP setup time (vs. MD3↑)tVPS tVPS 2 VDD setup time (vs. MD3↑)tVDS tVCS 2 Initial program pulse width tPW tPW 0.95 1.0 1.05 ms Additional program pulse width tOPW t OPW 0.95 21.0 ms MD0 setup time (vs. MD1↑)tM0S tCES 2 MD0 ↓→ data output delay time tDV tDV MD0 = MD1 = VIL 1 MD1 hold time (vs. MD0↑)tM1H tOEH tM1H + tM1R ≥ 50 µs2 MD1 recovery time (vs. MD0↓)tM1R tOR 2 Program counter reset time tPCR —10 CLK input high-, low-level widths tXH, tXL — 0.125 CLK input frequency fX — 4.19 MHz Initial mode set time tI —2 MD3 setup time (vs. MD1↑)tM3S —2 MD3 hold time (vs. MD1↓)tM3H —2 MD3 setup time (vs. MD0↓)tM3SR — On reading program memory 2 Address Address MD3 hold time (vs. MD0↑)tM3HR — On reading program memory 2 MD3 ↓→ data output float delay time tDFR — On reading program memory 2 Reset setup time tRES 10

Note 2

→ data output delay time tDAD tACC On reading program memory 2

Note 2

→ data output hold time tHAD tOH On reading program memory 0 130 ns

DD before VPP, and turn it off after VPP.

°C, VDD = 6.0±0.25 V, VPP = 12.5±0.5 V)

Note 2

(vs. MD0↓)tAS tAS 2

Note 2

(vs. MD0↑)tAH tAH 2

Notes 1. Corresponding symbols of µPD27C256A (the µPD27C256A is a maintenance product).

2. The internal address signal is incremented by one at the falling edge of CLK input at the third clock.

Page 27

PROGRAM MEMORY WRITE TIMING

PCR

M3S

VPS

VDS

Data input

M1S

RES

GND

CLK

D0-D7

Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

MD0

MD1

MD2

MD3

M1H

M1R

Data output

PD61P24

Data input Data input

M0S

OPW

M3H

PROGRAM MEMORY READ TIMING

RES

GND

CLK

D0-D7

MD0

MD1

VPS

VDS

Hi-Z Hi-Z

PCR

Data output Data output

“ L ”

HAD

DAD

M3HR

DFR

MD2

MD3

M3SR

Page 28

21. PACKAGE DRAWINGS

20 PIN PLASTIC SOP (300 mil)

110

PD61P24

1120

detail of lead end

NOTE

Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

ITEM MILLIMETERS INCHES

13.00 MAX.

0.78 MAX.

1.27 (T.P.) D 0.40 0.016 E

F G H

K 0.20

L 0.6±0.2 0.024 M

P3°

+0.10 –0.05

0.1±0.1

1.8 MAX.

1.55

7.7±0.3

5.6

1.1 +0.10

–0.05

0.12

0.10

+7°

–3°

0.512 MAX.

0.031 MAX.

0.050 (T.P.) +0.004

–0.003

0.004±0.004

0.071 MAX.

0.061

0.303±0.012

0.220

0.043 +0.004

0.008

–0.002 +0.008

–0.009

0.005

0.004

+7°

3°

–3°

P20GM-50-300B, C-4

Page 29

20PIN PLASTIC SHRINK DIP (300 mil)

20 11

110

PD61P24

NOTES

1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition.

2) ltem "K" to center of leads when formed parallel.

ITEM MILLIMETERS INCHES

A 19.57 MAX. 0.771 MAX. B 1.78 MAX. 0.070 MAX. C 1.778 (T.P.) 0.070 (T.P.)

D 0.50±0.10 0.020 F 0.85 MIN. 0.033 MIN.

G 3.2±0.3 0.126±0.012 H 0.51 MIN. 0.020 MIN.

I 4.31 MAX. 0.170 MAX.

J 5.08 MAX. 0.200 MAX. K 7.62 (T.P.) 0.300 (T.P.) L 6.5 0.256

M 0.25 0.010 N 0.17

R 0~15° 0~15°

+0.10 –0.05

+0.004 –0.005

+0.004 –0.003

0.007

P20C-70-300B-1

Page 30

22. RECOMMENDED SOLDERING CONDITIONS

It is recommended that µPD6124A and 6600A be soldered under the following conditions. For details on the recommended soldering conditions, refer to Information Document, Semiconductor Device

Mounting Technology Manual (C10535E).

For other soldering methods and conditions, consult NEC.

Table 22-1. Soldering Conditions of Surface-Mount Type

PD61P24GS: 20-pin plastic SOP (300 mil)

Soldering Method Soldering Conditions

Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per device side)

Table 22-2. Soldering Conditions of Through-Hole Type

PD61P24CS: 20-pin plastic shrink DIP (300 mil)

Soldering Method Soldering Conditions Wave Soldering (Only for pin part) Solder bath temperature: 260°C max., time: 10 seconds max. Partial Heating Pin temperature: 300°C max., time: 3 seconds max. (per pin)

PD61P24

Caution When soldering this product using of wave soldering, exercise care that the solder does not come

in direct contact with the package.

Page 31

APPENDIX A. µPD612× SERIES PRODUCT LIST

PD61P24

Item

Part Number

ROM capacity 1002 × 10 bits 512 × 10 bits 1002 × 10 bits 1002 × 10 bits

RAM capacity 32 × 5 bits I/O pin 8 pins (KI/O0-7) 12 pins 16 pins (KI/O0-7,

S-IN pin Provided Current consumption 2 µA1

(fOSC = STOP) (MAX.) S-IN high-level input 30 µA 15 µA

current (MAX.) Transmission carrier frequency Low-voltage detection Provided None

(reset) function Mask option Provided None (fixed) Provided Supply voltage VDD = 2.2 to 5.5 V V DD = 2.2 to 3.6 V VDD = 2.2 to 5.5 V VDD = 2.0 to 6.0 V Package • 20-pin plastic SOP (300 mil) • 24-pin plastic • 28-pin plastic

PD6124A

(mask ROM) (mask ROM) (one-time PROM) (mask ROM)

fOSC/12, fOSC/8

• 20-pin plastic shrink DIP (300 mil) SOP (300 mil) SOP (375 mil)

PD6600A

PD61P24

PD6125A

(KI/O0-7, I/O00-03) I/O00-03, I/O10-13)

• 24-pin plastic shrink DIP (300 mil)

PD6126A

Page 32

APPENDIX B. DEVELOPMENT TOOLS

The following tools are available for program development using the µPD61P24.

Document Document No.

PS612X Series Emulator —

PS61P24 Assembler —

PROM Programmer AF-9703

AF-9704 AF-9705 AF-9706

PD61P24 Program Adapter AF9807B

Notes 1. These are products from I.C Corp. For details, consult I.C Corp.

I.C Corp. 6th Barnet Gotanda Bldg. 1-9-5 Higashi-Gotanda, Shinagawa-ku, Tokyo 141 Tel. 03-3447-3793 Fax. 03-3440-5606

Note 1

Note 2, 3 Note 2, 3 Note 3 Note 3

Note 3

PD61P24

2. Not available.

3. These are products from Ando Electric Co., Ltd. For details, consult Ando Electric Co., Ltd.

Ando Electric Co., Ltd. 4-19-7 Kamata, Ota-ku, Tokyo 144 Tel. 0120-40-0211(toll-free)

Caution Use a writing program after assembling the program, convert the HEX file to a ROM file by using

the PROM utility program “UPDPROM” (refer to AS612X Assembler User’s Manual(IEM-1016)).

Page 33

[MEMO]

PD61P24

Page 34

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

PD61P24

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

Page 35

PD61P24

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490

NEC Electronics (Germany) GmbH

Benelux Office Eindhoven, The Netherlands Tel:040-2445845 Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France Tel:01-30-67 58 00 Fax: 01-30-67 58 99

NEC Electronics Hong Kong Ltd.

Hong Kong Tel:2886-9318 Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411

NEC Electronics (UK) Ltd.

Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99

NEC Electronics (France) S.A.

Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130 Tel:253-8311 Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689

J96. 8

Page 36

PD61P24

[MEMO]

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.

M4 96.5