Page 1
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
SWITCHING
N-AND P-CHANNEL POWER MOS FET
INDUSTRIAL USE
PA1790
µµµµ
DESCRIPTION
This product is N-and P-Channel MOS Field Effect Transistor
designed for motor driver applications.
FEATURES
Dual chip type
•
Low on-resistance
•
N-Channel R
P-Channel R
Low input capacitance
•
N-Channel C
P-Channel C
Built-in G-S protection diode
•
Small and surface mount package (Power SOP8)
•
DS(on)1
= 0.12 Ω TYP. (VGS = 10 V, ID = 0.5 A)
DS(on)2
R
= 0.19 Ω TYP. (VGS = 4 V, ID = 0.5 A)
DS(on)1
= 0.45 Ω TYP. (VGS = –10 V, ID = –0.35 A)
DS(on)2
R
= 0.74 Ω TYP. (VGS = –4 V, ID = –0.35 A)
iss
= 180 pF TYP.
iss
= 230 pF TYP.
ORDERING INFORMATION
PART NUMBER PACKAGE
PA1790G Power SOP8
µ
Gate
1.44
1.8 MAX.
PACKAGE DRAWING (Unit : mm)
85
14
5.37 MAX.
1.27
0.78 MAX.
+0.10
0.40
0.05 MIN.
–0.05
N-Channel 1 ; Source 1
P-Channel 3 ; Source 2
6.0 ±0.3
+0.10
–0.05
0.15
0.12 M
0.5 ±0.2
2 ; Gate 1
7,8 ; Drain 1
4 ; Gate 2
5,6 ; Drain 2
4.4
EQUIVARENT CIRCUIT
Drain
Body
Diode
Gate
0.8
0.10
Drain
Body
Diode
Remark
The diode connected between the gate and source of the transistor serves as a protector against ESD.
When this device actually used, an additional protection circuit is externally required if a voltage
exceeding the rated voltage may be applied to this device.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. G14320EJ1V0DS00 (1st edition)
Date Published May 1999 NS CP(K)
Printed in Japan
Gate
Protection
Diode
Source
Gate
Protection
Diode
Source
P-ChannelN-Channel
©
1999
Page 2
ABSOL UTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
PARAMETER SYMBOL N-CHANNEL P-CHANNEL UNIT
Drain to Source Voltage (VGS = 0 V) V
Gate to Source Voltage (VDS = 0 V) V
Drain Current (DC) I
Drain Current (pulse)
Total Power Dissipation (1 unit)
Total Power Dissipation (2 unit)
Note1
Note2
Note2
Channel Temperature T
Storage Temperature T
DSS
GSS
D(DC)
D(pulse)
I
P
P
ch
stg
60 –60 V
±20
±1.0
±4.0
T
T
#
#
#
1.7 W
2.0 W
150 °C
–55 to +150 °C
20
0.7
2.8
µµµµ
PA1790
V
A
A
Notes 1.
PW ≤ 10
2.
Mounted on ceramic substrate of 2000 mm2 x 2.25 mm
s, Duty Cycle ≤ 1 %
µ
2
Data Sheet G14320EJ1V0DS00
Page 3
ELECTRICAL CHARACTERISTICS (TA = 25 °C, All terminals are connected.)
N-CHANNEL
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TY P. MAX. UNIT
µµµµ
PA1790
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= 10 V, ID = 0.5 A 0.12 0.26
= 4 V, ID = 0.5 A 0.19 0.34
= 10 V, ID = 1 mA 1.0 1.7 2.5 V
Forward Transfer Admittance | yfs |VDS = 10 V, ID = 0.5 A 1.0 1.7 S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = 60 V, VGS = 0 V 10
GSS
VGS = ±16 V, VDS = 0 V ±10
iss
VDS = 10 V 180 pF
oss
VGS = 0 V 100 pF
rss
f = 1 MHz 35 pF
d(on)ID
d(off)
GS
GD
F(S-D)IF
rr
= 0.5 A 1 ns
r
GS(on)
V
= 10 V 1.4 ns
VDD = 30 V 23 ns
f
RG = 10
G
ID = 1.0 A 8 nC
Ω
VDD = 48 V 1 nC
VGS = 10 V 3.5 nC
= 1.0 A, VGS = 0 V 0.75 V
IF = 1.0 A, VGS = 0 V 30 ns
rr
di/dt = 100 A /
s33nC
µ
17 ns
Ω
Ω
A
µ
A
µ
TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE
IG = 2 mA
50 Ω
D.U.T.
R
L
V
DD
PG.
V
GS
RG = 10 Ω
0
τ
τ = 1 s
µ
Duty Cycle ≤ 1 %
R
G
D.U.T.
V
L
R
V
Wave Form
V
DD
I
D
Wave Form
GS
GS
0
10 %
V
GS(on)
90 %
PG.
90 %
D
I
10 %
0
t
r
t
d(on)
t
on
Data Sheet G14320EJ1V0DS00
90 %
I
D
t
d(off)
10 %
t
f
t
off
3
Page 4
P-CHANNEL
CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TY P. MAX. UNIT
µµµµ
PA1790
Drain to Source On-state Resi stance R
Gate to Source Cut-off Voltage V
DS(on)1VGS
DS(on)2VGS
R
GS(off)VDS
= –10 V, ID = –0.35 A 0.45 0.6
= –4 V, ID = –0.35 A 0.74 1.1
= –10 V, ID = –1 mA –1.0 –1.7 –2.5 V
Forward Transfer Admittance | yfs |VDS = –10 V, ID = –0.35 A 5.0 S
Drain Leakage Current I
Gate to Source Leakage Current I
Input Capacitance C
Output Capacitance C
Reverse Transfer Capacitance C
Turn-on Delay Time t
Rise Time t
Turn-off Delay Time t
Fall Time t
Total Gate Charge Q
Gate to Source Charge Q
Gate to Drain Charge Q
Body Diode Forward Voltage V
Reverse Recovery Time t
Reverse Recovery Charge Q
DSS
VDS = –60 V, VGS = 0 V –10
VGS = #16 V, VDS = 0 V
GSS
iss
VDS = –10 V 230 pF
oss
VGS = 0 V 100 pF
rss
f = 1 MHz 25 pF
d(on)ID
d(off)
GS
GD
F(S-D)IF
rr
= –0.35 A 1.9 ns
r
GS(on)
V
= –10 V 1.7 ns
VDD = –30 V 30 ns
f
RG = 10
G
ID = –0.7 A 7.6 nC
Ω
VDD = –48 V 1 nC
VGS = –10 V 2 nC
= 0.7 A, VGS = 0 V 0.85 V
IF = 0.7 A, VGS = 0 V 58 ns
rr
di/dt = 100 A /
s 130 nC
µ
#
10
15 ns
Ω
Ω
A
µ
A
µ
TEST CIRCUIT 1 SWITCHING TIME TEST CIRCUIT 2 GATE CHARGE
IG = 2 mA
50 Ω
D.U.T.
R
L
V
DD
PG.
V
GS
RG = 10 Ω
0
τ
τ = 1 s
µ
Duty Cycle ≤ 1 %
R
G
D.U.T.
V
L
R
V
Wave Form
V
DD
I
D
Wave Form
GS
GS
0
10 %
V
GS(on)
90 %
PG.
90 %
D
I
10 %
0
t
r
t
d(on)
t
on
90 %
I
D
t
d(off)
10 %
t
f
t
off
4
Data Sheet G14320EJ1V0DS00
Page 5
[MEMO]
µµµµ
PA1790
Data Sheet G14320EJ1V0DS00
5
Page 6
[MEMO]
µµµµ
PA1790
6
Data Sheet G14320EJ1V0DS00
Page 7
[MEMO]
µµµµ
PA1790
Data Sheet G14320EJ1V0DS00
7
Page 8
µµµµ
PA1790
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
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systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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