Page 1
uP7706
A
3A Ultra Low Dropout Linear Regulator
General Description
The uP7706 is a 3A ultra low dropout linear regulator
specifically designed for motherboard and notebook
applications. This device works with dual supplies, a control
input for the control circuitry and a power input as low as
1.2V for providing current to output. The uP7706 delivers
high-current and ultra-low-drop output voltage as low as
0.8V for applications where V
is very close to VIN.
OUT
The uP7706 features comprehensive control and protection
functions: a power on reset (POR) circuit for monitoring
both control and power inputs for proper operation; an EN
input for enabling or disabling the device, a power OK with
time delay for indicating the output voltage status, a
foldback current limit function, and a thermal shutdown
function.
The uP7706 is available in PSOP-8 or VDFN6x5-8L
packages with very low thermal resistance.
pplications
Desktop PCs, Notebooks, and Workstations
Graphic Cards
Low Voltage Logic Supplies
Microprocessor and Chipset Supplies
Split Plane Microprocessor Supplies
Advanced Graphics Cards Supplies
SoundCards and Auxiliary Power Supplies
SMPS Post Regulators
Features
Works with 1.2~5.5V V
Adjustable Output Voltage, Down to 0.8V
1.5% Initial Accuracy
Excellent Line and Load Regulation
3A Guaranteed Output Current
IN
200mV @ 2A Dropout Voltage
Very Low On-Resistance
100m
V
OUT
Low Reverse Leakage (Output to Input )
V
OUT
Fast Transient Response
Low External Component Count
Low Cost and Easy to Use
Enable Pin
Over Current and Over Temperature Protection
ΩΩ
Ω typical
ΩΩ
Pull Low Resistance when Disabled
Power OK Signal
Ordering Information
rebmuNredrOepyTegakcaPkrameR
8U6077Pu8-POSP
8CDA6077PuL8-5x6NFDV
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 and RoHS requirements. They are
100% matte tin (Sn) plating and suitable for use in SnPb
or Pb-free soldering processes.
Pin Configuration & Typical Application Circuit
GNDPOK
8
FB
7
VOUT
6
NC
8
GND
FB
7
6
VOUT
5
NC
EN
VIN
CNTL
POK
VIN
CNTL
1
2
GND
3
45
PSOP-8
1
2
EN
3
4
GND
DFN6x5- 8L
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
5VCC
V
IN
C1
0.1uF
C2
22uF
EN
CNTL
2
3
4
8
uP7706
GND
POK
1
R3
VOUTVIN
6
FB
7
10K
R2
12.5K
R1
10K
C4
option
V
OUT
C3
100uF
1
Page 2
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Functional Pin Descriptio
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Functional Block Diagram
CNTLEN
2
Thermal Limit
0.3V
7
0.8V V
92% V
REF
Softstart &
Control Logic
REF
Delay
1
POK GND
4
Power On
Reset
Current Limit
VIN
3
6
8
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
2
Page 3
uP7706
Functional Description
Definitions
Some important terminologies for LDO are specified below.
Dropout Voltage
The input/output voltage differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. Measured when the output drops
2% below its nominal value. Dropout voltage is affected by
junction temperature, load current and minimum input
supply requirements.
Line Regulation
The change in output voltage for a change in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse techniques such that average
chip temperature is not significantly affected.
Load Regulation
The change in output voltage for a change in load current
at constant chip temperature. The measurement is made
under conditions of low dissipation or by using pulse
techniques such that average chip temperature is not
significantly affected.
Maximum Power Dissipation
The maximum total device dissipation for which the
regulator will operate within specifications.
Initialization
The uP7706 automatically initiates upon the receipt of
supply voltage and power voltage. A power on reset circuit
continuously monitors VIN and CNTL pins voltages with
rising threshold levels of 1.0V and 2.7V respectively.
It’s recommended to maintain 50-100uA through the output
divider network for a tight load and line regulation. The
internal voltage reference is V
= 0.8V with 1.5%
REF
accuracy over full temperature range. This commands the
use of 0.5% or better accuracy resistors to build a precision
power supply.
5VCC
CNTL
4
8
uP7706
GND
POK
1
R3
10K
VOUTVIN
6
7
R2
12.5K
FB
R1
10K
C4
option
V
OUT
100uF
C3
C2
22uF
EN
2
3
C1
0.1uF
V
IN
Figure 1. Typical application of 2.5V to 1.8V conversion
with a 5.0V control supply
Over Current Protection
The uP7706 features a foldback over current protection
function as shown in Figure 2. The current limit threshold
level is proportional to V
V
OUT
= V
, where V
NOM
NOM
OUT/VNOM
is the target output voltage. If the
and is typically 4A when
output continuously demands more current than the
maximum current, output voltage will eventually drops below
its nominal value. This, in turns, will lower its OCP threshold
level. This will limit power dissipation in the device when
over current limit happens. The power dissipation is near
zero when the output is short circuited to ground.
Chip Enable and Soft Start
The uP7706 features an enable pin for enable/disable
control of the chip. Pulling VEN lower than 0.8V disables
the chip and reduces its quiescent current down to 1uA.
When disabled, an internal MOSFET of 90Ω R
DS(ON)
turns
on to pull output voltage to ground. Pulling VEN higher than
2.0V enables the output voltage, providing POR is
recognized. The uP7706 features soft start function that
limits inrush current for charging the output capacitors. The
soft start time is typically 2.5ms.
Output Voltage Programming
Figure 1 shows a typical application of 2.5V to 1.8V
conversion with a 5.0V control supply. The output voltage
is sensed through a voltage divider and regulated to internal
reference voltage V
. The output voltage is programmed
REF
as:
V
= V
OUT
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
x (R1+R2) / R1 = 0.8V x (22.5k/10k) = 1.8V
REF
V
OUT
3V
2A
1V
0A 1A 2A 3A 4A
Figure 2. Current Limit Behavior
I
OUT
3
Page 4
uP7706
A
g
n
bsolute Maximum Ratin
Control Input Voltage V
Power Input Voltage V
Other Pins --------------------------------------------------------------------------------------------------------------- −0.3V to (V
(Note 1) -------------------------------------------------------------------------------------------------- -0.3V to +6V
CNTL
--------------------------------------------------------------------------------------------------------------------- -0.3V to +6V
IN
+ 0.3V)
CNTL
Storage Temperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC
Junction Temperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
Lead Temperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V
Thermal Informatio
Package Thermal Resistance (Note 3)
PSOP-8 θJA ---------------------------------------------------------------------------------------------------------------------------------- 52°C/W
PSOP-8 θJA ------------------------------------------------------------------------------------------------------------------------------------- 5°C/W
VDFN6x5-8L θJA ----------------------------------------------------------------------------------------------------------------------------- 45°C/W
VDFN6x5-8L θJC ------------------------------------------------------------------------------------------------------------------------------ 4°C/W
Power Dissipation, PD @ T
= 25°C
A
PSOP-8 ------------------------------------------------------------------------------------------------------------------------------------------- 1.9W
VDFN6x5-8L ------------------------------------------------------------------------------------------------------------------------------------ 2.2W
Recommended Operation Conditions
Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C
Operating Ambient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C
Supply Input Voltage, V
------------------------------------------------------------------------------------------------------------ +4.5V to +5.5V
CNTL
Electrical Characteristics
(V
= 5V, TA = 25OC, unless otherwise specified)
CNTL
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V,A0=
V=
TUO
FER
0.3--5.5V
--7.2--V
--2.0--V
0.1--5.5V
--0.15.1Am
--0.15.1Am
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
4
Page 5
uP7706
Electrical Characteristics
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Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. θ
is measured in the natural convection at T
JA
= 25°C on a low effective thermal conductivity test board of
A
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
C
C
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
5
Page 6
uP7706
Typical Operation Characteristics
V
=5V, VIN = 3.3V, C
CNTL
Power On from V
1ms/Div
= 1000uF, No Load.
OUT
Turn On from EN
IN
V
POK (5V/Div)
VEN (5V/Div)
V
VIN (2V/Div)
(1V/Div)
OUT
IIN (1A/Div)
(1V/Div)
OUT
Power On from V
CNTL
V
CNTL
V
POK (5V/Div)
1ms/Div
V
=5V, VIN = 3.3V, C
CNTL
= 1000uF, No Load.
OUT
Dropout Voltage vs. Output Current
300mV
(5V/Div)
(1V/Div)
OUT
IIN (1A/Div)
Output Voltage (V)
V
=5V, VIN = 3.3V, C
CNTL
2V
1.5V
1V
0.5V
0V
POK (5V/Div)
1ms/Div
= 1000uF, No Load.
OUT
Output Short Circuit
0A 1A 2A 3A 4A 5A
IIN (1A/Div)
Dropout Voltgae (mV)
200mV
100mV
0mV
0A 1A
2A
Output Current (A)
Ouput Voltage vs. Ouptut Current
0A 1A 2A 3A
0mV
2mV
4mV
3A
Output Current (A)
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
Output Voltage Deviation (mV)
Output Current (A)
6
Page 7
uP7706
Typical Operation Characteristics
Load Transient Response
(5mV/D iv)
25us/Div
C
= 22uF/X5R
OUT
Shutdown Current vs. Input Voltage
80
70
60
50
40
30
20
Shutdown Current (uA)
10
0
2.5 3 3.5 4 4.5 5 5.5 6
Input Voltage V
CNTL
= VIN (V)
V
OUT
I
OUT
(1A/Div)
Quiescent Current vs. Input Voltage
1200
1000
800
600
400
Quiescent Current (uA)
200
0
2.533.544.555.56
Input Voltage V
CNTL
= VIN (V)
Line Regulation
0.81
0.808
0.806
(V)
FB
0.804
0.802
0.8
0.798
0.796
0.794
Feedback Voltage V
0.792
0.79
2.53 3.544.555.56
Input Voltage V
CNTL
= VIN (V)
Quiescent Current vs. Temperature
1400
1200
1000
800
600
400
Quiescent Current (uA)
200
0
- 50 -25 0 25 50 75 100 125
Junction Temperature (OC)
V
= VIN = 5V
CNTL
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
Shutdown Current vs. Temperature
25
20
15
10
Shutdown Current (uA)
5
0
-50-25 0 255075100125
Junction Temperature (OC)
V
= 5V
CNTL
7
Page 8
uP7706
Typical Operation Characteristics
0. 81
0.808
0.806
(V)
FB
0.804
0.802
0.8
0.798
0.796
0.794
Feedback Voltage V
0.792
0. 79
FB Voltage vs. Temperature
-50 -25 0 25 50 75 100 125
Junction Temperature (OC)
V
= 5V, VIN = V
CNTL
OUT
+ 1V
On Resistance vs. Temperature
140
120
100
80
60
40
On Resistance (mΩ)
20
0
-50-250255075100125
Junction Temperature (OC)
V
CNTL
= 5V, V
OUT
= 1.6V
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
8
Page 9
uP7706
A
pplication Information
The uP7706 is a high performance linear regulator
specifically designed to deliver up to 3A output current with
very low input voltage and ultra low dropout voltage. With
dual-supply configuration, the uP7706 operates with a wide
input voltage VIN range from 1.0V to 5.5V and is ideal for
applications where VOUT is very close to VIN .
Supply Voltage for Control Circuit V
CNTL
Unlike other linear regulators that use a P-Channel
MOSFET as the pass transistor, the uP7706 uses an NChannel as the pass transistor. N-Channel MOSFET
provides lower on-resistance and better stability meeting
stringent requirements of current generation
microprocessors and other sensitive electronic devices.
The drain of N-Channel MOSFET is connected to VIN and
the source is connected to VOUT. This requires that the
supply voltage V
for control circuit is at least 1.5V higher
CNTL
than the output voltage to provide enough overdrive capability
for the pass transistor thus to achieve low dropout and fast
transient response. It is highly recommended to bias the
device with 5V voltage source if available.
Use a minimum 0.1uF ceramic capacitor plus a 10Ω
resistor to locally bypass the control voltage.
Input/Output Capacitor Selection
The uP7706 has a fast transient response that allows it to
handle large load changes associated with high current
applications. Proper selection of the of the output capacitor
and it’s ESR value determines stable operation and
optimizes performance. The typical application circuit
shown in Figure 1 was tested with a wide range of different
capacitors. The circuit was found to be unconditionally
stable with capacitor values from 10ìF to 2200ìF and ESR
ranging from 0.5mΩ to greater then 75mΩ.
5VCC
CNTL
4
8
uP7706
GND
POK
1
R3
10K
VOUTVIN
6
7
R2
12.5K
FB
R1
10K
C4
option
V
OUT
C3
100uF
C2
22uF
EN
2
3
C1
0.1uF
V
IN
Figure 1. Typical Application Circuit
Input capacitor: A minimum of 10uF ceramic capacitor is
recommended to be placed directly next to the VIN pin.
This allows for the device being some distance from any
bulk capacitance on the rail. Additionally, bulk capacitance
may be added closely to the input supply pin of the uP7706
to ensure that VIN does not sag, improving load transient
response.
Output capacitor: A minimum bulk capacitance of 33uF,
along with a 0.1uF ceramic decoupling capacitor is
recommended. Increasing the bulk capacitance will improve
the overall transient response. The use of multiple lower
value ceramic capacitors in parallel to achieve the desired
bulk capacitance will not cause stability issues. Although
designed for use with ceramic output capacitors, the uP7706
is extremely tolerant of output capacitor ESR values and
thus will also work comfortably with tantalum output
capacitors.
Thermal Consideration
The uP7706 integrates internal thermal limiting function to
protect the device from damage during fault conditions.
However, continuously keeping the junction near the thermal
shutdown temperature may remain possibility to affect
device reliability. It is highly recommended to keep the
junction temperature below the recommended operation
condition 125OC for maximum reliability.
Power dissipation in the device is calculated as:
PD = (VIN - V
OUT
) x I
OUT
+ V
CNTL
x I
CNTL
It is adequate to neglect power loss with respective to
control circuit V
CNTL
x I
when considering thermal
CNTL
management in uP7706 Take the following moderate
operation condition as an example: VIN = 2.5V, V
I
= 2A, the power dissipation is:
OUT
OUT
= 1.5V,
PD = (1.8V- 1.2V) x 2A = 2.0W
This power dissipation is conducted through the package
into the ambient environment, and, in the process, the
temperature of the die (TJ) rises above ambient. Large power
dissipation may cause considerable temperature raise in
the regulator in large dropout applications. The geometry
of the package and of the printed circuit board (PCB) greatly
influence how quickly the heat is transferred to the PCB
and away from the chip. The most commonly used thermal
metrics for IC packages are thermal resistance from the
chip junction to the ambient air surrounding the package
(θ
):
JA
θ
= ( TJ -TA ) / P
JA
θ
specified in the Thermal Information section is measured
JA
D
in the natural convection at TA = 25OC on a high effective
thermal conductivity test board (4 Layers, 2S2P) of JEDEC
51-7 thermal measurement standard. The case point of
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
9
Page 10
θ
A
is on the exposed pad for PSOP-8 package.
JC
Given power dissipation PD, ambient temperature and
thermal resistance θ
, the junction temperature is
JA
calculated as:
TJ = T
+ ∆T
A
= TA + P
JA
D
x θ
JA
To limit the junction temperature within its maximum rating,
the allowable maximum power dissipation is calculated
as:
P
= ( T
D(MAX)
where T
-T
J(MAX)
J(MAX)
) /θ
A
JA
is the maximum operation junction
temperature 125OC, TA is the ambient temperature and the
θJA is the junction to ambient thermal resistance. θ
of
JA
PSOP-8 packages is 75OC/W on JEDEC 51-7 (4 layers,
2S2P) thermal test board with minimum copper area. The
maximum power dissipation at TA = 25¢XC can be calculated
as:
P
= (125OC - 25OC) / 75OC/W = 1.33W
D(MAX)
The thermal resistance θ
highly depends on the PCB
JA
design. Copper plane under the exposed pad is an effective
heatsink and is useful for improving thermal conductivity.
Figure 3 show the relationship between thermal resistance
θ
vs. copper area on a standard JEDEC 51-7 (4 layers,
JA
2S2P) thermal test board at TA = 25OC. A 50mm2 copper
plane reduces θ
from 75OC/W to 50OC/W and increases
JA
maximum power dissipation from 1.33W to 2W.
uP7706
pplication Information
GNDPOK
FB
VOUT
6
7
8
GND
1
2
3
EN
VIN
Figure 4. Recommended PCB Layout.
Layout Consideration
1. Place a local bypass capacitor as closed as possible
to the VIN pin. Use short and wide traces to minimize
parasitic resistance and inductance.
2. The exposed pad should be soldered on GND plane
with maximum area and with multiple vias to inner layer
of ground place for improved thermal performance.
3. Connect voltage divider directly to the point where
regulation is required. Place voltage divider close to
the device.
uP7706
45
CNTL
100
90
C/W)
80
O
(
JA
70
60
50
T herm a l Re si stanc e θ
40
30
Copper Area (mm2)
60 7050403020100
Figure 3. Thermal Resistance èJA vs. Copper Area
Figure 4 illustrated the recommended PCB layout for best
thermal performance.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
10
Page 11
uP7706
A
pplication Information
PSOP-8 Package
0.76 REF
1.27 REF
4.80 - 5.00
1.85 REF
2.39 REF
5.80 - 6.20
6.15 REF
8.00 MIN
2.39 REF
4.00 MIN
3.80 - 4.00
2.29 BSC
2.29 BS C
1.27 BSC
0.32 - 0.52
Recommended Solder Pad Layout
1.45 - 1.60
0.20 BSC
0.41 - 0.89
0.18 - 0.25
1.75 MAX
0.10 - 0.25
3.81 BSC
Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
11
Page 12
VDFN6x5-8L Package
A
uP7706
pplication Information
4.90 - 5.10
5.90 - 6.10
0.50 - 0.75
58
3.30 - 3.50
3.90 - 4.10
14
0.35 - 0.481.27 BSC
3.90 - 4.10
1.00 MAX
4.30 - 4.50
6.80 - 7.00
3.30 - 3.50
0.00 - 0.050.20 REF
0.40 - 0.501.27 BSC
Recommended Solder Pitch and Dimensions
Note
1.Package Outline Unit Description:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7706-DS-F0000
12
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