Datasheet up7704 Datasheets

uP7704

A

2A Ultra Low Dropout Line ar Regulator

General Description

The uP7704 is a 2A ultra low dropout linear regulator
specifically designed for motherboard, notebook a nd gra phic
card a pplications. This device works with dual supplies, a
control input for the control circuitry and a power in put as
low as 1.2V for providing current to output. The uP7704
delivers high-current and ultra-low-drop output voltage a s
low as 0.8V for applications where V

is very close to

OUT

VIN.
The uP7704 features comprehensive control a nd protection

functions: a power on reset (POR) circuit for monitoring
both control and power inputs f or proper operation; an EN
input for enabling or disabling the device, a power OK with
time delay for indicating the output voltage status, a
foldback current limit function, and a thermal shutdown
function.

The uP7704 is available in PSOP-8 or WDFN3x3-10L
package s with very low thermal resistance.

pplications



 Desktop PCs, Notebooks, and Workstations





 Graphic Cards





 Low Voltage Logic Supplies





 Microprocessor and Chipset Supplies





 Split Plane Microprocessor Supplies





 Advanced Gra phics Cards Supplies





 SoundCards and Auxiliary Power Supplies





 SMPS Post Regulators



Features



 Works with 1.2V~5.5V V





 Adjustable Output Voltage, Down to 0.8V





 1.5% Initial Accuracy





 Excellent Line and Load Regulation





 2A Guaranteed Output Current



IN

 300mV @ 2A Dropout Voltage



 Very Low On-Re sistance



 150m



 V



OUT



 V



OUT



 Fast T ran sient Respon se





 Low External Component Count





 Low Cost and Ea sy to Use





 Enable Pin





 Over Current and Over Temperature Protection



ΩΩ

Ω typical

ΩΩ

Pull Low Resistance when Disabled
Power OK Signal

Ordering Inf o rmation

rebmuNredrOepyTegakcaPkrameR

8U4077Pu8-POSP

ADDA4077PuL01-3x3NFDW

Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 a nd RoHS requirements. They are 100%
matte tin (Sn) plating and suitable f or use in SnPb or Pb­free soldering processes.

Pin Configuration & Typical Application Circuit

1
2

VIN

CNTL

VOUT
VOUT
VOUT

FB

POK

GND

3
45

PSOP-8

1
2
3

GND

4
5 EN6

WDFN3x3-10L

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

GNDPOK

8

FBEN

7

VOUT

6

NC

10

CNTL
VIN

9
8

VIN

7

VIN

5VCC

V

IN

R4

10R

C2

4.7uF

C1

1uF

EN

NC

CNTL

uP7704

GND

POK

VOUTVIN

FB

R3

10K

R2

12.5K

R1

10K

C4

option

V

OUT

C3

10uF

1

uP7704

n

Function al Pin Descriptio

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FB

90% V

Thermal Limit

REF

0.8V

Softstart &

Control Logic

Delay

CNTLEN

Power On

Reset

Current Limit

Functional Block Diagram

VIN

VOUT

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

POK GND

2

uP7704

Functional Description

Definitions

Some important terminologie s for LDO are specified below .

Dropout V oltage

The input/output voltage differential at which the regulator
output no longer maintains regulation against further
reductions in input voltage. Mea sured when the output drops
2% below its nominal value. Dropout voltage is af fected by
junction temperature, load current and minimum input
supply requirements.

Line Regulation

The change in output voltage for a cha nge in input voltage.
The measurement is made under conditions of low
dissipation or by using pulse techniques such that average
chip temperature is not significa ntly affected.

Load Regulation

The change in output voltage f or a change in loa d current
at constant chi p temperature. The measurement is made
under conditions of low dissipation or by using pulse
techniques such that average chip temperature is not
significantly affe cted.

Maximum Power Dissipation

The maximum total device dissipation for which the
regulator will operate within specifications.

Output Voltage Programming

Figure 1 shows a typical application of 2.5V to 1.8V
conversion with a 5.0V control supply . The output voltage
is sensed through a voltage divider and regulated to intern al
reference voltage V

. The output voltage is progra mmed

REF

as:
V

= V

OUT

x (R1+R2) / R1 = 0.8V x (22.5k/10k) = 1.8V

REF

It’s recommended to maintain 50-100uA through the output
divider network for a tight load and line regulation. The
internal voltage reference is V

= 0.8V with 1.5% initial

REF

accuracy. This commands the use of 0.5% or better
accura cy resistors to build a pre cision power supply .

5VCC

R4

10R

V

IN

C1

1uF

C2

4.7uF

EN

NC

CNTL

uP7704

GND

POK

VOUTVIN

FB

R3

10K

R2

12.5K

R1

10K

C4

option

V

OUT

C3

10uF

Quiescent Bia s Current

Current which is used to operate the regulator chip a nd is
not delivered to the load.

The quiescent current IQ is defined as the supply current
used by the regulator itself that does not pass into the
load. It typically includes all bias currents required by the
LDO and any drive current f or the pa ss tran sistor .

Initialization

The uP7704 automatically initiates upon the receipt of
supply voltage and power voltage. A power on reset circuit
continuously monitors VIN and CNTL pins voltages with
rising threshold levels of 0.6V a nd 2.7V respectively .

Chip Enable and Soft Start

The uP7704 features an enable pin for enable/disable
control of the chip. Pulling VEN lower than 0.4V disables
the chip a nd reduces its quiescent current down to 25uA.
When disabled, an intern al MOSFET of 50Ω R

DS(ON)

turns

on to pull output voltage to ground. Pulling VEN higher than

1.4V enables the output voltage, providing POR is
recognized. The uP7704 features soft start function that
limits inrush current for charging the output ca pa citors. The
soft start time is typically 4ms.

Figure 1. T ypical a pplication of 2.5V to 1.8V conversion

with a 5.0V control supply

Over Current and Short Circuit Protection

The uP7704 features a foldback over current protection
function as shown in Figure 2. The current li mit threshold
level is proportional to V
V

= V

OUT

, where V

NOM

NOM

OUT/VNOM

is the target output voltage. If the

and is typically 2.5A when

output continuously demands more current than the
maximum current, output voltage will eventually drops below
its nominal value. This, in turns, will lower its OCP threshold
level. This will limit power dissipation in the device when
over current limit ha ppens.

When output short circuit occurs, the uP7704 will try to
rebuild the output voltage with maximum allowable current
as shown if Figure 3. The duty cycle is about 20% a nd the
averaged short circuit current is about 400mA.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

3

2.0V

1.5V

1.0V

0.5V

uP7704

Functional Description

V

IN

VOUT

(20mV/Div)

(1V/Div)

0V

0A 0.5A 1.0A 1.5A 2.0A 2.5A

Figure 2. Current Limit Behavior

3.0A 3.5A

I

IN

(0.5A/Div)

Figure 3. Output Short Circuit Protection

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

4

uP7704

A

g

n

bsolute Ma x imum Ratin

Control Input V oltage V
Power Input V oltage V

Other Pins --------------------------------------------------------------------------------------------------------------- -0.3V to (V

(Note 1) ------------------------------------------------------------------------------------------------- -0.3V to +7V

CNTL

-------------------------------------------------------------------------------------------------------------------- -0.3V to +7V

IN

+ 0.3V)

CNTL

Storage T emperature Range ----------------------------------------------------------------------------------------------------------- -65OC to +150OC
Junction T emperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
Lead T e mperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)

HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V

Thermal Informatio

Pack age Thermal Resistance (Note 3)

PSOP-8 θJA ---------------------------------------------------------------------------------------------------------------------------------- 52°C/W
PSOP-8 θJC ---------------------------------------------------------------------------------------------------------------------------------- 5°C/W
W DFN3x3-10L θJA -------------------------------------------------------------------------------------------------------------------------- 60°C/W
W DFN3x3-10L θJC ------------------------------------------------------------------------------------------------------------------------- 5°C/W

Power Dissipation, PD @ TA = 25°C

PSOP-8 ------------------------------------------------------------------------------------------------------------------------------------------- 1.9W
W DFN3x3-10L θJA -------------------------------------------------------------------------------------------------------------------------- 1.67W

Recommen de d Op er at i o n Conditi on s

Operating Junction T emperature Ra nge (Note 4) ------------------------------------------------------------------------ -40°C to +125°C
Operating Ambient T emperature Range -------------------------------------------------------------------------------------- -40°C to +85°C
Supply Input V oltage, V
Power Input V oltage, V

------------------------------------------------------------------------------------------------------------ +3.0V to +5.5V

CNTL

------------------------------------------------------------------------------------------------------------ +1.0V to V

IN

CNTL

Electrical Characteristics

(V

= 5V, TA = 25OC, unless otherwise specified)

CNTL

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LTNC

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LTNC

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V

LTNC

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--10.01.0V/%

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

5

uP7704

Electrical Characteristics

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Note 1. Stresses listed a s the above “Absolute Maximum Ratings” may cause permanent damage to the device.

These are for stress ratings. Functional operation of the device at the se or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to af fect device relia bility .

Note 2. Devices are ESD sen sitive. Handling precaution recommended.
Note 3. θJA is mea sured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of

JEDEC 51-7 thermal mea surement sta ndard.

Note 4. The device is not guaranteed to function outside its operating conditions.

C

C

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

6

uP7704

Typical Operation Characteri stics

Power On from V

V

= VIN = 5V, C

CNTL

Turn On Waveform

2.5ms/Div
= 470uF, No Load.

OUT

CNTL

(0.5V/Div)

(0.5A/Div)

V

CNTL

(2V/Div)

V

OUT

POK

(2V/Div)

I

IN

EN

(2V/Div)

V

(0.5V/Div)

OUT

Power On from V

V

= VIN = 5V, C

CNTL

Power Off from V

2.5ms/Div
= 470uF, No Load.

OUT

IN

CNTL

V

CNTL

(2V/Div)

V

IN

(2V/Div)

V

OUT

(0.5V/Div)

POK

(2V/Div)

I

IN

(0.5A/Div)

V

= VIN = 5V, C

CNTL

2.5ms/Div
= 470uF, No Load.

OUT

Power Off from V

(2V/Div)

(0.5A/Div)

IN

V

IN

(2V/Div)

V

OUT

(0.5V/Div)

POK

(2V/Div)

I

IN

(0.5A/Div)

POK

I

IN

2.5ms/Div

VIN = 5V , C

= 470uF , I

OUT

T urn Off W aveforms

POK

(2V/Div)

V

OUT

(0.5V/Div)

I

IN

(0.5A/Div)

= 0.2A.

OUT

V

OUT

(0.5V/Div)

V

EN

(5V/Div)

POK

(5V/Div)

I

IN

(0.5A/Div)

2.5ms/Div

V

CNTL

= 5V, C

= 470uF, I

OUT

= 0.2A.

OUT

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

V

= VIN = 5V , C

CNTL

2.5ms/Div
= 470uF , I

OUT

= 0.2A.

OUT

7

uP7704

Typical Operation Characteri stics

400

350

300

Load T ra n sient Re spon se

V

OUT

(50mV/Div)

I

OUT

(1A/Div)

2.5us/Div

V

CNTL

= 5V , C

= 4.7uF, I

OUT

= 0A to 1.6A

OUT

Quiescent Current vs. Input Voltage

Dropout V oltage vs. Output Current

300mV

250mV

200mV

150mV

100mV

Dropout Voltage (mV)

50mV

0mV

0.5A 1.0A 1.5A

0A 2.0A

Output Current (A)

Enable/Disable Threshold vs. Input Voltage

1.2
Disab le

1.1
Enable

1

250

200

150

100

Quiescent Current (uA)

50

0

2.5 3 3.5 4 4.5 5 5.5

VIN = V

V

OUT

CNTL

= V

(V)

REF

Output Voltage Line Regulation

0.1

0.05

0

-0.05

-0.1

0.9

0.8

0.7

0.6

0.5

Enable/Disable Threshold (V)

0.4

2.533.544.5 55.5

VIN = V

V

OUT

CNTL

= V

(V)

REF

Output Voltage Load Regulation

0.9

0.7

0.5

0.3

0.1

-0.1

-0.15

Output Voltage Variation (%)

-0.2

2.5 3 3.5 4 4.5 5 5.5

VIN = V

CNTL

(V)

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

-0.3

Output voltage Variation (%)

-0.5

0 0.5 1 1.5 2

Output Current (A)

8

uP7704

Typical Operation Characteri stics

On Resista nce vs. In put Voltage

200
190
180
170
160
150
140
130

On Resistance (mΩ)

120
110
100

2.533.544.555.5

Control Input V

V

= 1.8V

OUT

CNTL

(V)

Current Limit

2.0V

Output Voltage vs. Temperature

1

0.5

0

-0.5

-1

-1.5

Output Voltage Variation (%)

-2

-50 0 50 100 150

Junction Temperature (OC)

Output V oltage (V)

1.5V

1.0V

0.5V

0V

0A 0.5A 1.0A 1.5A 2.0A 2.5A

Output Current (A)

3.0A 3.5A

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

9

uP7704

A

pplication I nformation

The uP7704 is a high performance linear regulator
specifically designed to deliver up to 2A output current with
very low input voltage and ultra low dropout voltage. With
dual-supply configuration, the uP7704 operates with a wide
input voltage VIN range from 1.2V to 5.5V and is ideal for
application s where VOUT is very close to VIN .

Supply Voltage for Control Circuit V

CNTL

Unlike other linear regulators that use a P-Channel
MOSFET as the pass transistor, the uP7704 uses an N­Channel as the pass transistor. N-Channel MOSFET
provides lower on-resistance a nd better sta bility meeting
stringent requirements of current generation
microprocessors and other sensitive electronic devices.
The drain of N-Cha nnel MOSFET is connected to VIN a nd
the source is connected to VOUT. This requires that the
supply voltage V

for control circuit is at lea st 1.5V higher

CNTL

than the output voltage to provide enough overdrive ca pability
for the pa ss transistor thus to a chieve low dropout a nd fa st
transient response. It is highly recommended to bias the
device with 5V voltage source if available.

Use a minimum 1uF cera mic ca pacitor plus a 10Ω resistor
to locally bypass the control voltage.

Input/Output Ca p acitor Selection

The uP7704 has a fa st tra nsient respon se that allows it to
handle large load changes associated with high current
application s. Proper selection of the output ca pa citor a nd
its ESR value determines stable operation and opti mizes
performance. The typical application circuit shown in Figure
1 was te sted with a wide range of different ca pa citors. The
circuit was f ound to be unconditionally stable with ca pa citor
values from 10uF to 1000uF and ESR ranging from 0.5mΩ
to greater then 75mΩ.

5VCC

R4

10R

V

IN

C1

1uF

C2

4.7uF

EN

NC

CNTL

uP7704

GND

POK

VOUTVIN

FB

R3

10K

R2

12.5K

R1

10K

C4

option

V

OUT

C3

10uF

Figure 1. T ypical Application Circuit

Input capacitor: A minimum of 4.7uF ceramic capacitor
is recommended to be placed dire ctly next to the VIN pin.

This allows for the device being some dista nce from any
bulk ca pacita nce on the rail. Additionally , bulk ca pa cita nce
may be added closely to the input supply pin of the uP7704
to ensure that VIN does not sag, improving load transient
response.

Output cap a citor: A minimum bulk ca pa cita nce of 10uF,
along with a 0.1uF ceramic decoupling capacitor is
recommended. Increa sing the bulk ca pacita nce will improve
the overall transient re sponse. The use of multiple lower
value cera mic cap acitors in parallel to a chieve the desired
bulk capacitance will not cause stability issues. Although
designed for use with cera mic output ca pacitors, the uP7704
is extremely tolerant of output capacitor ESR values and
thus will also work comfortably with tantalum output
capacitors.

Thermal Consideration

The uP7704 integrates internal thermal limiting function to
protect the device from damage during fault conditions.
However, continuously kee ping the junction near the thermal
shutdown temperature may remain possibility to affect

device reliability. It is highly recommended to keep the

junction temperature below the recommended operation
condition 125OC for maximum relia bility .

Power dissipation in the device is calculated a s:
PD = (VIN - V

OUT

) x I

OUT

+ V

CNTL

x I

CNTL

It is adequate to neglect power loss with respective to
control circuit V

CNTL

x I

when considering thermal

CNTL

management in uP7704 Take the following moderate
operation condition a s an exa mple: VIN = 3.3V , V
I

= 1A, the power dissipation is:

OUT

= 1.5V ,

OUT

PD = (3.3V- 1.5V) x 1A = 1.8W
This power dissipation is conducted through the pa ckage

into the ambient environment, and, in the process, the
temperature of the die (TJ) rises above a mbient. Large power
dissipation may cause considerable temperature raise in
the regulator in large dropout application s. The geometry
of the pack age and of the printed circuit board (PCB) greatly
influences how quickly the heat is tran sferred to the PCB
and away from the chi p. The most commonly used thermal
metrics for IC packages are thermal resistance from the
chip junction to the ambient air surrounding the package
(θJA):

θ

= ( TJ -TA ) / P

JA

θ

specified in the Thermal Information section is mea sured

JA

D

in the natural convection at TA = 25OC on a high effective
thermal conductivity test board (4 Layers, 2S2P) of JEDEC
51-7 thermal measurement standard. The case point of

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

10

θ

A

is on the exposed pad for PSOP-8 package.

JC

Given power dissipation PD, ambient temperature and
thermal resistance θJA, the junction temperature is
calculated as :

uP7704

pplication I nformation

FB

VOUT

GNDPOK

NC

TJ = TA + ΔTJA = TA + PD x θ

JA

T o limit the junction temperature within its maxi mum rating,
the allowable maximum power dissipation is calculated
as:

P

= ( T

D(MAX)

where T

-TA ) /θ

J(MAX)

is the maximum operation junction

J(MAX)

JA

temperature 125OC, TA is the ambient te mperature and the

θ

is the junction to ambient thermal resistance. θJA of

JA

PSOP-8 packages is 75OC/W on JEDEC 51-7 (4 layers,
2S2P) thermal test board with minimum copper area. The
maximum power dissipation at TA = 25OC can be calculated
as:

P

= (125OC - 25OC) / 75OC/W = 1.33W

D(MAX)

The thermal resistance θJA highly depends on the PCB
design. Copper plane under the exposed pad is a n effective
heatsink and is useful f or improving thermal conductivity.
Figure 3 show the relationship between thermal resistance

θ

vs. copper area on a standard JEDEC 51-7 (4 layers,

JA

2S2P) thermal test board at TA = 25OC. A 50mm2 copper
plane reduces θJA from 75OC/W to 52OC/W and increa s es
maximum power dissipation from 1.33W to 1.9W .

6

7

8

GND

1

2

3

EN

VIN

uP7704

45

CNTL

Figure 4. Recommended PCB Layout.

Layout Consideration

1. Place a local bypass capacitor as closed as possible
to the VIN pin. Use short and wide traces to mini mize
para sitic resistance a nd inducta nce.

2. The exposed pad should be soldered on GND plane
with maximum area a nd with multiple via s to inner layer
of ground place f or improving thermal performa nce.

3. Connect voltage divider directly to the point where
regulation is required. Place voltage divider close to
the device.

100

90

C/W)

80

O

(

JA

70

60

50

Thermal Resistanc e θ

40

30

Copper Are a (mm2)

60 7050403020100

Figure 3. Thermal Resistance θJA vs. Copper Are a

Figure 4 illustrated the recommended PCB layout for best
thermal performance.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

11

PSOP-8 Packa ge

n

uP7704

Package Informa tio

0.70 RE F 1.27 REF

3.00 REF

7.00 REF

5.50 REF

1.50 R EF

2.20 REF

4.00 REF

Recommended Solder Pad Layout

0.20 BSC

0.40 - 0.90

0.18 - 0.25

5.80 - 6.20

1.27 BSC

1.45 - 1.60

1.75 MAX

4.80 - 5.00

3.00 BSC

3.80 - 4.00

3.81 BSC

2.20 BSC

0.32 - 0.52

0.05 - 0.25

Note

1.Package Outline U nit Description:
BSC: Basic. Re presents theoretical exa ct dimen sion or dimen sion target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension f or reference use only . This value is not a device specification.
TYP . Typical. Provided a s a general value. This value is not a device spe cification.

2.Dimensions in Millimeters.

3.Drawing not to scale.

4.These dimensions no not include mold fla sh or protrusion s. Mold fla sh or protrusions shell not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

12

WDFN3x3-10L Pa ckage

n

uP7704

Package Informa tio

2.90 - 3.10

2.90 - 3.10

0.00 - 0.050.20 REF

0.35 - 0.45

1.55 - 1.65

0.80 MAX

2.25 - 2.35

610

15

0.18 - 0.280.50 BSC

2.25 - 2.35

1.55 - 1.65

1.95 - 2.05

3.55 - 3.65

0.50 BSC

Recommended Solder Pitch and Dimensions

0.18 - 0.28

Note

1.Package Outline U nit Description:
BSC: Basic. Re presents theoretical exa ct di mension or dimen sion target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension f or reference use only . This value is not a device specification.
TYP . Typical. Provided a s a general value. This value is not a device spe cification.

2.Dimensions in Millimeters.

3.Drawing not to scale.

4.These dimensions no not include mold fla sh or protrusion s. Mold fla sh or protrusions shell not exceed 0.15mm.

uPI Semiconductor Corp., http://www.upi-semi.com
Rev. F00, File Name: uP7704-DS-F0001

13