As an interface between low-level logic and solenoids, dc (brush)
motors, or stepper motors, the UDN2998W dual full-bridge driver will
operate inductive loads up to 50 V with continuous output currents of
up to 2 A per bridge or peak (start-up) currents to 3 A. The control
inputs are compatible with TTL, DTL, and 5 V CMOS logic. Except
for a common supply voltage and thermal shutdown, the two drivers in
each package are completely independent.
For external PWM control, an Output Enable for each bridge
circuit is provided and the sink driver emitters are pinned out for
connection to external current-sensing resistors. The chopper drive
mode is characterized by low power dissipation levels and maximum
efficiency. A PHASE input to each bridge determines load-current
direction.
Data Sheet
29319.6B†
Dwg. No. W-106
ABSOLUTE MAXIMUM RATINGS
at T
≤ +150°C
J
Supply Voltage, VBB.......................... 50 V
Output Current, I
(peak) ........................................... ±3 A
Sink Driver Emitter Voltage, VE...... 1.5 V
Logic Input Voltage Range,
V
or V
PHASE
Package Power Dissipation,
PD....................................... See Graph
Operating Temperature Range,
TA.............................. -20°C to +85°C
Storage Temperature Range,
TS............................. -55°C to +150°C
NOTE: Output current rating may be limited
by chopping frequency, ambient temperature, air flow, or heat sinking. Under any set
of conditions, do not exceed the specified
current rating or a junction temperature of
+150°C.
(continuous) ..... ±2 A
OUT
....... -0.3 V to 15 V
ENABLE
Extensive circuit protection is provided on-chip. Both groundclamp and flyback diodes for each bridge are provided. A thermal
shutdown circuit disables the load drive if chip temperature rating
(package power dissipation) is exceeded. Internally-generated delays
provide crossover-current protection.
The UDN2998W is packaged in a 12-pin single in-line power-tab
package for high power capabilities. Driving either of the bridges at
the full 2 A dc rating requires the use of an external heat sink. The tab
is at ground potential and needs no insulation.
FEATURES
■±3 A Peak Output Current
■Output Voltage to 50 V
■Integral Output Suppression Diodes
■Output Current Sensing
■TTL/CMOS Compatible Inputs
■Internal Thermal Shutdown Circuitry
■Crossover-Current Protected
■Automotive Capable
Always order by complete part number:UDN2998W .
Page 2
2998
DUAL FULL-BRIDGE
MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
(ONE OF TWO DRIVERS)
BB
Dwg. No. W-107A
To maintain isolation between integrated circuit components and to
provide for normal transistor operation, the ground tab must be
connected to the most negative point in the external circuit.
NOTES: 1. Lead thickness is measured at seating plane or below.
2. Lead spacing tolerance is non-cumulative.
3. Exact body and lead configuration at vendor’s option within limits shown.
4. Lead gauge plane is 0.030” below seating plane.
5. Supplied in standard sticks/tubes of 15 devices.
Page 6
2998
DUAL FULL-BRIDGE
MOTOR DRIVER
Dimensions in Millimeters
(for reference only)
INDEX
AREA
1.65
0.89
0.51
1
32.00
31.49
19.69
19.45
0.76
0.51
12
6.22
5.71
3.56
9.27
2.54
±0.254
3.94
3.68
4.57
MAX
ø
14.48
13.71
7.36
MIN
0.59
0.45
1.40
1.14
3.43
2.54
2.03
1.77
Dwg. MP-007 mm
NOTES: 1. Lead thickness is measured at seating plane or below.
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be required
to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.