▪ 4.75 to 35 V driver supply voltage
▪ Output enable-disable (OE/R)
▪ 350 mA output source current
▪ Overcurrent protected
▪ Internal ground clamp diodes
▪ Output Breakdown Voltage 35 V minimum
▪ TTL, DTL, PMOS, or CMOS compatible inputs
▪ Internal Thermal Shutdown (TSD)
Package: 20-pin SOICW (suffix LW)
Not to scale
Description
Providing overcurrent protection for each of its eight
sourcing outputs, the UDN2987LW-6 driver is used as an
interface between standard low-level logic and relays, motors,
solenoids, LEDs, and incandescent lamps. This device includes
thermal shutdown and output transient protection/clamp diodes
for use with sustaining voltages to 35 V.
In this driver, each channel includes a latch to turn off that
channel if the maximum channel current is exceeded. All
channels are disabled if the thermal shutdown is activated. A
common FAULT output is used to indicate either chip thermal
shutdown or any overcurrent condition. All outputs are enabled
by pulling the common OE/R input high. When OE/R ¯ is low,
all outputs are inhibited and the eight latches are reset. The
OE/R ¯function can be especially important during power-up,
in preventing floating inputs from turning on the outputs.
Under normal operating conditions, each of eight outputs
will source in excess of 100 mA continuously at an ambient
temperature of 25°C and a supply of 35 V. The overcurrent
fault circuit will protect the device from short-circuits to ground
with supply voltages of up to 30 V.
T ypical Application
IN1
IN2
IN3
IN4
CPU
IN5
IN6
IN7
IN8
FAULT
OE/R
2987
¯
Continued on the next page…
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
GND
VS
1 to 8 Load
Components
4.75 to 35 V
29876-DS, Rev. 6
Page 2
UDN2987x-6
Description (continued)
DABIC-5 8-Channel Source Driver
with Overcurrent Protection
The inputs are compatible with 5 and 12 V logic systems: TTL,
Schottky TTL, DTL, PMOS, and CMOS. In all cases, the output is
switched ON by an active high input level. Compared to predecessor
devices, the UDN2987LW-6 has a significantly faster T
PHL
(200 ns
The UDN2987LW-6 is supplied in a 20-lead small-outline (SOIC-W)
plastic package. All packages are lead (Pb) free, with 100% mattetin leadframe plating.
typical) and a lower driver supply voltage rating (4.75 V), which
allows the use of 5 V logic.
Selection Guide
Part NumberPackingPackage
UDN2987LWTR-6-T1000 pieces/13-in. reel20-pin SOIC, wide body
9FAULT Fault output
10OE/ ¯R¯ Logic input for Output Enable and Reset
11VSSupply voltage
12GNDSupply ground
13OUT8Output 8 to load
14OUT7Output 7 to load
15OUT6Output 6 to load
16OUT5Output 5 to load
17OUT4Output 4 to load
18OUT3Output 3 to load
19OUT2Output 2 to load
20OUT1Output 1 to load
As with all power integrated circuits, the UDN2987LW-6
has a maximum allowable output current rating. The
500 mA rating does not imply that operation at that value
is permitted or even obtainable. The channel output current
trip point is specified as –370 mA, minimum; therefore,
attempted operation at current levels greater than –370 mA
may cause a fault indication and channel shutdown. The
device is tested at a maximum of –350 mA and that is the
recommended maximum output current per driver. It provides protection for current overloads or shorted loads up to
30 V.
All outputs are enabled by pulling the OE/R ¯ input high.
When OE/R ¯ is low or allowed to float (internal pull-down),
all outputs are inhibited and the latches are reset. Note that
the reset pulse duration (OE/R ¯ low) should be at least 1 μs.
This will ensure safe operation under attempted reset conditions with a shorted load. The latches are also reset during
power-up, regardless of the state of the OE/R ¯ input.
The load current causes a small voltage drop across the
internal low-value sense resistor. This voltage is com-
pared to the voltage drop across a reference resistor with
a constant current. The two resistors are matched to
eliminate errors due to manufacturing tolerances or temperature effects. Each channel includes a comparator and
its own latch. An overcurrent fault (V
SENSE
> V
REF
) will
set the affected latch and shut down only that channel.
All other channels will continue to operate normally. The
latch includes a 1 μs blanking delay, t
BLANK
, to prevent
unwanted triggering due to crossover currents generated
when switching inductive loads. For an abrupt short circuit,
the blanking and output switching times will allow a brief,
permissible current in excess of the trip current before the
output driver is turned off.
A common thermal shutdown disables all outputs if the
chip temperature exceeds 165°C. At thermal shutdown, all
latches are reset. The outputs are disabled until the chip
cools down to approximately 150°C (thermal hysteresis).
In the event of an overcurrent condition on any channel, or
chip thermal shutdown, the FAULT open-collector output is
pulled low (turned on).
For Reference Only
Dimensions in millimeters
(Reference JEDEC MS-013 AC)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
2.65 MAX
0.20 ±0.10
4° ±4
+0.07
0.27
–0.06
+0.44
0.84
–0.43
0.25
C
SEATING PLANE
GAUGE PLANE
Terminal #1 mark area
A
Reference pad layout (reference IPC SOIC127P1030X265-20M)
B
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its
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