Page 1
INTEGRATED CIRCUITS
DATA SH EET
UDA1340
Low-voltage low-power stereo
audio CODEC with DSP features
Preliminary specification
Supersedes data of 1997 May 20
File under Integrated Circuits, IC01
1997 Jul 09
Page 2
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
FEATURES
General
• Low power consumption
• 3.0 V power supply
• 256, 384 and 512f
• Small package size (SSOP28)
• ADC plus integrated high pass filter to cancel DC offset
• Overload detector for easy record level control
• Separate power control for ADC and DAC
• Integrated digital filter plus DAC
• No analog post filter required for DAC
• Easy application
• Functions controllable by microcontroller interface.
Multiple format input interface
2
S-bus, MSB-justified and LSB-justified format
• I
compatible
• 1fs input and output format data rate.
DAC digital sound processing
• Digital volume control
• Digital tone control, bass boost and treble
• dB-linear volume and tone control (low microcontroller
load)
• Digital de-emphasis for 32, 44.1 and 48 kHz f
• Soft mute.
system clock
s
s
UDA1340
GENERAL DESCRIPTION
The UDA1340 is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.
The UDA1340 supports the I
lengths of up to 20 bits, the MSB-justified data format with
word lengths of up to 20 bits and the LSB justified serial
data format with word lengths of 16, 18 and 20 bits.
The UDA1340 has special sound processing features in
playback mode, de-emphasis, volume, bass boost, treble,
and soft mute, which can be controlled via the
microcontroller interface.
2
S-bus data format with word
Advanced audio configuration
• Stereo single-ended input configuration
• Stereo line output (under microcontroller volume
control)
• Power-down click prevention circuitry
• High linearity, dynamic range, low distortion.
ORDERING INFORMATION
TYPE
NUMBER
UDA1340M SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
1997 Jul 09 2
NAME DESCRIPTION VERSION
PACKAGE
Page 3
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
UDA1340
CODEC with DSP features
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
DDA(ADC)
V
DDA(DAC)
V
DDO
V
DDD
I
DDA(ADC)
I
DDA(DAC)
I
DDO
I
DDD
I
PD(ADC)
I
PD(DAC)
T
amb
Analog-to-digital converter
V
I(rms)
(THD + N)/S total harmonic distortion plus
S/N signal-to-noise ratio V
α
cs
Digital-to-analog converter
V
o(rms)
(THD + N)/S total harmonic distortion plus
S/N signal-to-noise ratio code = 0; A weighted − 100 − dBA
α
cs
Power performance
P
ADDA
P
DA
P
AD
P
PD
ADC analog supply voltage 2.7 3.0 3.6 V
DAC analog supply voltage 2.7 3.0 3.6 V
operational amplifiers supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
ADC supply current − 4.5 − mA
DAC supply current − 3.5 − mA
operational amplifier supply current − 4 − mA
digital supply current − 6 − mA
digital ADC power-down supply current − 3 − mA
digital DAC power-down supply current − 3 − mA
operating ambient temperature −20 − +85
°
input voltage (RMS value) − 0.8 − V
at 0 dB −−85 −80 dB
noise-to-signal ratio
at −60 dB; A-weighted −−35 −30 dBA
= 0 V; A-weighted − 95 − dBA
i
channel separation − 100 − dB
output voltage (RMS value) − 0.8 − V
at 0 dB −−85 −80 dB
noise-to-signal ratio
at −60 dB; A-weighted −−35 − dBA
channel separation − 100 − dB
power consumption in record and
− 54 − mW
playback mode
power consumption in playback only
− 33 − mW
mode
power consumption in record only
− 27 − mW
mode
power consumption in power-down
− 6 − mW
mode
C
1997 Jul 09 3
Page 4
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
BLOCK DIAGRAM
handbook, full pagewidth
V
V
VINL
DDD
SSD
V
DDA(ADC)VSSA(ADC)
21
3 5
10
11
UDA1340
DC-CANCELLATION FILTER
V
ADCP
76 4
ADC
DECIMATION FILTER
ADC
V
ADCN
V
ref(A)
UDA1340
VINR
8
TEST1
21
TEST2
20
TEST3
DATAO
BCK
WS
DATAI
OVERFL
VOUTL
18
16
17
19
9
26
25 27 23 22
V
DDO
DIGITAL INTERFACE
INTERPOLATION FILTER
V
SSO
DSP FEATURES
NOISE SHAPER
DAC
V
DAC
DDA(DAC)VSSA(DAC)
L3-BUS
INTERFACE
V
ref(D)
13
L3MODE
14
L3CLOCK
15
L3DATA
12
SYSCLK
24
VOUTR
28
MGG839
Fig.1 Block diagram.
1997 Jul 09 4
Page 5
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
PINNING
SYMBOL PIN
V
SSA(ADC)
V
DDA(ADC)
1 ADC analog ground
2 ADC analog supply voltage
VINL 3 ADC input left
V
ref(A)
4 ADC reference voltage
VINR 5 ADC input right
V
ADCN
V
ADCP
6 ADC negative reference voltage
7 ADC positive reference voltage
TEST1 8 test control 1 (pull-down)
OVERFL 9 overload flag output
V
V
DDD
SSD
10 digital supply voltage
11 digital ground
SYSCLK 12 system clock 256, 384 or 512f
L3MODE 13 L3-bus mode input
L3CLOCK 14 L3-bus clock input
L3DATA 15 L3-bus data input
BCK 16 bit clock input
WS 17 word selection input
DATAO 18 data output
DATAI 19 data input
TEST3 20 test output
TEST2 21 test control 2 (pull-down)
V
SSA(DAC)
V
DDA(DAC)
22 DAC analog ground
23 DAC analog supply voltage
VOUTR 24 DAC output right
V
DDO
25 operational amplifier supply voltage
VOUTL 26 DAC output left
V
V
SSO
ref(D)
27 operational amplifier ground
28 DAC reference voltage
Description
UDA1340
handbook, halfpage
s
V
SSA(ADC)
V
DDA(ADC)
V
ref(A)
V
ADCN
V
ADCP
TEST1
OVERFL
V
V
SYSCLK
L3MODE
L3CLOCK
VINL
VINR
DDD
SSD
1
2
3
4
5
6
7
8
9
10
11
12
13
UDA1340
MGG838
Fig.2 Pin configuration.
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
V
ref(D)
V
SSO
VOUTL
V
DDO
VOUTR
V
DDA(DAC)
V
SSA(DAC)
TEST2
TEST3
DATAI
DATAO
WS
BCK
L3DATA
1997 Jul 09 5
Page 6
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
FUNCTIONAL DESCRIPTION
System clock
The UDA1340 accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable. The options are 256f
The system clock must be locked in frequency to the digital
interface input signals.
Multiple format input/output interface
The UDA1340 supports the following data input/output
formats:
2
S-bus with data word length of up to 20 bits
• I
• MSB justified serial format with data word length of up to
20 bits
• LSB justified serial format with data word lengths of
16, 18 or 20 bits.
The formats are illustrated in Fig.3. Left and right
data-channel words are time multiplexed.
Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1340 consists of two
third-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
Decimation filter (ADC)
The decimation from 128f
s
The first stage realizes 3rd-order characteristic. This
filter decreases the sample rate by 16. The second stage,
an FIR filter, consists of 3 half-band filters, each
decimating by a factor of 2.
Table 1 Decimation filter characteristics
ITEM CONDITION VALUE (dB)
Passband Ripple 0 − 0.45f
Stop band >0.55f
Dynamic range 0 − 0.45f
Gain overall −1.16
, 384fs and 512fs.
s
is performed in two stages.
sin x
----------- x
s
s
s
±0.05
−60
108
UDA1340
DC cancellation filter (ADC)
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 2.
Table 2 DC cancellation filter characteristics
ITEM CONDITION VALUE (dB)
Passband ripple none
Passband gain 0
Droop at 0.00045f
Attenuation at DC at 0.00000036f
Dynamic range 0 − 0.45f
s
s
s
Mute (ADC)
On recovery from power-down or switching on of the
system clock, the serial data output DATAO is held LOW
until valid data is available from the decimation filter. This
time depends on whether the DC cancellation filter is
selected:
DC cancel off: time = , t = 23.2 ms when
f
= 44.1 kHz
s
DC cancel on: time = , t = 279 ms when
f
= 44.1 kHz
s
1024
------------ f
s
12288
----------------
f
s
Overload detection (ADC)
In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512f
(11.6 ms at fs= 44.1 kHz). This time-out is reset for each
infringement.
0.031
>40
>110
cycles
s
1997 Jul 09 6
Page 7
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
Interpolation filter (DAC)
The digital filter interpolates from 1fsto 128fs by means of
a cascade of a recursive filter and an FIR filter.
Table 3 Interpolation filter characteristics
ITEM CONDITION VALUE (dB)
Passband ripple 0 − 0.45f
Stop band >0.55f
Dynamic range 0 − 0.45f
Gain DC −3.5
Noise shaper (DAC)
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.
s
s
s
±0.03
−50
108
UDA1340
The Filter Stream DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post-filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.
1997 Jul 09 7
Page 8
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
21516 1
RIGHT
MSB LSBB2 B15
RIGHT
UDA1340
215161718 1
LSB
2151617181920 1
B17
RIGHT
MSB B2 B3 B4
LSB
B19
MSB B2 B3 B4 B5 B6
MGG841
book, full pagewidth
321321
RIGHT
>=8 >=8
LEFT
S-BUS
2
INPUT FORMAT I
MSB B2 MSBLSB LSB MSBB2
32
RIGHT
1321
>=8 >=8
LEFT
2
MSB-JUSTIFIED FORMAT
1516 1
LEFT
MSB B2 MSBLSB LSB MSB B2B2
B15
215161718 1
LSB-JUSTIFIED FORMAT 16 BITS
MSB LSBB2
LEFT
LSB
B17
LSB-JUSTIFIED FORMAT 18 BITS
MSB B2 B3 B4
2151617181920 1
LEFT
LSB
B19
LSB-JUSTIFIED FORMAT 20 BITS
Fig.3 Serial interface formats.
MSB B2 B3 B4 B5 B6
WS
BCK
DATA
WS
BCK
DATA
WS
BCK
DATA
1997 Jul 09 8
WS
BCK
DATA
WS
BCK
DATA
Page 9
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
L3-Interface
The UDA1340 has a microcontroller input mode. In the
microcontroller mode, all the digital sound processing
features and the system controlling features can be
controlled by the microcontroller. The controllable features
are:
• System clock frequency
• Data input format
• Power control
• DC-filtering
• De-emphasis
• Volume
• Flat/min/max switch
• Bass boost
• Treble
• Mute.
The exchange of data and control information between the
microcontroller and the UDA1340 is accomplished through
a serial hardware interface comprising the following pins:
L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.
Information transfer via the microcontroller bus is
organized in accordance with the so called ‘L3’ format, in
which two different modes of operation can be
distinguished; address mode and data transfer mode
(see Figs 4 and 5).
The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode. Data
transfer for the UDA1340 can only be in one direction,
input to the UDA1340 to program its sound processing and
other functional features.
Address mode
The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.4. Data bits 0 to 1 indicate the type of
subsequent data transfer as given in Table 4.
UDA1340
Table 4 Selection of data transfer
BIT 1 BIT 0 TRANSFER
0 0 DATA (volume, bass boost, treble,
de-emphasis, mute, mode and power
control)
0 1 not used
1 0 STATUS (system clock frequency, data
input format and DC-filter)
1 1 not used
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1340 is 000101 (bit 7 to bit 2). In the event that the
UDA1340 receives a different address, it will deselect its
microcontroller interface logic.
Data transfer mode
The selection preformed in the address mode remains
active during subsequent data transfers, until the
UDA1340 receives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.4.
The maximum input clock and data rate is 64f
All transfers are byte wise, i.e. they are based on groups
of 8 bits. Data will be stored in the UDA1340 after the
eighth bit of a byte has been received. A multibyte transfer
is illustrated in Fig.6.
P
ROGRAMMING THE SOUND PROCESSING AND OTHER
FEATURES
The sound processing and other feature values are stored
in independent registers. The first selection of the registers
is achieved by the choice of data type that is transferred.
This is performed in the address mode, BIT 1 and BIT 0
(see Table 4). The second selection is performed by the
2 MSBs of the data byte (BIT 7 and BIT 6). The other bits
in the data byte (BIT 5 to BIT 0) is the value that is placed
in the selected registers.
When the data transfer of type ‘data’ is selected, the
features VOLUME, BASS BOOST, TREBLE,
DE-EMPHASIS, MUTE, MODE and POWER CONTROL
can be controlled. When the data transfer of type ‘status’
is selected, the features SYSTEM CLOCK FREQUENCY,
DATA INPUT FORMAT and DC-FILTER can be
controlled.
.
s
1997 Jul 09 9
Page 10
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
handbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
t
h;MA
t
BIT 0
s;MA
t
s;DAT
t
HC
UDA1340
t
BIT 7
t
h;MA
s;MA
MGD016
t
LC
T
cy
t
h;DAT
handbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
write
t
s;MT
t
halt
BIT 0
Fig.4 Timing address mode.
t
LC
t
s;DAT
T
cy
t
HC
t
h;DAT
t
BIT 7
t
h;MT
h;DAT
t
halt
MGD017
Fig.5 Timing for data transfer mode.
1997 Jul 09 10
Page 11
Philips Semiconductors Preliminary specification
h
Low-voltage low-power stereo audio
CODEC with DSP features
andbook, full pagewidth
L3MODE
L3CLOCK
L3DATA
address
t
halt
UDA1340
addressdata byte #1 data byte #2
MGD018
Fig.6 Multibyte transfer.
Table 5 Data transfer of type ‘status’; note 1
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED
0 X SC1 SC0 IF2 IF1 IF0 DC System Clock frequency (1 : 0)
data Input Format (2 : 0)
DC-filter
1XXXXXXXnot used
Note
1. X = don’t care.
Table 6 Data transfer of type ‘data’; note 1
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED
0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0)
0 1 BB3 BB2 BB1 BB0 TR1 TR0 Bass Boost (3 : 0)
Treble (1 : 0)
1 0 X DE1 DE0 MT M1 M0 DE-emphasis (1 : 0)
MuTe
Mode (1 : 0)
11XXXXPC1PC0Power Control (1 : 0)
Note
1. X = don’t care.
1997 Jul 09 11
Page 12
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
SYSTEM CLOCK FREQUENCY
A 2-bit value (SC1 and SC0) to select the used external
clock frequency (see Table 7).
Table 7 System clock frequency settings
SC1 SC0 FUNCTION
0 0 512f
0 1 384f
1 0 256f
1 1 not used
DATA INPUT FORMAT
A 3-bit value (IF2 to IF0) to select the used data format
(see Table 8).
Table 8 Data input format settings
IF2 IF1 IF0 FUNCTION
000 I
0 0 1 LSB justified, 16 bits
0 1 0 LSB justified, 18 bits
0 1 1 LSB justified, 20 bits
1 0 0 MSB justified
1 0 1 not used
1 1 0 not used
1 1 1 not used
2
S-bus
s
s
s
UDA1340
DC-FILTER
A 1-bit value to enable the digital DC-filter (see Table 9).
Table 9 DC-filtering
DC FUNCTION
0 no DC-filtering
1 DC-filtering
VOLUME CONTROL
A 6-bit value to program the left and right channel volume
attenuation (VC5 to VC0). The range is 0 dB to −∞ dB in
steps of 1 dB (see Table 10).
Table 10 Volume settings
VC5 VC4 VC3 VC2 VC1 VC0
000000 0
000001 0
000010 −1
000011 −2
:::::: :
111011 −58
111100 −59
111101 −60
111110 −∞
111111 −∞
VOLUME
(dB)
1997 Jul 09 12
Page 13
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
UDA1340
CODEC with DSP features
BASS BOOST
A 4-bit value to program the bass boost setting. The used set depends on the MODE bits.
Table 11 Bass boost settings
BB3 BB2 BB1 BB0
FLAT SET (dB) MIN. SET (dB) MAX. SET (dB)
0000 0 0 0
0001 0 2 2
0010 0 4 4
0011 0 6 6
0100 0 8 8
0101 0 10 10
0110 0 12 12
0111 0 14 14
1000 0 16 16
1001 0 18 18
1010 0 18 20
1011 0 18 22
1100 0 18 24
1101 0 18 24
1110 0 18 24
1111 0 18 24
BASS BOOST
TREBLE
A 2-bit value to program the treble setting. The used set depends on the MODE bits.
Table 12 Treble settings
TR1 TR0
FLAT SET (dB) MIN. SET (dB) MAX. SET (dB)
00 0 0 0
01 0 2 2
10 0 4 4
11 0 6 6
TREBLE
1997 Jul 09 13
Page 14
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
DE-EMPHASIS
A 2-bit value to enable the digital de-emphasis filter.
Table 13 De-emphasis settings
DE1 DE0 FUNCTION
0 0 no de-emphasis
0 1 de-emphasis, 32 kHz
1 0 de-emphasis, 44.1 kHz
1 1 de-emphasis, 48 kHz
MUTE
A 1-bit value to enable the digital mute.
Table 14 Mute
MT FUNCTION
0 no muting
1 muting
ODE
M
UDA1340
Table 15 The flat/min./max. switch
M1 M0 FUNCTION
0 0 flat
0 1 min.
1 0 min.
1 1 max.
OWER CONTROL
P
A 2-bit value to disable the ADC and/or DAC to reduce
power consumption.
Table 16 Power control settings
PC1 PC0
00offoff
0 1 off on
1 0 on off
1 1 on on
FUNCTION
ADC DAC
A 2-bit value to program the mode of the sound processing
filters of Bass Boost and Treble. There are three modes:
flat, min. and max.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground,
V
DDD=VDDA=VDDO
= 3 V; T
=25°C; unless otherwise specified.
amb
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
DDD
T
xtal(max)
T
stg
T
amb
V
es
supply voltage note 1 − 5.0 V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
operating ambient temperature −20 +85 °C
electrostatic handling note 2 −3000 +3000 V
note 3 −300 +300 V
Notes
1. All V
and VSS connections must be made to the same power supply.
DD
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pins 24, 26 and 28 which can
withstand ESD pulses of −1500 V to +1500 V.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air 90 K/W
1997 Jul 09 14
Page 15
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
UDA1340
CODEC with DSP features
DC CHARACTERISTICS
V
DDD=VDDA=VDDO
=3V; T
unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
DDA(ADC)
V
DDA(DAC)
V
DDO
V
DDD
I
DDA(ADC)
I
DDA(DAC)
I
DDO
I
DDD
ADC analog supply voltage 2.7 3.0 3.6 V
DAC analog supply voltage 2.7 3.0 3.6 V
operational amplifiers supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
ADC supply current operation mode − 4.5 − mA
DAC supply current operation mode − 3.5 − mA
operational amplifier supply current operation mode − 4 − mA
digital supply current operation mode − 6 − mA
Digital input pins
V
IH
V
IL
I
input leakage current −−10 µA
LI
C
i
HIGH level input voltage 0.8V
LOW level input voltage −0.5 − +0.2V
input capacitance −−10 pF
Digital output pins
V
OH
V
OL
HIGH level output voltage IOH= −2 mA 0.85V
LOW level output voltage IOL=2mA −−0.4 V
Analog-to-digital converter
V
R
R
C
ref
o(ref)
i
i
reference voltage with respect to V
V
reference output resistance pin 4 − 24 − kΩ
refA
input resistance 1 kHz − 9.8 − kΩ
input capacitance − 20 − pF
Digital-to-analog converter
V
ref
R
o(ref)
R
o
I
o(max)
R
L
C
L
reference voltage with respect to V
V
reference output resistance pin 28 − 28 − kΩ
refD
DAC output resistance − 0.13 3.0 Ω
maximum output current (THD + N)/S < 0.1%
load resistance 3 −− kΩ
load capacitance note 2 −−200 pF
=25°C; RL=5kΩ; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27);
amb
ADC power-down − 200 −µA
DAC power-down − 15 −µA
DAC power-down − 15 −µA
DAC power-down − 3 − mA
ADC power-down − 3 − mA
SSA
SSA
0.45V
0.45V
− V
DDD
−− V
DDD
0.5V
DDA
DDA
0.5V
DDA
DDA
DDD
0.55V
0.55V
+ 0.5 V
DDD
DDA
DDA
− 0.22 − mA
RL=5kΩ
V
V
V
Notes
1. All power supply pins (V
and VSS) must be connected to the same external power supply unit.
DD
2. When higher capacitive loads must be driven then a 100 Ω resistor must be connected in series with the DAC output
in order to prevent oscillations in the output operational amplifier.
1997 Jul 09 15
Page 16
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
UDA1340
CODEC with DSP features
AC CHARACTERISTICS (ANALOG)
V
DDD=VDDA=VDDO
(pins 1, 11, 22 and 27); unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Analog-to-digital converter
V
i(rms)
∆V
i
(THD + N)/S total harmonic distortion plus
S/N signal-to-noise ratio V
α
CS
PSRR power supply rejection ratio f
Digital-to-analog converter
V
o(rms)
∆V
o
(THD + N)/S total harmonic distortion plus
S/N signal-to-noise ratio code = 0; A-weighted − 100 − dBA
α
cs
PSRR power supply rejection ratio f
=3V; fi= 1 kHz; T
=25°C; RL=5kΩ all voltages referenced to ground
amb
input voltage (RMS value) − 0.8 − V
unbalance between channels − 0.1 − dB
at 0 dB −−85 −80 dB
noise-to-signal ratio
at −60 dB; A-weighted −−35 −30 dBA
= 0 V; A-weighted − 95 − dBA
i
channel separation − 100 − dB
ripple
V
ripple(p-p)
= 1 kHz;
=30mV
− 30 − dB
output voltage (RMS value) − 0.8 − V
unbalance between channels − 0.1 − dB
at 0 dB −−85 −80 dB
noise-to-signal ratio
at −60 dB; A-weighted −−35 − dBA
channel separation − 80 − dB
ripple
V
ripple(p-p)
= 1 kHz;
= 100 mV
− 50 − dB
1997 Jul 09 16
Page 17
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
UDA1340
CODEC with DSP features
AC CHARACTERISTICS (DIGITAL)
V
DDD=VDDA=VDDO
= 2.7 to 3.6 V; T
(pins 1, 11, 22 and 27); unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
T
cy
t
CWL
t
CWH
clock cycle f
f
LOW level pulse width f
sys
f
HIGH level pulse width f
sys
Serial input/output data timing; see Fig.7
t
BCK
t
BCK(H)
t
BCK(L)
t
r
t
f
t
s;DATI
t
h;DATI
t
d(DATO)(BCK)
t
d(DATO)(WS)
t
h;DATO
t
s;WS
t
h;WS
bit clock period
bit clock HIGH time 100 −−ns
bit clock LOW time 100 −−ns
rise time −−20 ns
fall time −−20 ns
data input set-up time 20 −−ns
data input hold time 0 −−ns
data output delay time (from BCK falling edge) −−80 ns
data output delay time (from WS edge) MSB-justified format −−80 ns
data output hold time 0 −−ns
word selection set-up time 20 −−ns
word selection hold time 10 −−ns
Address and data transfer mode timing; see Figs 4 and 5
T
cy
t
HC
t
LC
t
s;MA
t
h;MA
t
s;MT
t
h;MT
t
s;DAT
t
h;DAT
t
halt
L3CLK cycle time 500 −−ns
L3CLK HIGH period 250 −−ns
L3CLK LOW period 250 −−ns
L3MODE set-up time address mode 190 −−ns
L3MODE hold time address mode 190 −−ns
L3MODE set-up time data transfer mode 190 −−ns
L3MODE hold time data transfer mode 190 −−ns
L3DATA set-up time data transfer mode
L3DATA hold time data transfer mode
L3MODE halt time 190 −−ns
= −20 to +85 °C; RL=5kΩ; all voltages referenced to ground
amb
= 256f
f
f
f
f
sys
sys
sys
sys
sys
sys
sys
s
= 384f
s
= 512f
s
< 19.2 MHz 30 − 70 %T
≥ 19.2 MHz 40 − 60 %T
< 19.2 MHz 30 − 70 %T
≥ 19.2 MHz 40 − 60 %T
78 88 131 ns
52 59 87 ns
39 44 66 ns
1
⁄64fs−−ns
190 −−ns
and address mode
30 −−ns
and address mode
sys
sys
sys
sys
1997 Jul 09 17
Page 18
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
handbook, full pagewidth
WS
t
BCK
DATAO
DATAI
t
r
BCK(H)
t
f
t
T
BCK(L)
cy
t
h;WS
t
d(DATO)(WS)
t
s;WS
t
h;DATO
t
d(DATO)(BCK)
t
s;DATI
UDA1340
t
h;DATI
MGG840
Fig.7 Serial interface timing.
1997 Jul 09 18
Page 19
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
APPLICATION INFORMATION
3 V
ground
system
clock
L1
8LM32A07
L2
8LM32A07
C12
100 µF
(16 V)
R30
47 Ω
C11
100 µF
(16 V)
V
DDA
V
DDD
SYSCLK
DATAO
BCK
DATAI
WS
12
18
16
17
19
100 µF
(16 V)
100 nF
(63 V)
V
SSA(ADC)
1
C2
C21
26711
handbook, full pagewidth
V
DDA
R21
1 Ω
R24
C25
100 nF
V
DDA(ADC)VADCNVADCPVSSD
(63 V)
C9
100 µF
(16 V)
C29
100 nF
(63 V)
V
DDD
R28
1 Ω
V
DDD
10
UDA1340
V
ref(A)
4
C22
100 nF
(63 V)
C3
47 µF
(16 V)
overload
flag
left
input
right
input
OVERFL
9
C1
X4
C31
47 µF
1 nF
(16 V)
(63 V)
C6
X5
C32
47 µF
1 nF
(16 V)
(63 V)
R32
1 MΩ
R33
680 kΩ
L3CLOCK
VINL
VINR
L3MODE
L3DATA
3
5
13
14
15
27
V
SSO
100 nF
(63 V)
100 µF
(16 V)
C26
C7
UDA1340
25
V
R25
1 Ω
V
DDO
DDO
22
V
SSA(DAC)
C27
100 nF
(63 V)
C10
100 µF
(16 V)
V
23
V
DDA(DAC)
R29
1 Ω
DDA
26
24
28
VOUTL
VOUTR
V
ref(D)
C5
47 µF
(16 V)
C8
47 µF
(16 V)
C23
100 nF
(63 V)
R22
10 kΩ
R27
10 kΩ
R23
100 Ω
R26
100 Ω
C4
47 µF
(16 V)
X2
X3
MGK582
left
output
right
output
Fig.8 Application diagram.
1997 Jul 09 19
Page 20
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
PACKAGE OUTLINE
SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm
D
c
y
Z
28 15
UDA1340
SOT341-1
E
H
E
A
X
v M
A
pin 1 index
114
w M
b
e
DIMENSIONS (mm are the original dimensions)
mm
A
max.
2.0
0.21
0.05
1.80
1.65
2
A3b
0.25
0.38
0.25
p
cD
0.20
0.09
UNIT A1A
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
p
0 2.5 5 mm
scale
(1)E(1) (1)
10.4
10.0
eHELLpQZywv θ
5.4
0.65 1.25
5.2
7.9
7.6
Q
A
2
A
1
detail X
1.03
0.9
0.63
0.7
(A )
L
p
L
0.13 0.10.2
A
3
θ
1.1
0.7
o
8
o
0
OUTLINE
VERSION
SOT341-1 MO-150AH
IEC JEDEC EIAJ
REFERENCES
1997 Jul 09 20
EUROPEAN
PROJECTION
ISSUE DATE
93-09-08
95-02-04
Page 21
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
“IC Package Databook”
our
Reflow soldering
Reflow soldering techniques are suitable for all SSOP
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Wave soldering
Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
(order code 9398 652 90011).
UDA1340
If wave soldering cannot be avoided, the following
conditions must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
• The longitudinal axis of the package footprint must
be parallel to the solder flow and must incorporate
solder thieves at the downstream end.
Even with these conditions, only consider wave
soldering SSOP packages that have a body width of
4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Repairing soldered joints
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
1997 Jul 09 21
Page 22
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
UDA1340
CODEC with DSP features
DEFINITIONS
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1997 Jul 09 22
Page 23
Philips Semiconductors Preliminary specification
Low-voltage low-power stereo audio
CODEC with DSP features
UDA1340
NOTES
1997 Jul 09 23
Page 24
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© Philips Electronics N.V. 1997 SCA55
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
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Internet: http://www.semiconductors.philips.com
Printed in The Netherlands 547027/1200/02/pp24 Date of release: 1997 Jul 09 Document order number: 9397 750 02548
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