Datasheet UCN5818EPF, UCN5818AF Datasheet (Allegro)

BiMOS II 32-BIT SERIAL-INPUT, LATCHED

SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

UCN5818EPF

30

32

31

OUT

NC

6

5

4

7

29

8

9

10

11

12

13

14

15

16

17

19

LATCHES

20

18

19

17

18

NC

OUT

3

REGISTER

BLNK

21

BLANKING

SERIAL

DATA OUT

2

22

GROUND

LOAD

1

BB

V

CLK

23

CLOCK

SUPPLY

ABSOLUTE MAXIMUM RATINGS

at TA = 25°C

Logic Supply Voltage, VDD.................... 15 V

Driver Supply Voltage, VBB................... 60 V

Continuous Output Current,

I

......................... -40 mA to +15 mA

OUT

Input Voltage Range,

VIN....................... -0.3 V to VDD + 0.3 V

Package Power Dissipation, P

(UCN5818AF) ............................ 3.5 W*

(UCN5818EPF) ......................... 2.7 W†

Operating Temperature Range,

T

................................. -20°C to +85°C

A

Storage Temperature Range,

TS............................... -55°C to +150°C

* Derate at rate of 28 mW/°C above TA = +25°C † Derate at rate of 22 mW/°C above TA = +25°C

Caution: CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges.

LOGIC

SUPPLY

44

DD

V

ST

24

STROBE

SERIAL

DATA IN

43

25

16

OUT

D

1

OUT

42

REGISTER

OUT

26

15

OUT

2

OUT

41

2

LATCHES

8

27

14

OUT

3

OUT

40

28

NC

39

38

37

36

35

34

33

19

32

31

30

29

Dwg. PP-059-2

OUT

NC

5818-F

Designed primarily for use with vacuum-fluorescent displays, the UCN5818AF and UCN5818EPF smart power BiMOS II drivers combine CMOS shift registers, data latches, and control circuitry, with bipolar highspeed sourcing outputs and DMOS active pull-down circuitry. The highspeed shift register and data latches allow direct interfacing with microprocessor LSI-based systems. A CMOS serial data output enables cascade connec-

4

tions in applications requiring additional drive lines. Both devices feature 60 V and -40 mA output ratings, allowing them to be used in many other peripheral power driver applications.

These smart power drivers have been designed with BiMOS II logic for improved data entry rates. With a 5 V supply, it will operate to at least 3.3 MHz. At 12 V, higher speeds are possible. Use of these devices with TTL may require the use of appropriate pull-up resistors to ensure an input logic high. All devices can be operated over the ambient temperature range of -

13

20°C to +85°C. The UCN5818AF is supplied in a 40-pin plastic dual in-line package with 0.600" (15.24 mm) row spacing. A copper lead frame, reduced supply current requirement, and low output saturation voltage permits operation with minimum junction temperature rise. The ‘A’ package allows all 32 outputs to be operated at -25 mA continuously over the operating temperature range.

For high-density packaging applications, the UCN5818EPF is furnished in a 44-lead plastic chip carrier (quad pack) for surface mounting on solder lands with 0.050" (1.27 mm) centers. The PLCC allows -25 mA continuous operation of all outputs simultaneously at ambient temperatures to 60°C. Similar devices are available as the UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5812AF/EPF (20 bits).

FEATURES

■ 60 V Source Outputs

■ High-Speed Source Drivers

■ To 3.3 MHz Data Input Rate

■ Low-Output Saturation Voltages

■ Active DMOS Pull-Downs

Always order by complete part number, e.g., UCN5818EPF .

■ Low-Power CMOS Logic and Latches

■ Reduced Supply Current Requirements

■ Improved Replacements for SN75518N/FN

Data Sheet

26182.28C

5818-F

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

UCN5818AF

FUNCTIONAL BLOCK DIAGRAM

LOAD

SUPPLY

SERIAL

DATA OUT

OUT

BLANKING

GROUND

LOGIC

1

V

BB

2

338

32

4

31

5

30

6

29

7

28

8

27

9

26

10

25

LATCHES

REGISTER

11

24

12

23

13

22

14

21

15

20

16

19

17

18

17

19

BLNK

20

REGISTER

V

LATCHES

CLK

40

DD

SUPPLY

SERIAL

39

DATA IN

OUT

1

OUT

37

2

36

OUT

3

35

OUT

4

34

OUT

5

33

OUT

6

32

OUT

7

31

OUT

8

30

OUT

9

OUT

29

10

OUT

28

11

OUT

27

12

OUT

26

13

25

OUT

14

24

OUT

15

23

OUT

16

22

STROBE

ST

CLOCK

21

CLOCK

SERIAL

DATA IN

STROBE

BLANKING

GROUND

SERIAL-PARALLEL SHIFT REGISTER

LATCHES

OUT1OUT

OUT

2

3

TYPICAL INPUT CIRCUIT

V

DD

IN

OUT

V

LOGIC

DD

SUPPLY

SERIAL DATA OUT

MOS

BIPOLAR

V

BB

N

LOAD SUPPLY

Dwg. FP-013-1

Dwg. PP-029-4

3.0

2.5

SUFFIX 'A', R = 36°C/W

θJA

2.0

1.5

SUFFIX 'EP', R = 46°C/W

θJA

1.0

0.5

ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS

0

25

50 75 100 125 150

AMBIENT TEMPERATURE IN °C

Dwg. GP-025A

Dwg. EP-010-5

TYPICAL OUTPUT DRIVER

V

BB

OUT

N

Dwg. No. A-14,219

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

5818-F

32-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVERS

WITH ACTIVE-DMOS PULL-DOWNS

ELECTRICAL CHARACTERISTICS at TA = + 25°C, VBB = 60 V unless otherwise noted.

Limits @ VDD = 5 V Limits @ VDD = 12 V

Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units

V

Output Leakage Current I

Output Voltage V

Output Pull-Down Current I

Input Voltage V

Input Current I

Serial Data Output Voltage V

Maximum Clock Frequency f

Supply Current I

Blanking to Output Delay t

Output Fall Time t

Output Rise Time t

CEX

OUT(1)IOUT

V

OUT(0)IOUT

OUT(0)

IN(1)

V

IN(0)

IN(1)

I

IN(0)

OUT(1)IOUT

V

OUT(0)IOUT

clk

DD(1)

I

DD(0)

I

BB(1)

I

BB(0)

PHL

t

PLH

f

r

= 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA

OUT

= -25 mA 58 58.5 — 58 58.5 — V

= 1 mA — 2.0 3.0 ——— V

= 2 mA ——— —2.0 3.5 V

I

OUT

V

OUT

= 5 V to V

= 20 V to V

BB

2.0 3.5 — ——— mA

——— 8.0 13 — mA

3.5 — 5.3 10.5 — 12.3 V

-0.3 — +0.8 -0.3 — +0.8 V

VIN = V

DD

— 0.05 0.5 — 0.1 1.0 µA

VIN = 0.8 V — -0.05 -0.5 — -0.1 -1.0 µA

= -200 µA 4.5 4.7 — 11.7 11.8 — V

= 200 µA — 200 250 — 100 200 mV

3.3* —— ——— MHz

All Outputs High — 100 300 — 200 500 µA

All Outputs Low — 100 300 — 200 500 µA

Outputs High, No Load — 3.0 6.0 — 3.0 6.0 mA

Outputs Low — 10 100 — 10 100 µA

CL = 30 pF, 50% to 50% — 2000 ——1000 — ns

CL = 30 pF, 50% to 50% — 1000 ——850 — ns

CL = 30 pF, 90% to 10% — 1450 ——650 — ns

CL = 30 pF, 10% to 90% — 650 ——700 — ns

Negative current is defined as coming out of (sourcing) the specified device terminal. * Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.

www.allegromicro.com

5818-F

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

CLOCK

DATA IN

STROBE

A D

B

E F

C

Serial Data present at the input is transferred to the shift register on the logic “0” to logic “1” transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform.

BLANKING

G

OUT

N

Dwg. No. A-12,649A

TIMING REQUIREMENTS

(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)

A. Minimum Data Active Time Before Clock Pulse

(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns

B. Minimum Data Active Time After Clock Pulse

(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns

C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns

D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns

E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns

F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns

G. Typical Time Between Strobe Activation and

Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns

Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable with increased supply voltage; operation at high temperatures will reduce the specified maximum clock frequency.

Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry.

When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON, the information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.

TRUTH TABLE

Serial Shift Register Contents Serial Latch Contents Output Contents Data Clock Data Strobe Input Input I

HHR

LLR

XR

L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State

1I2I3

1R2R3

XXX...X X X L R1R2R3... R

P1P2P3... P

1R2

... I

... R

N-1IN

N-2RN-1

N-1RN

N-1PN

Output Input I1I2I3... I

R

N-1

R

N-1

R

N

P

N

HP1P2P3... P

X X X ... X X H L L L ... L L

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

N-1IN

N-1 RN

N-1 PN

Blanking I1I2I3... I

LP1P2P3... P

I

N-1

N-1 PN

N

0.580

0.485

5818-F

32-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVERS

WITH ACTIVE-DMOS PULL-DOWNS

UCN5818AF

Dimensions in Inches

(controlling dimensions)

40

21

0.015

0.008

0.600

BSC

0.700

MAX

0.250

MAX

14.73

12.32

6.35

MAX

0.015

MIN

12

0.070

0.030

0.022

0.014

40

12

1.77

0.77

4

3

2.095

1.980

Dimensions in Millimeters

(for reference only)

4

3

53.2

50.3

0.100

BSC

2.54

BSC

20

0.005

MIN

0.200

0.115

Dwg. MA-003-40 in

0.381

21

20

0.13

MIN

0.204

15.24

BSC

17.78

MAX

0.39

MIN

0.558

0.356

5.08

2.93

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Lead thickness is measured at seating plane or below.

4. Supplied in standard sticks/tubes of 9 devices.

www.allegromicro.com

Dwg. MA-003-40 mm

5818-F

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

UCN5818EPF

Dimensions in Inches

(controlling dimensions)

28

18

0.319

0.291

0.319

0.291

8.10

7.39

8.10

7.39

0.021

0.013

0.050

BSC

0.533

0.331

1.27

BSC

0.020

MIN

0.180

0.165

29

0.032

0.026

0.695

0.685

0.656

0.650

39

40

Dimensions in Millimeters

(for reference only)

28

29

0.812

0.661

17.65

17.40

16.662

16.510

39

0.656

0.650

144

0.695

0.685

INDEX AREA

2

INDEX AREA

17

7

6

Dwg. MA-005-44A in

18

17

7

144

17.65

17.40

2

0.51

MIN

4.57

4.20

40

16.662

16.510

NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.

2. Lead spacing tolerance is non-cumulative.

3. Supplied in standard sticks/tubes of 27 devices or add “TR” to part number for tape and reel.

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000

6

Dwg. MA-005-44A mm

5818-F

32-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVERS

WITH ACTIVE-DMOS PULL-DOWNS

www.allegromicro.com

The products described here are manufactured under one or more

U.S. patents or U.S. patents pending.

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.

Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.

The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.

5818-F

32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS

POWER

INTERFACE DRIVERS

Function Output Ratings* Part Number

SERIAL-INPUT LATCHED DRIVERS

8-Bit (saturated drivers) -120 mA 50 V‡ 5895 8-Bit 350 mA 50 V 5821 8-Bit 350 mA 80 V 5822 8-Bit 350 mA 50 V‡ 5841 8-Bit 350 mA 80 V‡ 5842 8-Bit (constant-current LED driver) 75 mA 17 V 6275 8-Bit (DMOS drivers) 250 mA 50 V 6595 8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595 8-Bit (DMOS drivers) 100 mA 50 V 6B595

10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10

12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811

16-Bit (constant-current LED driver) 75 mA 17 V 6276

20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812

32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818 32-Bit 100 mA 30 V 5833 32-Bit (saturated drivers) 100 mA 40 V 5832

PARALLEL-INPUT LATCHED DRIVERS

4-Bit 350 mA 50 V‡ 5800

†

8-Bit -25 mA 60 V 5815 8-Bit 350 mA 50 V‡ 5801 8-Bit (DMOS drivers) 100 mA 50 V 6B273 8-Bit (DMOS drivers) 250 mA 50 V 6273

SPECIAL-PURPOSE DEVICES

Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804 Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259 Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259 Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259 Addressable 28-Line Decoder/Driver 450 mA 30 V 6817

* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.

Negative current is defined as coming out of (sourcing) the output.

† Complete part number includes additional characters to indicate operating temperature range and package style.

‡ Internal transient-suppression diodes included for inductive-load protection.

115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000