Page 1
26182.26B
5812-F
BiMOS II 20-BIT SERIAL-INPUT, LATCHED
SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
Data Sheet
UCN5812EPF
20
19
OUT
SERIAL
DATA OUT
LOAD
1
2
BB
V
REGISTER
CLK
14
15
CLOCK
GROUND
LOGIC
SUPPLY
28
V
ST
16
STROBE
DD
OUT
OUT
OUT
4
3
5
18
6
7
8
9
10
11
12
12
11
OUT
LATCHES
13
BLANKING
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Logic Supply Voltage, VDD..................... 15 V
Driver Supply Voltage, V
Continuous Output Current Range,
I
................................. -40 to +15 mA
OUT
Input Voltage Range,
VIN........................ -0.3 V to VDD + 0.3 V
Package Power Dissipation, P
(UCN5812AF) ........................... 3.12 W*
(UCN5812EPF) ........................ 1.92 W†
Operating Temperature Range,
TA.................................. -20°C to +85°C
Storage Temperature Range,
TS................................ -55°C to +150°C
BB
1
OUT
SERIAL
DATA IN
SUPPLY
26
27
25
24
23
LATCHES
REGISTER
17
10
OUT
22
21
20
19
18
9
OUT
Dwg. PP-059-1
.................... 60 V
D
OUT
OUT
The UCN5812AF/EPF combine a 20-bit CMOS shift register, data
latches, and control circuitry with high-voltage bipolar source drivers and
active DMOS pull-downs for reduced supply current requirements. Although
designed primarily for vacuum-fluorescent displays, the high-voltage, highcurrent outputs also allow them to be used in other peripheral power driver
applications. They are improved versions of the original UCN5812A/EP.
2
The CMOS shift register and latches allow direct interfacing with
microprocessor-based systems. With a 5 V supply, they will operate to at
least 3.3 MHz. At 12 V, higher speeds are possible. Especially useful for
inter-digit blanking, the BLANKING input disables the output source drives
and turns on the DMOS sink drivers. Use with TTL may require the use of
appropriate pull-up resistors to ensure an input logic high.
8
A CMOS serial data output enables cascade connections in applications
requiring additional drive lines. Similar devices are available as the
UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5818AF/EPF
(32 bits).
The output source drivers are high-voltage pnp-npn Darlingtons with a
minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The
DMOS active pull-downs are capable of sinking up to 15 mA.
The UCN5812AF is supplied in a 28-pin dual in-line plastic package with
0.600" (15.24 mm) row spacing. For surface mounting, the UCN5812EPF is
furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm)
centers. Copper lead-frames, reduced supply current requirements and lower
output saturation voltages, allow continuous operation, with all outputs
sourcing 25 mA, of the UCN5812AF over the operating temperature range,
and the UCN5812EPF up to +75°C. All devices are also available for operation between -40°C and +85°C. To order, change the prefix from ‘UCN’ to
‘UCQ’.
* Derate at rate of 25 mW/°C above TA = +25°C
† Derate at rate of 15 mW/°C above TA = +25°C
Caution: Allegro CMOS devices have input static
protection but are susceptible to damage when
exposed to extremely high static electrical
charges.
Note that the UCN5812AF (dual in-line package)
and UCN5812EPF (PLCC package) are electrically identical and share a common terminal
number assignment.
FEATURES
■ High-Speed Source Drivers
■ 60 V Source Outputs
■ To 3.3 MHz Data Input Rate
■ Low Output-Saturation Voltages
■ Low-Power CMOS Logic and Latches
Always order by complete part number, e.g., UCN5812AF .
■ Active DMOS Pull-Downs
■ Reduced Supply Current
Requirements
■ Improved Replacement
for TL5812
Page 2
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5812AF
FUNCTIONAL BLOCK DIAGRAM
LOAD
SUPPLY
SERIAL
DATA OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BLANKING
GROUND
1
V
BB
2
326
20
4
19
5
18
6
17
7
16
BLNK
LATCHES
REGISTER
8
15
9
14
10
13
11
12
12
11
13
14 27
LATCHES
REGISTER
V
ST
CLK
DD
28
27
25
24
23
22
21
20
19
18
17
28
16
15
Dwg. PP-029-7
SUPPLY
SERIAL
DATA IN
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
OUT
9
OUT
10
STROBE
CLOCK
CLOCK
SERIAL
DATA IN
STROBE
BLANKING
LOGIC
GROUND
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
OUT1OUT
OUT
2
3
OUT
V
MOS
BIPOLAR
V
N
LOGIC
DD
SUPPLY
SERIAL
DATA OUT
LOAD
BB
SUPPLY
Dwg. FP-013-1
TYPICAL INPUT CIRCUIT
V
DD
IN
Dwg. EP-010-5
TYPICAL OUTPUT DRIVER
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1988, 2000 Allegro MicroSystems, Inc.
V
BB
OUT
N
Dwg. No. A-14,219
Page 3
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
ELECTRICAL CHARACTERISTICS at TA = +25°C, VBB = 60 V (unless otherwise noted).
Limits @ VDD = 5 V Limits @ VDD = 12 V
Characteristic Symbol Test Conditions Mln. Typ. Max. Min. Typ. Max. Units
Output Leakage Current I
Output Voltage V
Output Pull-Down Current I
Input Voltage V
Input Current I
Serial Data V
Maximum Clock Frequency f
Supply Current I
Blanking to Output Delay t
Output Fall Time t
Output Rise Time t
CEX
OUT(1)
V
OUT(0)
OUT(0)
IN(1)
V
IN(0)
IN(1)
I
IN(0)
OUT(1)
V
OUT(0)
clk
DD(1)
I
DD(0)
I
BB(1)
I
BB(0)
PHL
t
PLH
f
r
V
= 0 V, TA = +70°C — -5.0 -15 — -5.0 -15 µA
OUT
I
= -25 mA, VBB = 60 V 58 58.5 — 58 58.5 — V
OUT
I
= 1 mA — 2.0 3.0 ——— V
OUT
I
= 2 mA ——— —2.0 3.5 V
OUT
V
= 5 V to V
OUT
V
= 20 V to V
OUT
BB
BB
2.0 3.5 — ——— mA
——— 8.0 13 — mA
3.5 — 5.3 10.5 — 12.3 V
-0.3 — +0.8 -0.3 — +0.8 V
VIN = V
DD
— 0.05 0.5 — 0.1 1.0 µA
VIN = 0.8 V — -0.05 -0.5 — -0.1 -1.0 µA
I
= -200 µA 4.5 4.7 — 11.7 11.8 — V
OUT
I
= 200 µA — 200 250 — 100 200 mV
OUT
3.3* —— ——— MHz
All Outputs High — 100 300 — 200 500 µA
All Outputs Low — 100 300 — 200 500 µA
Outputs High, No Load — 1.5 4.0 — 1.5 4.0 mA
Outputs Low — 10 100 — 10 100 µA
CL = 30 pF, 50% to 50% — 2000 ——1000 — ns
CL = 30 pF, 50% to 50% — 1000 ——850 — ns
CL = 30 pF, 90% to 10% — 1450 ——650 — ns
CL = 30 pF, 10% to 90% — 650 ——700 — ns
Negative current is defined as coming out of (sourcing) the specified device pin.
* Operation at a clock frequency greater than the specified minimum value is possible but not warranteed.
www.allegromicro.com
Page 4
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
CLOCK
DATA IN
STROBE
BLANKING
OUT
N
(TA = +25°C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
B. Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ns
C. Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
D. Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 ns
E. Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . 300 ns
F. Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ns
G. Typical Time Between Strobe Activation and
Output Transistion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 ns
Timing is representative of a 3.3 MHz clock. Higher speeds may be attainable
with increased supply voltage; operation at high temperatures will reduce the
specified maximum clock frequency.
A D
B
E F
C
G
TIMING REQUIREMENTS
Dwg. No. 12,649A
Serial Data present at the input is transferred
to the shift register on the logic “0” to logic “1”
transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data
information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input
waveform.
Information present at any register is transferred to the respective latch when the STROBE
is high (serial-to-parallel conversion). The latches
will continue to accept
new data as long as the STROBE is held high.
Applications where the latches are bypassed
(STROBE tied high) will require that the
BLANKING input be high during serial data
entry.
When the BLANKING input is high, the
output source drivers are disabled (OFF); the
DMOS sink drivers are ON, the information
stored in the latches is not affected by the
BLANKING input. With the BLANKING input
low, the outputs are controlled by the state of
their respective latches.
TRUTH TABLE
Serial Shift Register Contents Serial Latch Contents Output Contents
Data Clock Data Strobe
Input Input I
HHR
LLR
XR
L = Low Logic Level H = High Logic Level X = Irrelevant P = Present State R = Previous State
1I2I3
1R2R3
XXX… XX X L R1R2R3… R
P1P2P3… P
1R2
1R2
…I
N-1IN
… R
N-2RN-1RN-1
… R
N-2RN-1RN-1
… R
N-1RN
N-1 PN
Output Input I1I2I3…I
R
N
P
N
HP1P2P3… P
XXX… XX H LLL… LL
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
N-1IN
N-1 RN
N-1 PN
Blanking I1I2I3…I
LP1P2P3… PN1P
N-1IN
N
Page 5
0.580
0.485
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5812AF
Dimensions in Inches
(controlling dimensions)
0.015
28
15
0.008
0.600
BSC
0.700
MAX
0.250
MAX
14.73
12.32
6.35
MAX
0.015
MIN
12
0.070
0.030
0.022
0.014
28
12
1.77
0.77
4
3
1.565
1.380
0.100
BSC
14
0.005
MIN
0.200
0.115
Dwg. MA-003-28 in
Dimensions in Millimeters
(for reference only)
0.381
15
4
3
39.7
35.1
2.54
BSC
14
0.13
MIN
0.204
15.24
BSC
17.78
MAX
0.39
MIN
0.558
0.356
5.08
2.93
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
4. Supplied in standard sticks/tubes of 12 devices.
www.allegromicro.com
Dwg. MA-003-28 mm
Page 6
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
UCN5812EPF
Dimensions in Inches
(controlling dimensions)
18 12
0.219
0.191
0.219
0.191
0.013
0.021
0.050
BSC
0.331
0.533
0.020
MIN
0.165
0.180
19
0.026
0.032
0.456
0.450
0.495
0.485
25
26
Dimensions in Millimeters
(for reference only)
18 12
19
0.495
0.485
128
0.456
0.450
11
INDEX AREA
5
4
Dwg. MA-005-28A in
11
5.56
4.85
5.56
4.85
1.27
BSC
0.51
MIN
4.57
4.20
12.57
12.32
11.58
11.43
0.812
0.661
25
26
12.57
12.32
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Supplied in standard sticks/tubes of 38 devices or add “TR” to part number for tape and reel.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
128
11.582
11.430
INDEX AREA
5
4
Dwg. MA-005-28A mm
Page 7
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
www.allegromicro.com
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
Page 8
5812-F
20-BIT SERIAL-INPUT,
LATCHED SOURCE DRIVERS
WITH ACTIVE-DMOS PULL-DOWNS
POWER
INTERFACE DRIVERS
Function Output Ratings* Part Number
SERIAL-INPUT LATCHED DRIVERS
8-Bit (saturated drivers) -120 mA 50 V‡ 5895
8-Bit 350 mA 50 V 5821
8-Bit 350 mA 80 V 5822
8-Bit 350 mA 50 V‡ 5841
8-Bit 350 mA 80 V‡ 5842
8-Bit (constant-current LED driver) 75 mA 17 V 6275
8-Bit (DMOS drivers) 250 mA 50 V 6595
8-Bit (DMOS drivers) 350 mA 50 V‡ 6A595
8-Bit (DMOS drivers) 100 mA 50 V 6B595
10-Bit (active pull-downs) -25 mA 60 V 5810-F and 6809/10
12-Bit (active pull-downs) -25 mA 60 V 5811 and 6811
16-Bit (constant-current LED driver) 75 mA 17 V 6276
20-Bit (active pull-downs) -25 mA 60 V 5812-F and 6812
32-Bit (active pull-downs) -25 mA 60 V 5818-F and 6818
32-Bit 100 mA 30 V 5833
32-Bit (saturated drivers) 100 mA 40 V 5832
PARALLEL-INPUT LATCHED DRIVERS
4-Bit 350 mA 50 V‡ 5800
†
8-Bit -25 mA 60 V 5815
8-Bit 350 mA 50 V‡ 5801
8-Bit (DMOS drivers) 100 mA 50 V 6B273
8-Bit (DMOS drivers) 250 mA 50 V 6273
SPECIAL-PURPOSE DEVICES
Unipolar Stepper Motor Translator/Driver 1.25 A 50 V‡ 5804
Addressable 8-Bit Decoder/DMOS Driver 250 mA 50 V 6259
Addressable 8-Bit Decoder/DMOS Driver 350 mA 50 V‡ 6A259
Addressable 8-Bit Decoder/DMOS Driver 100 mA 50 V 6B259
Addressable 28-Line Decoder/Driver 450 mA 30 V 6817
* Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits.
Negative current is defined as coming out of (sourcing) the output.
† Complete part number includes additional characters to indicate operating temperature range and package style.
‡ Internal transient-suppression diodes included for inductive-load protection.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
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