Datasheet UCC1917, UCC2917, UCC3917 Datasheet (UNITRODE)

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Positive Floating Hot Swap Power Manager

FEATURES

Manages Hot Swap of 15V and

•

Above

Precision Fault Threshold

•

Programmable Average Power

•

Limiting

Programmable Linear Current

•

Control

Programmable Overcurrent Limit

•

Programmable Fault Time

•

Internal Charge Pump to Control

•

External NMOS Device

Fault Output and Catastrophic

•

Fault Indication

• Fault Mode Programmable to

Latch or Retry

• Shutdown Control

• Undervoltage Lockout

BLOCK DIAGRAM

V

DD

40µA

SHTDWN

12

DESCRIPTION

The UCC3917 family of positive floating hot swap managers provides complete
power management, hot swap, and fault handling capability. The voltage limita
tion of the application is only restricted by the external component voltage limi
tations. The IC provides its own supply voltage via a charge pump off of VOUT.
The onboard 10V shunt regulator protects the IC from excess voltage. The IC
also has catastrophic fault indication to alert the user that the ability to shut off
the output NMOS has been bypassed. All control and housekeeping functions
are integrated and externally programmable. These include the fault current
level, maximum output sourcing current, maximum fault time, soft start time,
and average NMOS power limiting.

The fault level across the current sense amplifier is fixed at 50mV to minimize
total drop out. Once 50mV is exceeded across the current sense resistor, the
fault timer will start. The maximum allowable sourcing current is programmed
with a voltage divider from the VREF/CATFLT
on the MAXI pin. The current level at which the output appears as a current
source is equal to V
trolled current startup can be programmed with a capacitor on MAXI.

When the output current is below the fault level, the output device is switched
on with full gate drive. When the output current exceeds the fault level, but is
less than maximum allowable sourcing level programmed by MAXI, the output
remains switched on, and the fault timer starts charging CT. Once CT charges
to 2.5V, the output device is turned off and attempts either a retry sometime
later or waits for the state on the LATCH
the output current reaches the maximum sourcing current level, the output de­vice appears as a current source.

13 16

UVLO
>10V=ENABLE
< 6V=DISABLE

MAXI divided by the current sense resistor. If desired, a con

LATCHVDD

V

DD

VOUT

application

INFO

available

UCC1917
UCC2917
UCC3917

pin to generate a fixed voltage

pin to change if in latch mode. When

1

PLIM

5V

VDD

40µA

DISABLE

3

OUTPUT

-

-

-

VOUT

FLTOUT

C1P

C1N

C2P

C2N

11

8

7

6

5

SLUS203A - AUGUST 1999

5V

REFERENCE

LOGIC

SUPPLY

4V

9 15 14

VSS VREF/CATFLT MAXI

ON-TIME

DELAY

VOUT

OVER

CURRENT

COMPARATOR

OUTPUT

LOW

200mV

50mV

+

+

10

2

4

SENSE

VOUT

CT

UDG-99055

ABSOLUTE MAXIMUM RATINGS

IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

SHTDWN
LATCH

VREF Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –500µA

PLIM Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA

MAXI Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . VDD + 0.3V

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C

Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . +300°C

Currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Databook for thermal
limitations and considerations of package.

Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –500µA

Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –500µA

UCC1917
UCC2917
UCC3917

CONNECTION DIAGRAM

DIL-16, SOIC-16 (Top View)
J or N Package, D Package

ELECTRICAL CHARACTERISTICS:

UCC2917 and –55°C to 125°C for the UCC1917, C

Unless otherwise specified, TA= 0°C to 70°C for the UCC3917, –40°C to 85° for the

= 4.7nF. TA=TJ. All voltages are with respect to VOUT. Current is positive

T

into and negative out of the specified terminal.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VDD Section

I

DD From VOUT (Note 1) 3.0 5 11 mA

UVLO Turn On Threshold 7.9 8.8 9.7 V

UVLO Off Voltage 5.5 6.5 7.5 V

VSS Regulator Voltage –6 –5 –4 V

Fault Timing Section

Overcurrent Threshold T

A = 25°C 47.5 50 53 mV

Over Operating Temperature 46 50 54 mV

Overcurrent Input Bias 50 500 nA

CT Charge Current V

CT = 1V –78 –50 –28 µA

CT Catastrophic Fault Threshold 3.4 4.5 V

CT Fault Threshold 2.25 2.5 2.75 V

CT Reset Threshold 0.32 0.5 0.62 V

Output Duty Cycle Fault Condition 1.7 2.7 3.7 %

Output Section

Output High Voltage I

Output Low Voltage I

OUT = 0 6 8 10 V

OUT = –500µA 579V

I

OUT = 0 0 0.05 V

OUT = 500µA 0.1 0.5 V

I

OUT = 1mA 0.5 0.9 V

I

Linear Current Section

Sense Control Votlage MAXI = 100mV 85 100 115 mV

MAXI = 400mV 370 400 430 mV

Input Bias MAXI = 200mV 50 500 nA

SHUTDOWN Section

Shutdown Threshold 2.0 2.4 2.8 V

Input Current SHTDWN

= 0V 24 40 60 µA

Shutdown Delay 100 500 ns

2

UCC1917
UCC2917
UCC3917

ELECTRICAL CHARACTERISTICS:

the UCC2917 and –55°C to 125°C for the UCC1917, C
positive into and negative out of the specified terminal.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

LATCH Section

Latch Threshold 1.7 2 2.3 V
Input Current LATCH = 0V 24 40 60 µA

Fault Out Section

Fault Output High 6 8 10 V

Fault Output Low 0.01 0.05 V

Power Limiting Section

SENSE Regulator Voltage I

V

Duty Cycle Control I

VREF/CATFLT Section

V

REF Regulator Voltage 4.5 5 5.5 V

Fault Output Low I

Output Sink Current V

Overload Comparator Threshold Relative to MAXI 110 200 290 mV

Note 1: Set by user with RSS.

Unless otherwise specified, TA= 0°C to 70°C for the UCC3917, –40°C to 85° for

= 4.7nF. TA=TJ. All voltages are with respect to VOUT. Current is

T

= 64µA 4.5 5 5.5 V

PLIMIT

= 64µA 0.6 1.2 1.7 %

PLIMIT

= 1mA 0.045 0.1 0.2 %

I

PLIMIT

VREF/CATFLT

=

CT

= 5mA 0.22 0.50 V

5V, V

VREF/CATFLT

= 5V 15 40 70 mA

PIN DESCRIPTIONS

C1N: Negative side of the upper charge pump capacitor.

C1P: Positive side of the upper charge pump capacitor.

C2N: Negative side of the lower charge pump capacitor.

C2P: Positive side of lower charge pump capacitor.

CT: A capacitor is connected to this pin to set the fault

time. The fault time must be more than the time to
charge the external load capacitance (see Application In
formation).

FLTOUT

: This pin provides fault output indication. Inter

face to this pin is usually performed through level shift
transistors. Under a non-fault condition, FLTOUT

will pull
to a high state. When a fault is detected by the fault timer
or the under voltage lockout, this pin will drive to a low
state, indicating the output NMOS is in the off state.

LATCH

: Pulling this pin low causes a fault to latch until

this pin is brought high or a power on reset is attempted.
However, pulling this pin high before the reset time is
reached will not clear the fault until the reset time is
reached. Keeping LATCH

high will result in normal oper
ation of the fault timer. Users should note there will be an
RC delay dependent upon the external capacitor at this
pin.

MAXI: This pin programs the maximum allowable sour
cing current. Since VREF/CATFLT

is a regulated volt
age, a voltage divider can be derived to generate the
program level for MAXI. The current level at which the
output appears as a current source is equal to the volt

age on MAXI divided by the current sense resistor. If de­sired, a controlled current start up can be programmed
with a capacitor on MAXI (to VOUT), and a programmed
start delay can be achieved by driving the shutdown with
an open collector/drain device into an RC network.

OUTPUT: Gate drive to the NMOS pass element.

PLIM: This feature ensures that the average external

-

NMOS power dissipation is controlled. A resistor is con
nected from this pin to the drain of the external NMOS
pass element. When the voltage across the NMOS ex

­ceeds 5V, current will flow into PLIM which adds to the

fault timer charge current, reducing the duty cycle from
the 3% level.

SENSE: Input voltage from the current sense resistor.
When there is greater than 50mV across this pin with re
spect to VOUT, a fault is sensed, and CT starts to
charge.

SHTDWN

: This pin provides shutdown control. Interface

to this pin is usually performed through level shift transis

-

tors. When shutdown is driven low, the output disables
the NMOS pass device.

VDD: Power to the I.C. Is supplied by an external current
limiting resistor on initial power-up or if the load is

-

shorted. As the load voltages rises (VOUT), a small

-

amount of power is drawn from VOUT by an internal
charge pump. The charge pump’s input voltage is regu
lated by an on-chip 5V zener. Power to VDD is supplied

-

-

-

-

-

-

3

PIN DESCRIPTIONS (cont.)

by the charge pump under normal operation (i.e., exter
nal FET is on).

VOUT: Ground reference for the IC.

VREF/CATFLT

erence for the programming of MAXI. Secondarily, it pro
vides catastrophic fault indication. In a catastrophic fault,
when the IC unsuccessfully attempts to shutdown the

: This pin primarily provides an output ref

UCC1917
UCC2917
UCC3917

NMOS pass device, this pin pulls to a low state when C

­charges about the catastrophic fault thershold. A
possible application for this pin is to trigger the shutdown
of an auxilliaty FET in series with the main FET for

-

redundency.

­VSS: Negative reference out of the chip. Normally cur

rent fed via a resistor to ground.

T

-

Figure 1. Fault timing circuitry for the UCC3917, including power limit and overload.

APPLICATION INFORMATION

Fault Timing

Fig. 1 shows the detailed circuitry for the fault timing func
tion of the UCC3917. For simplicity, we first consider a
typical fault mode where the overload comparator and the
current source I3 do not come into play. A typical fault oc
curs once the voltage across the current sense resistor,

S, exceeds 50mV. This causes the over current com

R
parator to trip and the timing capacitor to charge with cur
rent source I1 plus the current from the power limiting
amplifier, or PLIM amplifier. The PLIM amplifier is de
signed to only source current into the CT pin once the
voltage across the output FET exceeds 5V. The current

PL is related to the voltage across the FET with the fol

I
lowing expression:

(V –VOUT)–5V

I=

PL

IN

R

PL

Note that under normal fault conditions where the output
current is just above the fault level, VOUT ≅ V

­and the C

charging current is just I1.

T

During a fault, CT will charge at a rate determined by

-

the internal charging current and the external timing ca
pacitor, CT. Once CT charges to 2.5V, the fault com

-

parator switches and sets the fault latch. Setting the

-

fault latch causes both the output to switch off and the
charging switch to open. CT must now discharge with

-

current source I2 until 0.5V is reached. Once the voltage
at CT reaches 0.5V, the fault latch resets (assuming
LATCH

-

until the LATCH

is high, otherwise the fault latch will not reset

pin is brought high or a power-on reset
occurs) which re-enables the output and allows the fault
circuitry to regain control of the charging switch. If a fault
is still present, the overcurrent comparator will close the
charging switch causing the cycle to repeat. Under a
constant fault the duty cycle is given by:

4

UDG-96265-1

IN,IPL

=0,

-

-

APPLICATION INFORMATION (cont.)

15

I

Duty Cycle =

where I

is 0µA under normal operations (see Fig. 2).

PL

2

IIAIA

1

PL PL

However, under large transients, average power dissipa
tion can be limited using the PLIM pin. A proof follows,
average dissipation in the pass element is given by:

I

OUT

I

MAX

I

FAULT

. µ

≅

50+

+

µ

-

P =(V – VOUT)•I •Duty Cycle

FET AVG IN MAX

µ

=(V – VOUT)•I •

IN MAX

Where (V

IN – VOUT) >> 5V,

V–VOUT

PL

IN

≅

R

I

PL

1.5 A

I+50A

PL

µ

UCC1917
UCC2917
UCC3917

I

O(nom)

V

CT

2.5V

0.5V

0V

V

OUT

V

IN

0V

t

t1t

0

t

2

3

t

4

t0: Safe condition - output current is nominal, output
voltage is at the positive rail, V

.

IN

t1: Fault control reached - output current rises above
the programmed fault value, CT begins to charge with ≅
50µA.

t2: Maximum current reached - output current reaches
the programmed maximum level and becomes a con
stant current with value I

MAX

.

t3: Fault occurs - CT has charged to 2.5V, fault output
goes low, the FET turns off allowing no output current to
flow, VOUT discharges to ground.

t4: Retry - CT has discharged to 0.5V, but fault current
is still exceeded, CT begins charging again, FET is on,
VOUT rises to V

.

IN

OUTPUT
CURRENT

t

CTVOLTAGE
(WITH RESPECT TO V

t

OUTPUT VOLTAGE
(WITH RESPECT TO GND)

t

t

5

t6t7t

t9t

8

10

OUT

)

t5 = t3: Illustrates 3% duty cycle.

t6 = t4:

t7: Output short circuit - if VOUT is short circuited to

ground, CT charges at a higher rate depending upon
the values for V

and RPL.

IN

t8: Fault occurs - output is still short circuited, but the

­occurrence of a fault turns the FET off so no current is

conducted.

t9 = t4: Output short circuit released, still in fault
mode.

t10 = t0: Fault released, safe condition - return to nor
mal operation of the circuit breaker.

Note that t6 – t5 ≅ 36 • (t5 – t4).

UDG-99147

-

Figure 2. Nominal timing diagram.

5

APPLICATION INFORMATION (cont.)

and where IPL>> 50µA, the duty cycle can be approxi
mated as:

1.5 A • R

µ

PL

VVOUT

−

IN

Therefore the average power dissipation in the MOSFET
can be approximated by:

P=(V-VOUT)•I•

FET AVG IN MAX

Notice that since (V
dissipation is limited in the NMOS pass element (see Fig.

3). Also, a value for R
this approximation.

R=

PL

.

=I •1.5 A •R

MAX PL

P

FET AVG

I • I.5 A

MAX

µ

– VOUT) cancels, average power

IN

PL

µ

µ

1.5 A • R

V-VOUT

IN

PL

can be roughly determined from

UCC1917
UCC2917
UCC3917

-

IImVR

OVERLOAD MAX S

Once the overcurrent comparator trips the UCC3917 will
enter programmed fault mode (hiccup or latched). It
should be noted that on subsequent retries during Hic
cup mode or if a short should occur when the UCC3917
is actively limiting the current, the output current will not
exceed I
not respond during a fault the UCC3917 will set the
VREF/CATFLT

Selecting the Minimum Timing Capacitance

To ensure that the IC will startup correctly the designer
must ensure that the fault time programmed by CT ex
ceeds the startup time of the load. The startup time
(T

) is a function of several components; load resis

START

tance and load capacitance, soft start components R1,
R2 and C
mined by R

For a parallel capacitor-constant current load: (1)

=+200 /

. In the event that the external FET does

MAX

pin low to indicate a catastrophic failure.

, the power limit current contribution deter

SS

, and CIN.

PL

-

-

-

-

RPL = INF

IMAX = 4A

RPL = 10M

PAVG

RPL = 5M

RPL = 2M

RPL = 1M

RPL = 200k

RPL =500k

Figure 3. Plot of average power vs. FET voltage
for increasing values of R

PL

.

Overload Comparator

The overload comparator provides protection against a
shorted load during normal operation when the external
N-channel FET is fully enhanced. Once the FET is fully
enhanced the linear current amplifier essentially saturates
and the system is in effect operating open loop. Once the
FET is fully enhanced the linear current amplifier requires
a finite amount of time to respond to a shorted output
possibly destroying the external FET. The overload com
parator is provided to quickly shutdown the external
MOSFET in the case of a shorted output (if the FET is
fully enhanced). During an output short CT is charged by
I3 at ~ 1mA. The current threshold for the overload com
parator is a function of I

and a fixed offset and is de

MAX

fined as:

T

START

CVIN

=

II

•

LOAD

–

MAX LOAD

For a parallel R-C load :

T

––

=

START

RC n

••

LOAD LOAD



l 1






V

IN

IR

•

MAX LOAD







If the power limit function is not be used then CT(min)
can be easily found:

IT

•

CT

(min) =

where dV

CH START

dV

CT

is the hysteresis on the fault detection cir

CT

cuitry. During operation in the latched fault mode config
uration dVCT = 2.5V. When the UCC3917 is configured
for the hiccup or retry mode of fault operation

=2.0V.

dV

CT

If the power limit function is used the CT charging cur
rent becomes a function of I

CH+IPL

. And CT(min) is

found from:

-

-

-

6

(2)

(3)

-

-

-

APPLICATION INFORMATION (cont.)

CT

(min)

≅

–




VIN I R e




I



CH

––

+

••

MAX LOAD






1






R

PL

t

•

RC

LOAD LOAD








dt

•

dV

CT

IPL(PK)

I

VIN-V

PL

T

Figure 4. Relationship between IPL,V

Since I

is a function of the output voltage, V

PL

START

PL

and T

OUT

OUT

varies over time, equation 4 must be integrated to solve
for CT(min). However equation 4 can be easily approxi
mated if the output voltage slews. If the output voltage
slews linearly then the CT charge current contribution
from the power limit circuitry is shown to be at a peak
when V

is the power limit voltage threshold. IPLis shown in

V

PL

= 0V and at 0A when V

OUT

=VIN-VPL, where

OUT

Fig. 4 below.

Where I

I

is defined as:

PL

VIN V V

––

()

≡

PL

OUT PL

R

PL



























V

OUT

START

, which

(4)

.

(5)

UCC1917
UCC2917
UCC3917

Please note that the actual on-time in hiccup mode

threshold current 60µA. For example, if the minimum
when operating into a short is defined by:

CT dV

•

CT

Ton

()=

IIpk

+

CH PL

where dV

Ipk

PL

~2.0V and

CT

=

()

VIN
R

PL

A

Selecting Other External Components

Other external components are necessary for correct
operation of the IC. Referring to the application diagram
at the back of the data sheet, resistors R
R1, R2 and R3 are required and follow certain equations
with a brief description following where applicable:

R=

SENSE

R=

SS

50mV

I

FAULT

V–5V

IN

5mA

GND)

R3 =

IN

5mA

(Used in series with a diode to

–

V10

connect VIN to VDD)

(R1+ R2) > 20kΩ

Lastly, the external capacitors used for the charge pump
are required and need to equal 0.1µF, i.e. C

­C1 = C2 = 0.1µF.

LEVEL Shift Circuitry (Optional)

The UCC3917 can be used in many systems without
logic command or diagnostic feedback. If a system re
quires control from low-voltage logic or feedback to
low-voltage logic, then level shifting circuits are required.
The level shift circuits in Fig. 5A and Fig. 5B show ways
to interface to LATCH
circuits in Fig. 6 show ways of interfacing from FLTOUT
to low-voltage logic.

seconds

()

SENSE,RSS

(Sense Resistor)

(Connected between VSS and

(Current limit out of VREF)

IN

and SHTDWN and the level shift

(8)

(9)

,

=CH=

-

The average I

current for the interval (0, T

PL

Fig. 4 is defined as:

2

PL

I AVG

()

PL

VIN V

–

()

≡

RVIN

2

••

PL

Equation 4 can now be simplified to:

I I AVG

+

CT

()

min ≅

CH PL

()

dV

CT

T

•

START

START

) from

(6)

(7)

In Fig. 5A, resistor R limits the level shift current. Select
R so that the current in the level shift circuit never ex
ceeds the absolute maximum current in the logic com
mand inputs, 500µA. For example, if the maximum
supply voltage for the system is 75V, select

V

75

R

>=

500

A

150µΩ

.

k

R must also be chosen so that the minimum current in
the level shift circuit exceeds the worst case logic

7

-

-

T

APPLICATION INFORMATION (cont.)

UCC1917
UCC2917
UCC3917

R

SHTDWN

OR

LATCH

(A)

SHTDWN

OR

LATCH

R

(B)

C

VOUT

C

VOUT

Figure 5. Potential level shift circuitry
to interface to LATCH

V

13

and SHTDWN on the

DD

TO

UCC3917

TO

UCC3917

UDG-99148

supply voltage for the system is 25V, choose

V

25

R

>=

60

A

416µΩ

.

k

The capacitor C shown on the output of this circuit is
useful to filter the level shift output and prevent false
triggering from noise. The minimum recommended ca
pacitor value is 100pF. Larger capacitors will result in
better noise immunity and longer delay to logic com
mand.

The circuit in Fig. 5B accomplished the same function as
the circuit in Fig. 5A, using different components. In this
circuit, select resistor R so that the transistor draws
enough current to exceed the 60µA logic threshold but
doesn’t exceed the 500µA maximum logic input current.
For example, if the input circuit is 5V logic, then

V

DD

13

V

DD

13

-

-

R1

LOCAL
FAULT

LOCAL

VDD

R2

LOCAL

FLTOUT11

LOCAL

FAULT

(A) (B) (C)

VDD

R1

R2

FLTOUT

11 11

LOCAL
FAULT

Figure 6. Potential level shift circuitry to interface to FLTOUT on the UCC3917.

LOCAL

VDD

FLTOU

R1

R2

8

APPLICATION INFORMATION (cont.)

D1

UCC1917
UCC2917
UCC3917

V

IN

R3

SHTDWN

FLTOUT

C1P

C1

C1N

C2P

C2

C2N

VOUT

15

LATCH

V

DD

ON-TIME

DELAY

R1 R2

5V

VDD

40µA

VOUT

CURRENT

COMPARATOR

DISABLE

OUTPUT

OVER

LOW

50mV

200mV

R

PLIM

1

OUTPUT

3

+

+

10

2

4

SENSE

VOUT

CT

PL

C

IN

R

SENSE

C

T

C

H

C

SS

VDD

13 16

V

DD

40µA

12

VOUT

11

8

7

6

5

9 14

VSS MAXI

R

SS

UVLO
>10V=ENABLE
< 6V=DISABLE

10V SHUNT

REGULATOR

5V

REFERENCE

LOGIC

SUPPLY

4V

VREF/CATFLT

Figure 7. Positive floating hot swap power manager UCC1917, UCC2917 and UCC3917.

SAFETY RECOMMENDATIONS

Although the UCC3917 is designed to provide system
protection for all fault conditions, all integrated circuits can
ultimately fail short. For this reason, if the UCC3917 is in
tended for use in safety critical applications where UL or
some other safety rating is required, a redundant safety

UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. [phone] FAX [phone]

device such as a fuse should be placed in series with
the power device. The UCC3917 will prevent the fuse

-

from blowing for virtually all fault conditions, increasing
system reliability and reducing maintenance cost, in ad
dition to providing the hot swap benefits of the device.

9

OUTPUT

UDG-99056

-