The UCC1913 family of negative voltage circuit breakers provides complete power management, hot swap, and fault handling capability. The IC is
referenced to the negative input voltage and is driven through an external
resistor connected to ground, which is essentially a current drive as opposed to the traditional voltage drive. The on-board 10V shunt regulator
protects the IC from excess voltage and serves as a reference for programming the maximum allowable output sourcing current during a fault. All
control and housekeeping functions are integrated, and externally programmable. These include the fault current level, maximum output sourcing current, maximum fault time, soft start time, and average power limiting. In the
event of a constant fault, the internal timer will limit the on-time from less
than 0.1% to a maximum of 3%. The duty cycle modulates depending on
the current into the PL pin, which is a function of the voltage across the
FET, and will limit average power dissipation in the FET. The fault level is
fixed at 50mV across the current sense amplifier to minimize total dropout.
The fault current level is set with an external current sense resistor. The
maximum allowable sourcing current is programmed with a voltage divider
from VDD to generate a fixed voltage on the IMAX pin. The current level,
when the output appears as a current source, is equal to V
IMAX/RSENSE
desired, a controlled current startup can be programmed with a capacitor
on the IMAX pin.
When the output current is below the fault level, the output device is
switched on. When the output current exceeds the fault level, but is less
than the maximum sourcing level programmed by the IMAX pin, the output
remains switched on, and the fault timer starts charging CT. Once CT
charges to 2.5V, the output device is turned off and performs a retry some
time later. When the output current reaches the maximum sourcing current
level, the output appears as a current source, limiting the output current to
the set value defined by IMAX.
.If
BLOCK DIAGRAM
LOGIC
SUPPLY
9.5V SHUNT REGULATOR
SD/FLT
SLUS274 - JANUARY 1999
1
20µA
Other features of the UCC1913 family include undervoltage lockout, and
8-pin small outline (SOIC) and Dual-In-Line (DIL) packages.
Lead Temperature (Soldering, 10 sec.). . . . . . . . . . . . . +300°C
All voltages are with respect to VSS (The most negative voltage). All currents are positive into, negative out of the specified
terminal. Consult Packaging Section of Databook for thermal
limitations and considerations of packages.
CONNECTION DIAGRAMS
DIL-8, SOIC-8 (Top View)
N or J, D Package
SD/FLT
IMAX
VDD
CT
1
2
3
4
8
7
6
5
UCC1913
UCC2913
UCC3913
PL
OUT
SENSE
VSS
ELECTRICAL CHARACTERISTICS: Unless otherwise stated these specifications apply for T
UCC1913; –40°C to +85°C for UCC2913; 0°C to +70°C for UCC3913; I
UCC1913; –40°C to +85°C for UCC2913; 0°C to +70°C for UCC3913; I
PARAMETERTEST CONDITIONSMINTYPMAX UNITS
Power Limiting Section
V
Duty Cycle ControlIPL= 64µA0.61.21.7%
Overload Section
Delay to Output(Note 1)300500ns
Output Sink CurrentV
ThresholdRelative to IMAX140200260mV
Note 1: Guaranteed by design. Not 100% tested in production.
Regulator VoltageIPL= 64 A4.354.855.35V
SENSE
Unless otherwise stated these specifications apply for TA= –55°C to +125°C for
= 2mA, CT = 4.7pF, TA= T
VDD
I
= 1mA0.0450.10.17%
PL
SENSE
= V
= 300mV40100mA
IMAX
J
PIN DESCRIPTIONS
CT: A capacitor is connected to this pin in order to set the
maximum fault time. The maximum fault time must be
more than the time to charge external load capacitance.
The maximum fault time is defined as:
()
CT
T
FAULT
•2
=
I
CH
where
IAI
=+36µ
CHPL
and I
is the current into the power limit pin. Once the
PL
,
fault time is reached the output will shutdown for a time
given by:
TCT
=••2 106
SD
IMAX: This pin programs the maximum allowable sourcing current. Since VDD is a regulated voltage, a voltage
divider can be derived from VDD to generate the program level for the IMAX pin. The current level at which
the output appears as a current source is equal to the
voltage on the IMAX pin over the current sense resistor.
If desired, a controlled current startup can be programmed with a capacitor on the imax pin, and a programmed start delay can be achieved by driving the
shutdown with an open collector/drain device into an RC
network.
OUT: Output drive to the MOSFET pass element.
PL: This feature ensures that the average MOSFET
power dissipation is controlled. A resistor is connected
from this pin to the drain of the NMOS pass element.
When the voltage across the NMOS exceeds 5V, current
will flow into the PL pin which adds to the fault timer
charge current, reducing the duty cycle from the 3%
level. When I
>>36µA then the average MOSFET
PL
power dissipation is given by:
−
PIMAX R
FET avgPL
=•••
()
110
6
SENSE: Input voltage from the current sense resistor.
When there is greater than 50mV across this pin with respect to VSS, then a fault is sensed, and CT starts to
charge.
SD/FLT: This pin provides fault output indication and
shutdown control. Interface into and out of this pin is usually performed through level shift transistors. When 20µA
is sourced into this pin, shutdown drives high causing the
output to disable the NMOS pass device. When opened,
and under a non-fault condition, the SD/FLT pin will pull
to a low state. When a fault is detected by the fault timer,
or undervoltage lockout, this pin will drive to a high state,
indicating the output FET is off.
VDD: Current driven with a resistor to a voltage at least
10V more positive than VSS. Typically a resistor is connected to ground. The 10V shunt regulator clamps VDD
at 10V above the VSS pin, and is also used as an output
reference to program the maximum allowable sourcing
current.
VSS: Ground reference for the IC and the most negative
voltage available.
3
Page 4
APPLICATION INFORMATION
LOAD
8
6
5
PL
5.0V
SENSE
+
50mV
VSS
OUTPUT
R
PL
R
S
VSS
INPUT VOLTAGE
V
DD
OVERCURRENT
COMPARATOR
OVERLOAD COMPARATOR
I1
36µA
H=CLOSE
I2
1µA
CT
4
C
T
I3
1mA
2.5V
H=CLOSE
0.5V
UCC1913
UCC2913
UCC3913
0.2V
+
SQ
FAULT TIMING CIRCUITRY
SENSE
IMAX
TO OUTPUT
DRIVE
H=OFF
QR
VSS
Figure 1. Fault timing circuitry for the UCC1913, including power limit overload.
Figure 1 shows the detailed circuitry for the fault timing
function of the UCC1913. For the time being, we will discuss a typical fault mode, therefore, the overload comparator, and current source I3 does not work into the
operation. Once the voltage across the current sense resistor, R
, exceeds 50mV, a fault has occurred. This
S
causes the timing capacitor to charge with a combination
of 36µA plus the current from the power limiting amplifier.
The PL amplifier is designed to only source current into
the CT pin and to begin sourcing current once the voltage across the output FET exceeds 5V. The current I
is related to the voltage across the FET with the following
expression:
VV
−5
FET
I
=
PL
Where V
R
PL
is the voltage across the NMOS pass de-
FET
vice.
Later it will be shown how this feature will limit average
power dissipation in the pass device. Note that under a
During a fault, CT will charge at a rate determined by the
internal charging current and the external timing capacitor. Once CT charges to 2.5V, the fault comparator
switches and sets the fault latch. Setting of the fault latch
causes both the output to switch off and the charging
switch to open. CT must now discharge with the 1µA current source, I2, until 0.5V is reached. Once the voltage at
CT reaches 0.5V, the fault latch resets, which re-enables
the output and allows the fault circuitry to regain control
of the charging switch. If a fault is still present, the fault
comparator will close the charging switch causing the cy-
PL
cle to begin. Under a constant fault, the duty cycle is
given by:
DutyCycle
=
A
IA
+136µµ
PL
Average power dissipation in the pass element is given
by:
PVIMAX
FET avgFET
=• •
()
condition where the output current is more than the fault
level, but less than the max level, V
~ VSS (input
OUT
where V
>> 5V IPLcan be approximated as :
FET
voltage), IPL= 0, the CT charging current is 36µA.
and where IPL>>36µA, the duty cycle can be approximated as :
UDG-99004
A
IA
+136µµ
PL
V
R
FET
PL
4
Page 5
APPLICATION INFORMATION (cont.)
IOUT
IMAX
Output
Current
IFAULT
Io(nom)
UCC1913
UCC2913
UCC3913
0A
CT
V
C
T
2.5V
Voltage
(w/respectt oVSS)
0.5V
0V
OUT
V
0V
Output
Voltage
(w/respecttoGND)
VSS
t
0
t1 t2t3t4t5t6 t7 t8t9 t10
t0: safe condition – output current is nominal, output
voltage is at the negative rail, VSS.
t1: fault control reached – output current rises above
the programmed fault value, CT begins to charge at
≅ 36µA.
t2: max current reached – output current reaches the
programmed maximum level and becomes a constant current with value I
MAX
.
t3: fault occurs – CT has charged to 2.5V, fault output
goes high, the FET turns off allowing no output current to flow, V
floats up to ground.
OUT
t4: retry – CT has discharged to 0.5V, but fault current
is still exceeded, CT begins charging again, FET is
on, V
pulled down to VSS.
OUT
t
t
t
t5: t5 = t3: illustrates 3%duty cycle.
t6: t6 = t4
t7: output short circuit - if V
is short circuited to
OUT
ground, CT charges at a higher rate depending
upon the values for VSS and R
PL
.
t8: fault occurs – output is still short circuited, but the
occurrence of a fault turns the FET off so no current
is conducted.
t9: t9 = t4; output short circuit released, still in fault
Therefore, the maximum average power dissipation in
the MOSFET can be approximated by:
P
FET avg
VIMAX
FET
=
()
AR
••
11µ
V
•
FET
PL
IMAXA R
=••
µ
PL
Figure 3.
∞
Figure 4. Plot average power vs. FET voltage for
increasing values of R
LOCAL VDD
SHUTDOWN
FAULT OUT
LOCAL GND
LEVEL SHIFT
PL
.
R3
R4
SD/FLT7
VSS
Notice that in the approximation, V
cancels. therefore,
FET
average power dissipation is limited in the NMOS pass
element.
Overload Comparator
The linear amplifier in the UCC1913 ensures that the
output NMOS does not pass more than I
V
IMAX/RS
programmed I
). In the event the output current exceeds the
by 0.2V/RS, which can only occur if
MAX
MAX
(which is
the output FET is not responding to a command from the
IC, the CT pin will begin charging with I3, 1mA, and continue to charge to approximately 8V. This allows a constant fault to show up on the SD/FLT pin, and also since
the voltage on CT will only charge past 2.5V in an overload fault mode, it can be used for detection of output
FET failure or to build in redundancy in the system.
Determining External Component Values
Referring now to Figure 3. To set R
the following
VDD
must be achieved:
V
IN
R
()
min
VDD
V
10
>
()
RR
12
+
+
2
mA
In order to estimate the minimum timing capacitor, CT,
several things must be taken into account. For example,
given the schematic below as a possible (and at this
point, a standard) application, certain external component values must be known in order to estimate C
Now, given the values of C
, Load, R
OUT
SENSE
, VSS, and
T(min)
.
the resistors determining the voltage on the IMAX pin,
the user can calculate the approximate startup time of
the node V
. This startup time must be faster than the
OUT
time it takes for CT to charge to 2.5V (relative to VSS),
and is the basis for estimating the minimum value of CT.
In order to determine the value of the sense resistor,
R
rent, R
, assuming the user has determined the fault cur-
SENSE
can be calculated by:
SENSE
mV
R
SENSE
=
50
I
FAULT
Figure 5. Possible level shift circuitry to interface to
the UCC1913.
6
Page 7
APPLICATION INFORMATION (cont.)
Next, the variable I
maximum current that the UCC1913 will allow through
the transistor, M1, and it can be shown that during
startup with an output capacitor the power MOSFET, M1,
can be modeled as a constant current source of value
where:
I
MAX
V
I
MAX
where V
IMAX
=
R
SENSE
= voltage on pin IMAX.
IMAX
Given this information, calculation of the startup time is
now possible via the following:
Current Source Load:
must be calculated. I
MAX
MAX
is the
UCC1913
UCC2913
UCC3913
CVSS
•
T
START
Resistive Load:
TCRn
STARTOUTOUT
Once T
START
UCC1913 must be addressed and component values derived. Assuming the user chooses to limit the maximum
allowable average power that will be associated with the
circuit breaker, the power limiting resistor, R
easily determined by the following:
OUT
=
II
−
MAXLOAD
IR
=••
IRVSS
MAXOUT
•
MAXOUT
•−
is calculated, the power limit feature of the
, can be
PL
SD/FLT
20µA
V
5.0V
REF
DD
LOGIC
SUPPLY
9.5V SHUNT REGULATOR
1
R
VDD
VDD
3
SOURCE
ONLY
UVLO
1=
UNDERVOLTAGE
ON-TIME
CONTROL
C
VDD
IMAX
2
R2
CSS
V
DD
DISABLE
VSS
LINEAR
CURRENT
AMPLIFIER
+
50Ω
V
FAULT=
50mV
DD
8
7
6
5
PL
R
OUT
SENSE
VSS
OUTPUT
T
R
S
R1
+
Figure 6. Typical application diagram.
C
T
CT
4
VSS
UDG-99002
7
Page 8
APPLICATION INFORMATION (cont.)
P
()
PL
=
FET avg
AI
•1µ
MAX
exists defined by
PL
R
()
PL
min
=
VSS
mA
5
R
where a minimum R
Finally, after computing the aforementioned variables,
the minimum timing capacitor can be derived as such:
Current Source Load:
()
TARVSSV
•••+−
C
T
=
()
min
36210
STARTPL
10
µ
R
•
PL
SAFETY RECOMENDATION
Although the UCC3913 is designed to provide system
protection for all fault conditions, all integrated circuits
can ultimately fail short. For this reason, if the UCC3913
is intended for use in safety critical applications where
UL or some other safety rating is required, a redundant
UCC1913
UCC2913
UCC3913
Resistive Load:
C
3315
3
safety device such as a fuse should be placed in series
with the device. The UCC3913 will prevent the fuse from
blowing for virtually all fault conditions, increasing system
reliability and reducing maintenance cost, in addition to
providing the hot swap benefits of the device.
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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