Datasheet UCC2585, UCC3585 Datasheet (UNITRODE)

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Page 1

查询UCC2585供应商

Low Voltage Synchronous Buck Controller

UCC2585 UCC3585

PRELIMINARY

FEATURES

Resistor Programmable 1.25V to 4.5V

•

OUT

2.5V to 6V Input Supply Range

•

1% DC Accuracy

•

High Efficiency Synchronous

•

Switching Drives P-channel (High Side) and

•

N-channel (Low Side) MOSFETs Lossless Programmable Current Limit

•

Logic Compatible Shutdown

•

Programmable Frequency

•

Start-up Voltage Tracking Protects

•

Dual Rail Microprocessors

DESCRIPTION

The UCC2585/UCC3585 synchronous Buck controller provides flexible high efficiency power conversion for output voltages as low as 1.25V with guaranteed ±1% DC accuracy. Output currents are only limited by the choice of external logic level MOSFETs. With an input voltage range of

2.5V to 6.0V it is the ideal choice for 3.3V only, battery input, or other low voltage systems. Applications include local microprocessor core voltage power supplies for desktop and Notebook computers, and high speed GTL bus regulation.Its fixed frequency oscillator is capable of providing practical PWM operation to 700kHz.

With its low voltage capability and inherent “always on” operation, the UCC2585/UCC3585 causes VOUT to track VIN once VIN has exceeded the threshold voltage of the external P channel MOSFET. Tracking can be tailored for any application with a single resistor or disabled by connecting TRACK to VIN. For dual supply rail microprocessors this feature negates the need for external diodes to insure supply voltage tracking between the +3.3V and lower voltage microprocessor core supplies.

(continued)

TYPICAL APPLICATION DIAGRAM

VIN

3.2N

10k

549k

0.22µF C6

470pF

15 VIN

3 SS

100k

RTN

150µFC2150µF

147pF

ENB

COMP

VFB

ISET

0.47µF

CLSET

PDRV

ISENSE

NDRV

TRACK

N/C

PWRGND

GND

27.4k

Q1 IRF7404

L1 4.7µF

Q2 IRF7401

220µF

C10

C11 220µF

R12

32k

R10

36k

R11

82k

VOUT

RTN

07/99

UDG-98024

Page 2

UCC2585 UCC3585

ABSOLUTE MAXIMUM RATINGS

Analog Pins

Minimum and Maximum Forced Voltage

(Reference to GND) . . . . . . . . . . . . . . . . . . . –0.3V to +6.3V

Digital Pins

Minimum and Maximum Forced Voltage

(Reference to GND) . . . . . . . . . . . . . . . . . . . . .–0.3V to 6.3V

Power Driver Output Pins

Maximum forced current . . . . . . . . . . . . . . . . . . . . . . . . . ±1.0A

Operating Junction Temperature. . . . . . . . . . –55°C to +125°C

Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C

Note: Unless otherwise indicated, voltages are reference to ground and currents are positive into, negative out of, the spec ified terminals. Pulsed is defined as a less than 10% duty cycle with a maximum duration of 500ns.

APPLICATIONS

Low Voltage Microprocessor Power such as PowerPC

•

603 and 604 High Power 5V or 3.3V to 1.25V–4.5V Regulators

•

• GTL Bus Termination

CONNECTION DIAGRAMS

DIL-16, SOIC-16, SSOP-16 (TOP VIEW) J, N, D, and M Packages

ENB

VFB

GND

ISET

COMP

TRACK

CLSET

VIN

NDRV

PWRGND

PDRV

ISENSE

N/C

DESCRIPTION (cont.)

The UCC2585/UCC3585 drives a complementary pair of power MOSFET transistors, P-channel on the high side, and N-channel on the low side to step down the input voltage at up to 90% efficiency.

A programmable two-level current limiting function is provided by sensing the voltage drop across the high side P channel MOSFET. This circuit can be configured to pro vide pulse-by-pulse limiting, timed shutdown after 7 con

secutive faults, or latch-off after fault detection, allowing maximum application flexibility. The current limit threshold is programmed with a single resistor selected to match system MOSFET characteristics.

The UCC2585/UCC3585 also includes undervoltage lockout, a logic controlled enable, and softstart functions.

The UCC2585/UCC3585 is offered in the 16 pin surface

mount and through hole packages.

Page 3

UCC2585 UCC3585

ELECTRICAL CHARACTERISTICS:

UCC3585, and T C

= 330pF, R

= –40°C to 85°C for the UCC2585. TA=TJ. VIN = 3.3V, ENB, I

= 100k, RTRACK = 10k, RCLSET = 10k.

ISET

Unless otherwise stated, these specifications hold for TA= 0°C to 70°C for the

= VIN,VFB= 1.25V, COMP = 1.5V,

SENSE

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

Input Supply Section

Supply Current – Total (Active) 2.3 3.5 mA Supply Current – Shutdown ENABLE = 0V 10 25 µA VIN Turn On Threshold (UVLO) 2.35 2.60 V VIN Turn On Hysteresis 450 550 mV

Voltage Amplifier Section

Input Voltage (Internal Reference) T

= 0°C to 70°C, VIN = 3.0V to 3.6V, Note 1 1.238 1.250 1.262 V

Input Voltage (Internal Reference) VIN = 3.0V to 3.6V, IND/MIL Temp, Note 1 1.228 1.250 1.273 V Open Loop Gain COMP = 0.5 to 2.5V 65 80 dB Output Voltage High I(COMP) = –50µA 3.00 3.25 V Output Voltage Low I(COMP) = 50µA 0.10 0.25 V Output Source Current –100 –175 µA Output Sink Current 0.4 1.0 mA

Oscillator/PWM Section

Initial Accuracy T

= 25°C 405 450 495 kHz

Initial Accuracy Over Temperature 390 450 510 kHz CT Ramp Peak to Valley 1.8 2.1 2.4 V CT Ramp Valley Voltage 0.3 0.4 V PWM Maximum Duty Cycle COMP = 3V, Measured on PDRV 100 % PWM Minimum Duty Cycle COMP = 0.2V, Measured on PDRV 0 % PWM Delay to Outputs COMP = 2.5V 45 ns Tracking Current Measured on TRACK, V

= 1.6V 10 12 15 µA

TRACK

Enable High Threshold Measured on ENABLE (Note 3) 2.8 V Enable Low Threshold Measured on ENABLE 0.5 V Softstart Charge Current SS = 0V –10 –14 –18 µA

Current Limit Section

Pulse to Pulse Threshold Measured Between V

and I

SENSE

100 125 150 mV CLSET Current 11 14 16 µA SD Sink Current SD = 2V 8 13 18 µA SD Source Current SD = 2V –100 –140 µA Restart Threshold Measured on SDOWN 0.40 0.55 0.90 V

Output Driver Section (PDRV, NDRV)

Pull Up Resistance –100mA (Source) T Pull Down Resistance 100mA (Sink) T

= 25°C6Ω

= 25°C4Ω

Deadtime Delay Note 2 150 200 250 ns

Note 1. Measured on COMP with the Error Amp in a Unity Gain (voltage follower) configuration. Note 2. 50% point of PDRV Rise to NDRV Rise and 50% point of NDRV Fall to PDRV Fall. Note 3. Enable High Threshold = V

–0.5.

Page 4

BLOCK DIAGRAM

UCC2585 UCC3585

VIN

ISETTRACK

PRECISION

CLK

BIAS SET

UVLO

REVERSE

CURRENT

LIMIT

ANTI

SHOOT THRU

SOFTSTART COMPLETE

OVER CURRENT COUNTER

SHUTDOWN TIMER

H = NO OVERCURRENT

10µA

L =NO SHUTDOWN H = LATCHEDSHUTDOWN CAP =TIMED SHUTDOWN

10µA

1.25V

1ENB

2COMP

4VFB

3SS

9NC

ENABLE

VIN –0.8V

1.25V

SOFTSTART COMPLETE

REVERSE CURRENT

LOGIC

REF

PWM

10µA

REVERSE

16 10 CT

UVLO

PRECISION

BIAS

OSCILLATOR

TRACK

GND

R Q

PWM

LATCH

CLSET

CURENT

LIMIT ADJ

DRIVER

TRACK

DRIVER

DISABLE DRIVERS

ISENSE

12 PDRV

14 NDRV

13 PWRGND

UDG-98008

PIN DESCRIPTIONS

CLSET: CLSET is used to program the pulse by pulse

and overcurrent shutdown levels for the UCC1585. A re sistor is connected between CLSET and VIN to set the thresholds. The threshold follows the following relation ship:

125.

lcl

COMP: Output of the Voltage type error amplifier. Loop compensation components are connected between COMP and VFB.

CT: A high quality ceramic capacitor connected between this pin and ground sets the PWM oscillator frequency by the following relationship:

6700()

ISET

RDS on

•

()

CLSET

Use capacitor values greater than 100pF in order to mini mize the effects of stray capacitance. The oscillator is ca

pable of reliable operation in excess of 1MHz.

ENB: A LOGIC1 (V

–0.5V) on this input will activate the

Output drivers. A logic zero (0.5V) will prevent switching of the output drivers. Do not allow ENB to remain be tween these levels steady state.

GND: Reference level for the IC. All voltages and cur rents are with respect to GND.

ISENSE: ISENSE performs two functions. The first is to monitor the voltage dropped across the high side P chan nel MOSFET switch while it is conducting. This informa tion is used to detect over current conditions by the current limit circuitry. The second function of ISENSE is to measure current through the lowside N-channel MOSFET. When the current flow through this MOSFET is drain to source, (i.e. reversed), this FET is turned off for the remainder of the switching cycle.

Page 5

PIN DESCRIPTIONS (cont.)

ISET: A resistor is connected between ISET and ground

to program a precision bias for many of the UCC2585/UCC3585 circuit blocks. Allowable resistor val ues are 90kΩ to 110kΩ. 1.25V is provided to ISET via a buffered version the internal bandgap voltage reference.

This current is mir

The resultant current is 1.25V / R rored directly over to CLSET to program the over current thresholds. A second use for this current is to set a basis for the charging current of the oscillator.

PDRV: High current driver output for the high side P channel MOSFET switch. A 3Ω to 10Ω series resistor be tween PDRV and the MOSFET gate may be inserted to reduce ringing on this pin. In some layout situations, a low V

diode may be required from this pin to ground to

keep the pin from ringing more than 0.5V below ground. PWRGND: High current return path for the MOSFET

drivers. PWRGND and GND should be terminated to gether as close to the IC package as possible.

SD: This pin can configure current limit to operate in any one of three different ways.

1) A forced voltage of less than 250mV on SD inhibits the shutdown function causing pulse by pulse limiting.

2) A capacitor from SD to GND provides a controller-converter shutdown timeout after 7 consecutive overcurrent signals are received by the current limit circuitry. An interval 10µA (typ) current source discharges the SD capacitor to the 0.5V (typ) restart threshold. The shutdown time is given by:

[]

•−0510.

()

SHUT

where C

SD IN

is the value of the capacitor from SD to GND,

and VIN is the chip supply voltage (on pin 15). At this point, a softstart cycle is initiated, and a 100µA current (typ) quickly recharges SD to VIN. During softstart, pulse by pulse limiting is enabled, and the 7 cycle count is de layed until softstart is complete (i.e. charged to approxi mately VIN volts).

3) A forced voltage of greater than 1V on SD will cause the UCC2585/UCC3585 to latch OFF after 7 overcurrent signals are received.After the controller is latched off, SD must drop below 250mV to restart the controller.

ISET

UCC2585 UCC3585

SS: A low leakage capacitor connected between SS and

GND will provide a softstart function for the converter. The voltage on this capacitor will slowly charge on start-

up via an internal current source. The output of the Volt age error amplifier (COMP) tracks this voltage thereby limiting the controller duty ratio.

NDRV: High current driver output for the low side

MOSFET switch. A 3Ω to 10Ω series resistor between NDRV and the MOSFET gate may be inserted to reduce ringing on this pin. In some layout situations, a low V ode may be required from this pin to ground to keep the

pin from ringing more than 0.5V below ground.

TRACK: A resistor is connected between TRACK and output voltage of the converter to set the start-up profile of the power converter. Certain dual supply rail micropro cessors require that a maximum voltage differential be tween the supply rails is not exceeded. Failure to do so

results in large currents in the microprocessor through the ESD (electrostatic discharge) protection devices.This can result in chip failure. The UCC2585/UCC3585 is designed such that it is “normally on” before V the 2.0V (nom.) UVLO threshold. That is, the high side P channel MOSFET switch driver output is actively held low allowing the MOSFET to conduct current to the output as soon as V

is high enough to exceed the gate turn on

threshold. The resistor from TRACK to V voltage level on VOUT at which the P channel MOSFET is turned off. The tracking cutoff voltage follows the following relationship:

VVAR

(max) .=+•125 12µ

OUT TRACK

()

This is necessary for very low output voltage applications (< 2.0V), where overvoltage may occur if the Pchannel MOSFET is not disabled before the UVLO threshold is reached. For applications with V

greater than 2.0V,

OUT

TRACK can be disabled by tying TRACK to V VFB: Inverting input to the Voltage type error amplifier.

The common mode input range for VFB extends from

GND to 1.5V.

VIN: Supply voltage for the UCC2585/UCC3585.Bypass with a 0.1µF ceramic capacitor (minimum) to supply the switching transient currents required by the external MOSFET switches.

OUT

reaches

sets the

Page 6

APPLICATION INFORMATION

Some of today’s microprocessors require very low oper ating voltages. In some cases, as low as 1.8V of supply voltage are required in addition to already available 3.3V system voltage. Following is an illustration of a design using the UCC3585 as the power controller.

The design criteria are as follows:

Input Voltage (V

•

Output Voltage (V

•

Output Ripple Voltage (V

•

Output Current (I

•

Other features include

Output Tracking

•

Switching Frequency (F

•

100% Surface Mount

•

The first few steps in the design are to define the power stage (Schematic Fig. 1).

1) The normal operating duty cycle (δ) of the regulator is approximately

) 3.3V DC

) 1.8V DC

OUT

) 3.5A DC

OUT

) 18mV

OUT

) 350kHz

UCC2585 UCC3585

OUT

δ= = =

2) Select the output inductor to meet ripple current re quirements.For this design, the allowable ripple current in the output inductor is selected to be 10% of the full load output current.

A Pulse Engineering SMT inductor (PE-53682) is 4.7µH has a DC resistance (R

0.1W under full load operation. The resulting ∆I

∆

OUT

3) Next, the output capacitors are determined based upon the output ripple criteria. Assuming the ripple is limited by the equivalent series resistance, or ESR, of the capacitors and not the impedance of the capacitors at the switching frequency, then the output capacitor selection is based upon ESR, size and voltage considerations.

0 545

•

is now:

OUT

−

..47 10

•

46=

−

•=

−()

IN OUT

••

SOUT

()

IN OUT

.δµ

) of 8.3mΩ and will dissipate

RTN

VIN

150µFC2150µF

147pF

3.2N

10k

549k

0.22µF C6

470pF

15 VIN

3 SS

100k

ENB

COMP

VFB

ISET

0.47µF

CLSET

PDRV

ISENSE

NDRV

TRACK

N/C

PWRGND

GND

27.4k

Q1 IRF7404

L1 4.7µF

Q2 IRF7401

220µF

C10

C11 220µF

R12 32k

VOUT

R10 36k

R11 82k

RTN

UDG-98024

Figure 1. Application circuit schematic.

Page 7

APPLICATION INFORMATION (cont.)

ESR

===

∆

OUT

A 220µF, 6.3V Sprague 594D capacitor has an ESR of 75mΩ. Three of these in parallel will result in an overall ESR of 25mΩ. (C9, C10, and C11 in Fig. 1). Since the output ripple current is so low, the capacitor’s ripple cur rent rating of 1.45A is not a concern.

To check the assumption that the capacitor’s impedance at the switching frequency is dominated by the ESR and not the capacitor’s capacitance value, calculate the im pedance and compare it to the ESR.

∆

FC k

••=••

ππ µ

The ESR of the capacitor is 37 times that of the imped ance of the capacitor at the switching frequency, so the earlier assumption was valid.

4) Before selecting the switching MOSFETs, the current that will be flowing through them must first be determined.

==+

DOUT

The RMS of this current in Q1 is

IQ I A

128==δ .

DRMS D

And in Q2

OUT

0 018

2 350 220

∆

OUT

0 026

38.

Ω

UCC2585 UCC3585

and a body diode turn OFF switching time (t 59ns. In this topology, the N Channel MOSFET, Q2, is turned OFF prior to the turn ON of Q1, so when Q2 is turned OFF, current is being re-routed from the channel of the device into the intrinsic body diode. Therefore Q2’s intrinsic body diode incurs switching loss during the turn

OFF interval. The conduction loss in Q2 is:

PQ IQ R Q W

22 202

DOND RMS DS

The gate drive losses will be

PQ Q V F mW

DGATE G INS

=•=.

255

=••=

And the body diode turn OFF loss:

PQ V I T F W

D D OFF IN D OFF S

The total power loss for Q2 is the sum of these three:

PQ W

204= .

DTOTAL

7) Thus far the power loss in the two MOSFETs and the output inductor total 1.0W. The average input current is:

VIP

•+

OUT OUT LOSS

AVG

The peak to peak ripple in the input capacitors is the peak current less the average input current during Q1’s ON time, and equal to the average input current during Q1’s OFF time.The RMS value of this current is then:

1 2

=22.

0132_.=• • • • =

OFF

2) of

IQ I A

2125=−=δ .

DRMSD

5) Since this regulator must be able to operate from a

3.3V source, the MOSFETs used must have a gate threshold level of no more than 2V.

For Q1, an IRF7404 is selected. It has an R

0.04Ω, a total gate charge (Q OFF (t

1) time of 65ns. The conduction loss in Q1 will

OFF

1) of 50nC, and a turn

DS(on)

be:

PQ IQ R Q W

1 1 1 0 593

DONDRMS DS

=•=.

The gate drive losses will be

PQ Q V F mW

158

DGATEG IN S

=••=

And finally the turn OFF losses are estimated

PQ V IQ T F W

D OFF IN D PK OFF S

=• • • • =.

1014

The total power loss for Q1 is the sum of these three:

PQ W

105= .

DTOTAL

6) Q2 has been selected to be an IRF7401, which has an R

DS(ON)

of 0.03Ω, and a total gate charge (QG2) of 48nC

IIII A

IN CAP D IN IN

()()().=− •+ •−=

RMS PK AVG AVG

119δδ

8) After the input capacitor’s input ripple current is known, select the input capacitors. Again, Sprague 594D Solid Tantalum capacitors are chosen. A single 150µF,

10V capacitor has a ripple current rating of 1.35A RMS. Two in parallel (C1 and C2) will have a combined capabil

ity of 2.7A, and a total ESR of 40mΩ. The losses in the capacitors are:

P I ESR W

DIN CAP IN CAP

Adding the capacitor loss to that previously found, the to

RMS

.=•=

014

tal losses are now 2.1W.

9) The overall efficiency of the power train is then

•

OUT OUT

•+

OUT OUT

=21084..

The losses are dominated by the MOSFETs Q1 and Q2. One way to improve the efficiency would be to reduce the conduction loss in Q1, either by choosing a device with a

Page 8

APPLICATION INFORMATION (cont.)

lower R The conduction losses in Q2 may be improved by the same technique, but will prove detrimental in switching losses. To lower the switching losses, Q2 may be paral leled with a Schottky diode. In this manner, the switching loss may be absorbed by the Schottky, instead of the MOSFET.

10) After the power stage design is completed, attention is given to the feedback loop. The LC filter gain is de scribed by the equation (10A) below: (where ω= j2π

Where C and C11 and R

There will be a double pole at:

and a zero at the point where the impedance of the out put capacitors equals the ESR:

The modulator gain is given by

PWM

where V lator ramp found on the CT pin. The overall open loop gain is shown in Fig.2.

or by paralleling it with another MOSFET.

DS(on)

is the combined capacitance of C9, C10,

OUT

is the ESR of the capacitors.

ESR

•

OUT

••

296π

ESR OUT

==165.

RAMP

is the peak to peak amplitude of the oscil-

RAMP

kHz

28π.

kHz

)

UCC2585 UCC3585

11) The voltage divider is next determined to give us the proper output voltage. First select one of the divider re sistors R11 = 82k. The other resistor becomes:

10 11 11 36=• −=

12) The equation for the error amplifier in this configura tion is:

For a gain of 5 and a zero at 2kHz

RR k

2 15 10 180=• =

and

The overall voltage loop gain now has a crossover at

34kHz with a phase margin of about 73 degrees.

13) Select the R of value should be between 90k and 110k.) Then choosing the current limit trip point to be 130% of I rent limit set resistor is then found by the relationship

Note that the R fects of temperature.

OUT

••

fp R

••

•

OUT

125

DS(on)

REF

ISET

••=

440=

resistor, R3, to be 100k. (The range

RQR k

()

DS on

value used should include the ef-

OUT

1272=

ISET

, the cur-

-10

-20

GAIN (dB)

-30

-40 10 100 1000 10000 100000

FREQUENCY (Hz)

Figure 2. Modulator and filter frequency response.

+• •

(10A)

KLC

ωω

+••+ •+•+

LC R C R C

OUT L OUT ESR OUT

 



ESR OUT

100

80 60 40 20

GAIN (dB)

-20

-40

-60 10 100 1000 10000 100000

OVERALL LOOP GAIN

FREQUENCY (Hz)

AMPLIFIER GAIN

Figure 3. Error amp and closed loop frequency response.



LOAD

 

Page 9

APPLICATION INFORMATION (cont.)

14) During normal power on of the UCC3585, the gate of Q1 is held low (Q1 turned ON) until the V IC reaches the 2V Under Voltage Lockout (UVLO) volt age. At UVLO, the UCC3585 wakes up and switching be gins on Q1 and Q2. With a 1.8V output however, the output will reach 2V before regulation begins! This is where the tracking function comes into use. By selecting an appropriate resistive divider from the output, we can select the point below UVLO at which Q1 will be shut off. Upon reaching UVLO, the UCC3585 will then begin to regulate normally.

With a 1.8V nominal output voltage, select the tracking turn off point to be 1.6V.

16 125

−=..

29=

Ω

Note that the tracking function ONLY makes a difference below UVLO. If V tracking pin should be tied to V

were to be 2V or above, then the

OUT

15) A capacitor on the SD pin will allow the converter to shutdown in the event seven consecutive over current pulses occur. If a timing shutdown interval of 1ms is chosen as the shutdown time, T

, then the value of the ca-

pacitor is:

Where I

(–.)

and I

CHG

 

•+



CHG DICHG

DISCHG

are 100µA and 10µA respect

 



fully.

16) The next step is to find the value of timing capacitor.

6000

476==

A 470pF capacitor will result in a switching frequency of 354kHz.

17) The softstart capacitor is selected for a 5ms startup time. Knowing that a 10µA current source will charge the capacitor to 2.5V, the softstart capacitor is given by:

•

SS CHG

510

•=µ

20=

32=

input to the

180

135

ERROR AMP

PHASE (DEGREES)

10 100 1000 10000 100000

OVERALL LOOP

FREQUENCY (Hz)

Figure 4. Error amp and closed loop frequency response.

WITHOUT "TRACK AND HOLD"

2.0

1.5

1.0

VOUT (V)

0.5

1.0 1.5 2.0 2.5

"TRACK AND HOLD"

POWERONPROFILE

POWER ON

PROFILE WITH

VIN (V)

Figure 5. Power on profile.

RT kΩ

UCC2585 UCC3585

UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460

1.2 1.4 1.6 1.8

VTR (V)

Figure 6. Tracking resistor value as a function of turn off voltage.

PowerPC is a registered trademark of International Business Machines Corporation

2.0

Page 10

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