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查询UCC1946供应商
Microprocessor Supervisor with Watchdog Timer
UCC1946
UCC2946
UCC3946
FEATURES
Fully Programmable Reset Threshold
•
Fully Programmable Reset Period
•
Fully Programmable Watchdog Period
•
2% Accurate Reset Threshold
•
VDD Can Go as Low as 2V
•
18µA Maximum IDD
•
Reset Valid Down to 1V
•
BLOCK DIAGRAM
400nA
DESCRIPTION
The UCC3946 is designed to provide accurate microprocessor supervi
sion, including reset and watchdog functions. During power up, the IC
asserts a reset signal RES
mains asserted until the VDD voltage rises and remains above the re
set threshold for the reset period. Both reset threshold and reset period
are programmable by the user. The IC is also resistant to glitches on
the VDD line. Once RES
threshold voltage need to be of certain time duration and voltage mag
nitude to generate a reset signal. These values are shown in Figure 1.
An I/O line of the microprocessor may be tied to the watchdog input
(WDI) for watchdog functions. If the I/O line is not toggled within a set
watchdog period, programmable by the user, WDO
The watchdog function will be disabled during reset conditions.
The UCC3946 is available in 8-pin SOIC(D), 8-pin DIP (N or J) and
8-pin TSSOP(PW) packages to optimize board space.
with VDD as low as 1V. The reset signal re
has been deasserted, any drops below the
will be asserted.
VDD
8
POWER TO
CIRCUITRY
-
-
-
-
4RP
1.235V .
WP
2RTH
400nA
6
1.235V
7WDI
POWER ON RESET
100mV
WATCHDOG TIMING
EDGE DETECT
Note: Pinout represents the 8-pin TSSOP package.
1
GND
8-BIT COUNTER
A3
A2
CLR
A1
A0
CLK
3RES
5
WDO
UDG-98001
SLUS247B - FEBRUARY 2000
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UCC1946
UCC2946
UCC3946
ABSOLUTE MAXIMUM RATINGS
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10V
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
CONNECTION DIAGRAM
SOIC-8, TSSOP-8, DIL-8 (Top View)
D, PW, N or J Package
Lead Temperature (Soldering, 10 sec.). . . . . . . . . . . . . +300°C
Currents are positive into, negative out of the specified terminal.
Consult Packaging Section of the Databook for thermal limita
tions and considerations of packages.
ELECTRICAL CHARACTERISTICS:
Unless otherwise specified, VDD = 2.1V to 5.5V for UCC1946 and UCC2946;
GND
1
-
2
RTH
RES
3
4
RP
8
VDD
7
WDI
6
WP
5
WDO
VDD = 2V to 5.5V for UCC3946; TA = 0°C to 70°C for UCC3946, –40°C to 95°C for UCC2946, and –55°C to 125°C for UCC1946;
T
A =TJ
PARAMETERS TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
UCC3946 UCC1946 & UCC2946
Operating Voltage 2.0 5.5 2.1 5.5 V
Supply Current 10 18 12 18 µA
Minimum VDD (Note 1) 1 1.1 V
Reset Section
Reset Threshold VDD Rising 1.210 1.235 1.260 1.170 1.235 1.260 V
Threshold Hysteresis 15 15 mV
Input Leakage 55nA
Output High Voltage I
Output Low Voltage I
SOURCE = 2mA VDD –
0.3
SINK = 2mA 0.1 0.1 V
VDD = 1V, I
SINK = 20uA 0.2 0.4 V
VDD –
0.3
V
VDD to Output Delay VDD = -1mV/µs (Note 2) 120 120 µs
Reset Period C
RP = 64nF 160 200 260 140 200 320 ms
Watchdog Section
WDI Input High 0.7·
V
DD
WDI Input Low 0.3·
VDD
Watchdog Period C
WP = 64nF 1.12 1.60 2.08 0.96 1.60 2.56 s
0.7·
V
DD
0.3·
V
DD
V
V
Watchdog Pulse Width 50 50 ns
Output High Voltage I
Output Low Voltage I
SOURCE = 2mA VDD –
0.3
SINK = 2mA 0.1 0.1 V
VDD –
0.3
V
Note 1: This is the minimum supply voltage where RES is considered valid.
Note 2: Guaranteed by design.Not 100% tested in production.
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PIN DESCRIPTIONS
UCC1946
UCC2946
UCC3946
GND: Ground reference for the IC.
RES
: This pin is high only if the voltage on the RTH has
risen above 1.235V.Once RTH rises above the threshold,
this pin remains low for the reset period. This pin will also
go low and remain low if the RTH voltage dips below
1.235V for an amount of time determined by Figure 1.
RTH: This input compares its voltage to an internal 1.25V
reference. By using external resistors, a user can pro
gram any reset threshold he wishes to achieve.
RP: This pin allows the user to program the reset period
by adjusting an external capacitor.
APPLICATION INFORMATION
The UCC3946 supervisory circuit provides accurate re
set and watchdog functions for a variety of microproces
sor applications. The reset circuit prevents the
microprocessor from executing code during undervoltage
conditions, typically during power-up and power-down. In
order to prevent erratic operation in the presence of
noise, voltage “glitches” whose voltage amplitude and
time duration are less than the values specified in Fig. 1
are ignored.
VDD: Supply voltage for the IC.
WDI: This pin is the input to the watchdog timer. If this
pin is not toggled or strobed within the watchdog period,
is asserted.
WDO
WDO
: This pin is the watchdog output. This pin will be
asserted low if the WDI pin is not strobed or toggled
within the watchdog period.
-
WP: This pin allows the user to program the watchdog
period by adjusting an external capacitor.
-
-
The watchdog circuit monitors the microprocessor’s activity, if the microprocessor does not toggle WDI during
the programmable watchdog period WDO
will go low,
alerting the microprocessor’s interrupt of a fault. The
pin is typically connected to the non-maskable in
WDO
put of the microprocessor so that an error recovery rou
tine can be executed.
200
180
160
140
120
100
80
60
OVERDRIVE VOLTAGEWITH
40
GLITCHES ARE IGNORED,
20
RESPECT TORESET THRESHOLD (mV)
RESB REMAINS HIGH
0
100 110 120 130 140 150 160 170 180
RT SENSES GLITCH,
RES GOES LOW FOR RESET PERIOD
DELAY (µS)
Figure 1. Overdrive voltage vs. delay to output low
on RESB.
Slew rate:–1V/mS;monitored voltage = VDD.
-
-
Figure 2. Typical RTH threshold vs. temperature.
12.5
12
11.5
11
10.5
IDD (uA)
10
9.5
9
2345
VDD (V)
Figure 3. Typical IDD vs VDD.
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APPLICATION INFORMATION (cont.)
400nA
RP
4
VDD
C
RP
R1
RTH
2
R2
400nA
1.235V
POWER ON RESET
VDD
8
POWER TO
CIRCUITRY
3
UCC1946
UCC2946
UCC3946
RES
RESET
uP
WP
6
C
WDI
WP
1.235V
7
WATCHDOG TIMING
EDGE DETECT
100mV
Note: Pinout represents the 8-pin TSSOP package.
Figure 4. Typical application diagram.
Programming the Reset Voltage and Reset Period
The UCC3946 allows the reset trip voltage to be pro
grammed with two external resistors.In most applications
VDD is monitored by the reset circuit, however, the de
sign allows voltages other than VDD to be monitored.
Referring to Fig. 4, the voltage below which reset will be
asserted is determined by:
V =1.235 •
RESET
R1+ R2
R2
In order to keep quiescent currents low, resistor values in
the megaohm range can be used for R1 and R2. A man
ual reset can be easily implemented by connecting a mo
mentary push switch in parallel with R2. RES
guaranteed to be low with VDD voltages as low as 1V.
Once VDD rises above the programmed threshold, RES
remains low for the reset period defined by:
TCRP RP
=•3 125.
8-BIT COUNTER
A3
GND
1
5
WDO
NMI
A2
CLR
A1
A0
CLK
where T
in nanofarads. C
source of 400nA, a high quality, low leakage capacitor
(such as an NPO ceramic) should be used to maintain
timing tolerances. Fig. 5 illustrates the voltage levels and
RP is time in milliseconds and CRP is capacitance
RP is charged with a precision current
timings associated with the reset circuit.
Programming the Watchdog Period
The watchdog period is programmed with C
lows:
TCWP WP
=•25
-
where T
-
A high quality, low leakage capacitor should be used for
is
WP. The watchdog input WDI must be toggled with a
C
WP is in milliseconds and CWP is in nanofarads.
high/low or low/high transition within the watchdog period
to prevent WDO
from assuming a logic level low. WDO
will maintain the low logic level until WDI is toggled or
is asserted. If at any time RES is asserted, WDO
RES
will assume a high logic state and the watchdog period
will be reinitiated. Fig. 6 illustrates the timings associated
with the watchdog circuit.
I/O
UDG-98002
WP as fol
-
4
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APPLICATION INFORMATION (cont.)
Connecting WDO to RES
UCC1946
UCC2946
UCC3946
Layout Considerations
In order to provide design flexibility, the reset and watch
dog circuits in the UCC3946 have separate outputs. Each
output will independently drive high or low, depending on
circuit conditions explained previously.
In some applications, it may be desirable for either the
or WDO to reset the microprocessor. This can be
RES
done by connecting WDO
to RES. If the pins try to drive
to different output levels, the low output level will domi
nate.Additional current will flow from VDD to GND during
these states. If the application cannot support additional
current (during fault conditions), RES
and WDO can be
connected to the inputs of an OR gate whose output is
connected to the microprocessor’s reset pin.
-
A 0.1µF capacitor connected from V
DD to GND is recom
mended to decouple the UCC3946 from switching tran
sients on the V
DD supply rail.
Since RP and WP are precision current sources, capaci
tors C
RP and CWP should be connected to these pins
with minimal trace length to reduce board capacitance.
Care should be taken to route any traces with high volt
-
age potential or high speed digital signals away from
these capacitors.
Resistors R1 and R2 generally have a high ohmic value,
traces associated with these parts should be kept short
in order to prevent any transient producing signals from
coupling into the high impedance RTH pin.
-
-
-
-
t1: VDD> 1V, RES is guaranteed low.
t2: V
T
RP
t3: T
> programmed threshold, RES remains low for
DD
.
expires, RES pulls high.
RP
t4: Voltage glitch occurs, but is filtered at the RTH pin,
remains high.
RES
Figure 5. Reset circuit timings.
UDG-97067
t5: Voltage glitch occurs whose magnitude and duration
is greater than the RTH filter, RES
t6: On completion of the T
returned and RES
t7: V
dips below threshold (minus hysteresis), RES
DD
is pulled high.
RP
is asserted for TRP.
pulse the RTHvoltage has
is asserted.
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APPLICATION INFORMATION (cont.)
RESET
WDI
WDO
t1: Microprocessor is reset.
t2: WDI is toggled some time after reset, but before
WP expires.
T
t3: WDI is toggled before T
t4: WDI is toggled before T
t5: WDI is not toggled before T
serts low, triggering the microprocessor to enter an error recovery routine.
t6: The microprocessor’s error recovery routine is executed and WDI is toggled, reinitiating the watchdog
timer.
VDD
0V
V
DD
0V
DD
V
0V
TWP
t1
t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14
WP expires.
WP expires.
WP expires and WDO as-
UCC1946
UCC2946
UCC3946
T
RP
UDG-98007
t7: WDI is toggled before T
t8: WDI is toggled before T
t9: RES
for T
is momentarily triggered, RES is asserted low
RP.
t10: Microprocessor is reset, RES
t11: WDI is toggled some time after reset, but before
WP expires.
T
t12: WDI is toggled before T
t13: WDI is toggled before T
DD dips below the reset threshold, RES is as-
t14: V
serted.
WP expires.
WP expires.
pulls high.
WP expires.
WP expires.
Figure 6. Watchdog circuit timings.
UNITRODE CORPORATION
7 CONTINENTAL BLVD.• MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
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